Defined Constants and Types for the STM32L0xx Reset and Clock Control More...

Collaboration diagram for RCC Defines:

Data Structures
struct	rcc_clock_scale

Modules
	PLLDIV PLL division factor

	PLLMUL PLL multiplication factor

	RCC_CFGR APBx prescale factors
	These can be used for both APB1 and APB2 prescaling.

	RCC_CFGR AHB prescale Factors

	RCC_CFGR Deprecated dividers
	Older compatible definitions to ease migration.

	RCC_AHBRSTR reset values

	RCC_APB2RSTR reset values

	RCC_APB1RSTR reset values

	RCC_APHBENR enable values

	RCC_APPB2ENR enable values

	RCC_APB1ENR enable values

	I2C Clock source selections

	I2C for clock source selecting

	UART Clock source selections

	UART for clock source selecting

Macros
#define	RCC_CR MMIO32(RCC_BASE + 0x00)

#define	RCC_ICSCR MMIO32(RCC_BASE + 0x04)

#define	RCC_CRRCR MMIO32(RCC_BASE + 0x08)

#define	RCC_CFGR MMIO32(RCC_BASE + 0x0c)

#define	RCC_CIER MMIO32(RCC_BASE + 0x10)

#define	RCC_CIFR MMIO32(RCC_BASE + 0x14)

#define	RCC_CICR MMIO32(RCC_BASE + 0x18)

#define	RCC_IOPRSTR MMIO32(RCC_BASE + 0x1c)

#define	RCC_AHBRSTR MMIO32(RCC_BASE + 0x20)

#define	RCC_APB2RSTR MMIO32(RCC_BASE + 0x24)

#define	RCC_APB1RSTR MMIO32(RCC_BASE + 0x28)

#define	RCC_IOPENR MMIO32(RCC_BASE + 0x2c)

#define	RCC_AHBENR MMIO32(RCC_BASE + 0x30)

#define	RCC_APB2ENR MMIO32(RCC_BASE + 0x34)

#define	RCC_APB1ENR MMIO32(RCC_BASE + 0x38)

#define	RCC_IOPSMEN MMIO32(RCC_BASE + 0x3c)

#define	RCC_AHBSMENR MMIO32(RCC_BASE + 0x40)

#define	RCC_APB2SMENR MMIO32(RCC_BASE + 0x44)

#define	RCC_APB1SMENR MMIO32(RCC_BASE + 0x48)

#define	RCC_CCIPR MMIO32(RCC_BASE + 0x4c)

#define	RCC_CSR MMIO32(RCC_BASE + 0x50)

#define	RCC_CR_PLLRDY (1 << 25)

#define	RCC_CR_PLLON (1 << 24)

#define	RCC_CR_RTCPRE_SHIFT 20

#define	RCC_CR_RTCPRE_MASK 0x3

#define	RCC_CR_RTCPRE_DIV2 0

#define	RCC_CR_RTCPRE_DIV4 1

#define	RCC_CR_RTCPRE_DIV8 2

#define	RCC_CR_RTCPRE_DIV16 3

#define	RCC_CR_CSSHSEON (1 << 19)

#define	RCC_CR_HSEBYP (1 << 18)

#define	RCC_CR_HSERDY (1 << 17)

#define	RCC_CR_HSEON (1 << 16)

#define	RCC_CR_MSIRDY (1 << 9)

#define	RCC_CR_MSION (1 << 8)

#define	RCC_CR_HSI16DIVF (1 << 4)

#define	RCC_CR_HSI16DIVEN (1 << 3)

#define	RCC_CR_HSI16RDY (1 << 2)

#define	RCC_CR_HSI16KERON (1 << 1)

#define	RCC_CR_HSI16ON (1 << 0)

#define	RCC_ICSCR_MSITRIM_SHIFT 24

#define	RCC_ICSCR_MSITRIM_MASK 0xff

#define	RCC_ICSCR_MSICAL_SHIFT 16

#define	RCC_ICSCR_MSICAL_MASK 0xff

#define	RCC_ICSCR_MSIRANGE_SHIFT 13

#define	RCC_ICSCR_MSIRANGE_MASK 0x7

#define	RCC_ICSCR_MSIRANGE_65KHZ 0x0

#define	RCC_ICSCR_MSIRANGE_131KHZ 0x1

#define	RCC_ICSCR_MSIRANGE_262KHZ 0x2

#define	RCC_ICSCR_MSIRANGE_524KHZ 0x3

#define	RCC_ICSCR_MSIRANGE_1MHZ 0x4

#define	RCC_ICSCR_MSIRANGE_2MHZ 0x5

#define	RCC_ICSCR_MSIRANGE_4MHZ 0x6

#define	RCC_ICSCR_HSI16TRIM_SHIFT 8

#define	RCC_ICSCR_HSI16TRIM_MASK 0x1f

#define	RCC_ICSCR_HSI16CAL_SHIFT 0

#define	RCC_ICSCR_HSI16CAL_MASK 0xff

#define	RCC_CRRCR_HSI48CAL_SHIFT 8

#define	RCC_CRRCR_HSI48CAL_MASK 0xff

#define	RCC_CRRCR_HSI48RDY (1<<1)

#define	RCC_CRRCR_HSI48ON (1<<0)

#define	RCC_CFGR_MCOPRE_DIV1 0

#define	RCC_CFGR_MCOPRE_DIV2 1

#define	RCC_CFGR_MCOPRE_DIV4 2

#define	RCC_CFGR_MCOPRE_DIV8 3

#define	RCC_CFGR_MCOPRE_DIV16 4

#define	RCC_CFGR_MCO_NOCLK 0x0

#define	RCC_CFGR_MCO_SYSCLK 0x1

#define	RCC_CFGR_MCO_HSI16 0x2

#define	RCC_CFGR_MCO_MSI 0x3

#define	RCC_CFGR_MCO_HSE 0x4

#define	RCC_CFGR_MCO_PLL 0x5

#define	RCC_CFGR_MCO_LSI 0x6

#define	RCC_CFGR_MCO_LSE 0x7

#define	RCC_CFGR_MCO_HSI48 0x8

#define	RCC_CFGR_MCO_SHIFT 24

#define	RCC_CFGR_MCO_MASK 0xf

#define	RCC_CFGR_PLLDIV_SHIFT 22

#define	RCC_CFGR_PLLDIV_MASK 0x3

#define	RCC_CFGR_PLLMUL_SHIFT 18

#define	RCC_CFGR_PLLMUL_MASK 0xf

#define	RCC_CFGR_PLLSRC_HSI16_CLK 0x0

#define	RCC_CFGR_PLLSRC_HSE_CLK 0x1

#define	RCC_CFGR_STOPWUCK_MSI (0<<15)

#define	RCC_CFGR_STOPWUCK_HSI16 (1<<15)

#define	RCC_CFGR_PPRE2_SHIFT 11

#define	RCC_CFGR_PPRE2_MASK 0x7

#define	RCC_CFGR_PPRE1_SHIFT 8

#define	RCC_CFGR_PPRE1_MASK 0x7

#define	RCC_CFGR_HPRE_MASK 0xf

#define	RCC_CFGR_HPRE_SHIFT 4

#define	RCC_CFGR_SWS_MSI 0x0

#define	RCC_CFGR_SWS_HSI16 0x1

#define	RCC_CFGR_SWS_HSE 0x2

#define	RCC_CFGR_SWS_PLL 0x3

#define	RCC_CFGR_SWS_MASK 0x3

#define	RCC_CFGR_SWS_SHIFT 2

#define	RCC_CFGR_SW_MSI 0x0

#define	RCC_CFGR_SW_HSI16 0x1

#define	RCC_CFGR_SW_HSE 0x2

#define	RCC_CFGR_SW_PLL 0x3

#define	RCC_CFGR_SW_MASK 0x3

#define	RCC_CFGR_SW_SHIFT 0

#define	RCC_CIER_CSSLSE (1 << 7)

#define	RCC_CIER_HSI48RDYIE (1 << 6)

#define	RCC_CIER_MSIRDYIE (1 << 5)

#define	RCC_CIER_PLLRDYIE (1 << 4)

#define	RCC_CIER_HSERDYIE (1 << 3)

#define	RCC_CIER_HSI16RDYIE (1 << 2)

#define	RCC_CIER_LSERDYIE (1 << 1)

#define	RCC_CIER_LSIRDYIE (1 << 0)

#define	RCC_CIFR_CSSHSEF (1 << 8)

#define	RCC_CIFR_CSSLSEF (1 << 7)

#define	RCC_CIFR_HSI48RDYF (1 << 6)

#define	RCC_CIFR_MSIRDYF (1 << 5)

#define	RCC_CIFR_PLLRDYF (1 << 4)

#define	RCC_CIFR_HSERDYF (1 << 3)

#define	RCC_CIFR_HSI16RDYF (1 << 2)

#define	RCC_CIFR_LSERDYF (1 << 1)

#define	RCC_CIFR_LSIRDYF (1 << 0)

#define	RCC_CICR_CSSHSEC (1 << 8)

#define	RCC_CICR_CSSLSEC (1 << 7)

#define	RCC_CICR_HSI48RDYC (1 << 6)

#define	RCC_CICR_MSIRDYC (1 << 5)

#define	RCC_CICR_PLLRDYC (1 << 4)

#define	RCC_CICR_HSERDYC (1 << 3)

#define	RCC_CICR_HSI16RDYC (1 << 2)

#define	RCC_CICR_LSERDYC (1 << 1)

#define	RCC_CICR_LSIRDYC (1 << 0)

#define	RCC_IOPPRSTR_IOPHRST (1<<7)

#define	RCC_IOPPRSTR_IOPERST (1<<4)

#define	RCC_IOPPRSTR_IOPDRST (1<<3)

#define	RCC_IOPPRSTR_IOPCRST (1<<2)

#define	RCC_IOPPRSTR_IOPBRST (1<<1)

#define	RCC_IOPPRSTR_IOPARST (1<<0)

#define	RCC_IOPENR_IOPHEN (1<<7)

#define	RCC_IOPENR_IOPEEN (1<<4)

#define	RCC_IOPENR_IOPDEN (1<<3)

#define	RCC_IOPENR_IOPCEN (1<<2)

#define	RCC_IOPENR_IOPBEN (1<<1)

#define	RCC_IOPENR_IOPAEN (1<<0)

#define	RCC_IOPSMENR_IOPHSMEN (1<<7)

#define	RCC_IOPSMENR_IOPESMEN (1<<4)

#define	RCC_IOPSMENR_IOPDSMEN (1<<3)

#define	RCC_IOPSMENR_IOPCSMEN (1<<2)

#define	RCC_IOPSMENR_IOPBSMEN (1<<1)

#define	RCC_IOPSMENR_IOPASMEN (1<<0)

#define	RCC_AHBSMENR_CRYPSMEN (1 << 24)

#define	RCC_AHBSMENR_RNGSMEN (1 << 20)

#define	RCC_AHBSMENR_TSCSMEN (1 << 16)

#define	RCC_AHBSMENR_CRCSMEN (1 << 12)

#define	RCC_AHBSMENR_MIFSMEN (1 << 8)

#define	RCC_AHBSMENR_DMASMEN (1 << 0)

#define	RCC_APB2SMENR_DBGSMEN (1 << 22)

#define	RCC_APB2SMENR_USART1SMEN (1 << 14)

#define	RCC_APB2SMENR_SPI1SMEN (1 << 12)

#define	RCC_APB2SMENR_ADC1SMEN (1 << 9)

#define	RCC_APB2SMENR_MIFSMEN (1 << 7)

#define	RCC_APB2SMENR_TIM22SMEN (1 << 5)

#define	RCC_APB2SMENR_TIM21SMEN (1 << 2)

#define	RCC_APB2SMENR_SYSCFGSMEN (1 << 0)

#define	RCC_APB1SMENR_LPTIM1SMEN (1 << 31)

#define	RCC_APB1SMENR_I2C3SMEN (1 << 30)

#define	RCC_APB1SMENR_DACSMEN (1 << 29)

#define	RCC_APB1SMENR_PWRSMEN (1 << 28)

#define	RCC_APB1SMENR_CRSSMEN (1 << 27)

#define	RCC_APB1SMENR_USBSMEN (1 << 23)

#define	RCC_APB1SMENR_I2C2SMEN (1 << 22)

#define	RCC_APB1SMENR_I2C1SMEN (1 << 21)

#define	RCC_APB1SMENR_USART5SMEN (1 << 20)

#define	RCC_APB1SMENR_USART4SMEN (1 << 19)

#define	RCC_APB1SMENR_LPUART1SMEN (1 << 18)

#define	RCC_APB1SMENR_USART2SMEN (1 << 17)

#define	RCC_APB1SMENR_SPI2SMEN (1 << 14)

#define	RCC_APB1SMENR_WWDGSMEN (1 << 11)

#define	RCC_APB1SMENR_LCDSMEN (1 << 9)

#define	RCC_APB1SMENR_TIM7SMEN (1 << 5)

#define	RCC_APB1SMENR_TIM6SMEN (1 << 4)

#define	RCC_APB1SMENR_TIM3SMEN (1 << 1)

#define	RCC_APB1SMENR_TIM2SMEN (1 << 0)

#define	RCC_CCIPR_HSI48SEL (1<<26)

#define	RCC_CCIPR_LPTIM1SEL_APB 0

#define	RCC_CCIPR_LPTIM1SEL_LSI 1

#define	RCC_CCIPR_LPTIM1SEL_HSI16 2

#define	RCC_CCIPR_LPTIM1SEL_LSE 3

#define	RCC_CCIPR_LPTIM1SEL_SHIFT 18

#define	RCC_CCIPR_LPTIM1SEL_MASK 0x3

#define	RCC_CCIPR_I2CxSEL_MASK 0x3

#define	RCC_CCIPR_LPUARTxSEL_PCLK RCC_CCIPR_USARTxSEL_PCLK

#define	RCC_CCIPR_LPUARTxSEL_SYSCK RCC_CCIPR_USARTxSEL_SYSCLK

#define	RCC_CCIPR_LPUARTxSEL_HSI RCC_CCIPR_USARTxSEL_HSI

#define	RCC_CCIPR_LPUARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE

#define	RCC_CCIPR_LPUARTxSEL_MASK 0x3

#define	RCC_CCIPR_USARTxSEL_MASK RCC_CCIPR_LPUARTxSEL_MASK

#define	RCC_CSR_LPWRRSTF (1 << 31)

#define	RCC_CSR_WWDGRSTF (1 << 30)

#define	RCC_CSR_IWDGRSTF (1 << 29)

#define	RCC_CSR_SFTRSTF (1 << 28)

#define	RCC_CSR_PORRSTF (1 << 27)

#define	RCC_CSR_PINRSTF (1 << 26)

#define	RCC_CSR_OBLRSTF (1 << 25)

#define	RCC_CSR_FWRSTF (1 << 24)

#define	RCC_CSR_RMVF (1 << 23)

#define	RCC_CSR_RESET_FLAGS

#define	RCC_CSR_RTCRST (1 << 19)

#define	RCC_CSR_RTCEN (1 << 18)

#define	RCC_CSR_RTCSEL_SHIFT (16)

#define	RCC_CSR_RTCSEL_MASK (0x3)

#define	RCC_CSR_RTCSEL_NONE (0x0)

#define	RCC_CSR_RTCSEL_LSE (0x1)

#define	RCC_CSR_RTCSEL_LSI (0x2)

#define	RCC_CSR_RTCSEL_HSE (0x3)

#define	RCC_CSR_CSSLSED (1 << 14)

#define	RCC_CSR_CSSLSEON (1 << 13)

#define	RCC_CSR_LSEDRV_SHIFT 11

#define	RCC_CSR_LSEDRV_MASK 0x3

#define	RCC_CSR_LSEDRV_LOWEST 0

#define	RCC_CSR_LSEDRV_MLOW 1

#define	RCC_CSR_LSEDRV_MHIGH 2

#define	RCC_CSR_LSEDRV_HIGHEST 3

#define	RCC_CSR_LSEBYP (1 << 10)

#define	RCC_CSR_LSERDY (1 << 9)

#define	RCC_CSR_LSEON (1 << 8)

#define	RCC_CSR_LSIRDY (1 << 1)

#define	RCC_CSR_LSION (1 << 0)

#define	_REG_BIT(base, bit) (((base) << 5) + (bit))

Enumerations
enum	rcc_osc { RCC_PLL , RCC_HSE , RCC_HSI48 , RCC_HSI16 , RCC_MSI , RCC_LSE , RCC_LSI }

enum	rcc_periph_clken { RCC_GPIOA = _REG_BIT(0x2c, 0) , RCC_GPIOB = _REG_BIT(0x2c, 1) , RCC_GPIOC = _REG_BIT(0x2c, 2) , RCC_GPIOD = _REG_BIT(0x2c, 3) , RCC_GPIOE = _REG_BIT(0x2c, 4) , RCC_GPIOH = _REG_BIT(0x2c, 7) , RCC_DMA = _REG_BIT(0x30, 0) , RCC_MIF = _REG_BIT(0x30, 8) , RCC_CRC = _REG_BIT(0x30, 12) , RCC_TSC = _REG_BIT(0x30, 16) , RCC_RNG = _REG_BIT(0x30, 20) , RCC_CRYPT = _REG_BIT(0x30, 24) , RCC_SYSCFG = _REG_BIT(0x34, 0) , RCC_TIM21 = _REG_BIT(0x34, 2) , RCC_TIM22 = _REG_BIT(0x34, 5) , RCC_FW = _REG_BIT(0x34, 7) , RCC_ADC1 = _REG_BIT(0x34, 9) , RCC_SPI1 = _REG_BIT(0x34, 12) , RCC_USART1 = _REG_BIT(0x34, 14) , RCC_DBG = _REG_BIT(0x34, 22) , RCC_TIM2 = _REG_BIT(0x38, 0) , RCC_TIM3 = _REG_BIT(0x38, 1) , RCC_TIM6 = _REG_BIT(0x38, 4) , RCC_TIM7 = _REG_BIT(0x38, 5) , RCC_LCD = _REG_BIT(0x38, 9) , RCC_WWDG = _REG_BIT(0x38, 11) , RCC_SPI2 = _REG_BIT(0x38, 14) , RCC_USART2 = _REG_BIT(0x38, 17) , RCC_LPUART1 = _REG_BIT(0x38, 18) , RCC_USART4 = _REG_BIT(0x38, 19) , RCC_USART5 = _REG_BIT(0x38, 20) , RCC_I2C1 = _REG_BIT(0x38, 21) , RCC_I2C2 = _REG_BIT(0x38, 22) , RCC_USB = _REG_BIT(0x38, 23) , RCC_CRS = _REG_BIT(0x38, 27) , RCC_PWR = _REG_BIT(0x38, 28) , RCC_DAC = _REG_BIT(0x38, 29) , RCC_I2C3 = _REG_BIT(0x38, 30) , RCC_LPTIM1 = _REG_BIT(0x38, 31) , SCC_GPIOA = _REG_BIT(0x3c, 0) , SCC_GPIOB = _REG_BIT(0x3c, 1) , SCC_GPIOC = _REG_BIT(0x3c, 2) , SCC_GPIOD = _REG_BIT(0x3c, 3) , SCC_GPIOE = _REG_BIT(0x3c, 4) , SCC_GPIOH = _REG_BIT(0x3c, 7) , SCC_DMA = _REG_BIT(0x40, 0) , SCC_MIF = _REG_BIT(0x40, 8) , SCC_SRAM = _REG_BIT(0x40, 12) , SCC_CRC = _REG_BIT(0x40, 12) , SCC_TSC = _REG_BIT(0x40, 16) , SCC_RNG = _REG_BIT(0x40, 20) , SCC_CRYPT = _REG_BIT(0x40, 24) , SCC_SYSCFG = _REG_BIT(0x44, 0) , SCC_TIM21 = _REG_BIT(0x44, 2) , SCC_TIM22 = _REG_BIT(0x44, 5) , SCC_ADC1 = _REG_BIT(0x44, 9) , SCC_SPI1 = _REG_BIT(0x44, 12) , SCC_USART1 = _REG_BIT(0x44, 14) , SCC_DBG = _REG_BIT(0x44, 22) , SCC_TIM2 = _REG_BIT(0x48, 0) , SCC_TIM3 = _REG_BIT(0x48, 1) , SCC_TIM6 = _REG_BIT(0x48, 4) , SCC_TIM7 = _REG_BIT(0x48, 5) , SCC_LCD = _REG_BIT(0x48, 9) , SCC_WWDG = _REG_BIT(0x48, 11) , SCC_SPI2 = _REG_BIT(0x48, 14) , SCC_USART2 = _REG_BIT(0x48, 17) , SCC_LPUART1 = _REG_BIT(0x48, 18) , SCC_USART4 = _REG_BIT(0x48, 19) , SCC_USART5 = _REG_BIT(0x48, 20) , SCC_I2C1 = _REG_BIT(0x48, 21) , SCC_I2C2 = _REG_BIT(0x48, 22) , SCC_USB = _REG_BIT(0x48, 23) , SCC_CRS = _REG_BIT(0x48, 27) , SCC_PWR = _REG_BIT(0x48, 28) , SCC_DAC = _REG_BIT(0x48, 29) , SCC_I2C3 = _REG_BIT(0x48, 30) , SCC_LPTIM1 = _REG_BIT(0x48, 31) }

enum	rcc_periph_rst { RST_GPIOA = _REG_BIT(0x1c, 0) , RST_GPIOB = _REG_BIT(0x1c, 1) , RST_GPIOC = _REG_BIT(0x1c, 2) , RST_GPIOD = _REG_BIT(0x1c, 3) , RST_GPIOE = _REG_BIT(0x1c, 4) , RST_GPIOH = _REG_BIT(0x1c, 7) , RST_DMA = _REG_BIT(0x20, 0) , RST_MIF = _REG_BIT(0x20, 8) , RST_CRC = _REG_BIT(0x20, 12) , RST_TSC = _REG_BIT(0x20, 16) , RST_RNG = _REG_BIT(0x20, 20) , RST_CRYPT = _REG_BIT(0x20, 24) , RST_SYSCFG = _REG_BIT(0x24, 0) , RST_TIM21 = _REG_BIT(0x24, 2) , RST_TIM22 = _REG_BIT(0x24, 5) , RST_ADC1 = _REG_BIT(0x24, 9) , RST_SPI1 = _REG_BIT(0x24, 12) , RST_USART1 = _REG_BIT(0x24, 14) , RST_DBG = _REG_BIT(0x24, 22) , RST_TIM2 = _REG_BIT(0x28, 0) , RST_TIM3 = _REG_BIT(0x28, 1) , RST_TIM6 = _REG_BIT(0x28, 4) , RST_TIM7 = _REG_BIT(0x28, 5) , RST_LCD = _REG_BIT(0x28, 9) , RST_WWDG = _REG_BIT(0x28, 11) , RST_SPI2 = _REG_BIT(0x28, 14) , RST_USART2 = _REG_BIT(0x28, 17) , RST_LPUART1 = _REG_BIT(0x28, 18) , RST_USART4 = _REG_BIT(0x28, 19) , RST_USART5 = _REG_BIT(0x28, 20) , RST_I2C1 = _REG_BIT(0x28, 21) , RST_I2C2 = _REG_BIT(0x28, 22) , RST_USB = _REG_BIT(0x28, 23) , RST_CRS = _REG_BIT(0x28, 27) , RST_PWR = _REG_BIT(0x28, 28) , RST_DAC = _REG_BIT(0x28, 29) , RST_I2C3 = _REG_BIT(0x28, 30) , RST_LPTIM1 = _REG_BIT(0x28, 31) }

Functions
void	rcc_osc_on (enum rcc_osc osc)

void	rcc_osc_off (enum rcc_osc osc)

void	rcc_osc_ready_int_clear (enum rcc_osc osc)
	RCC Clear the Oscillator Ready Interrupt Flag. More...

void	rcc_osc_ready_int_enable (enum rcc_osc osc)
	RCC Enable the Oscillator Ready Interrupt. More...

void	rcc_osc_ready_int_disable (enum rcc_osc osc)
	RCC Disable the Oscillator Ready Interrupt. More...

int	rcc_osc_ready_int_flag (enum rcc_osc osc)
	RCC Read the Oscillator Ready Interrupt Flag. More...

void	rcc_set_hsi48_source_rc48 (void)
	RCC Set HSI48 clock source to the RC48 (CRS) More...

void	rcc_set_hsi48_source_pll (void)
	RCC Set HSI48 clock source to the PLL. More...

void	rcc_set_sysclk_source (enum rcc_osc osc)
	RCC Set the Source for the System Clock. More...

void	rcc_set_pll_multiplier (uint32_t factor)
	RCC Set the PLL Multiplication Factor. More...

void	rcc_set_pll_divider (uint32_t factor)
	RCC Set the PLL Division Factor. More...

void	rcc_set_pll_source (uint32_t pllsrc)
	Set the pll source. More...

void	rcc_set_ppre2 (uint32_t ppre2)
	RCC Set the APB2 Prescale Factor. More...

void	rcc_set_ppre1 (uint32_t ppre1)
	RCC Set the APB1 Prescale Factor. More...

void	rcc_set_hpre (uint32_t hpre)
	RCC Set the AHB Prescale Factor. More...

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
	RCC Setup PLL and use it as Sysclk source. More...

void	rcc_set_msi_range (uint32_t msi_range)
	Set the range of the MSI oscillator. More...

void	rcc_set_peripheral_clk_sel (uint32_t periph, uint32_t sel)
	Set the peripheral clock source. More...

void	rcc_set_lptim1_sel (uint32_t lptim1_sel)
	Set the LPTIM1 clock source. More...

void	rcc_set_lpuart1_sel (uint32_t lpupart1_sel)
	Set the LPUART1 clock source. More...

void	rcc_set_usart1_sel (uint32_t usart1_sel)
	Set the USART1 clock source. More...

void	rcc_set_usart2_sel (uint32_t usart2_sel)
	Set the USART2 clock source. More...

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the USART at base specified. More...

uint32_t	rcc_get_timer_clk_freq (uint32_t timer)
	Get the peripheral clock speed for the Timer at base specified. More...

uint32_t	rcc_get_i2c_clk_freq (uint32_t i2c)
	Get the peripheral clock speed for the I2C device at base specified. More...

uint32_t	rcc_get_spi_clk_freq (uint32_t spi)
	Get the peripheral clock speed for the SPI device at base specified. More...

void	rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Enable Peripheral Clocks. More...

void	rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Disable Peripheral Clocks. More...

void	rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
	RCC Reset Peripherals. More...

void	rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
	RCC Remove Reset on Peripherals. More...

void	rcc_periph_clock_enable (enum rcc_periph_clken clken)
	Enable Peripheral Clock in running mode. More...

void	rcc_periph_clock_disable (enum rcc_periph_clken clken)
	Disable Peripheral Clock in running mode. More...

void	rcc_periph_reset_pulse (enum rcc_periph_rst rst)
	Reset Peripheral, pulsed. More...

void	rcc_periph_reset_hold (enum rcc_periph_rst rst)
	Reset Peripheral, hold. More...

void	rcc_periph_reset_release (enum rcc_periph_rst rst)
	Reset Peripheral, release. More...

void	rcc_set_mco (uint32_t mcosrc)
	Select the source of Microcontroller Clock Output. More...

void	rcc_osc_bypass_enable (enum rcc_osc osc)
	RCC Enable Bypass. More...

void	rcc_osc_bypass_disable (enum rcc_osc osc)
	RCC Disable Bypass. More...

bool	rcc_is_osc_ready (enum rcc_osc osc)
	Is the given oscillator ready? More...

void	rcc_wait_for_osc_ready (enum rcc_osc osc)
	Wait for Oscillator Ready. More...

uint16_t	rcc_get_div_from_hpre (uint8_t div_val)
	This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...

Variables
uint32_t	rcc_ahb_frequency

uint32_t	rcc_apb1_frequency

uint32_t	rcc_apb2_frequency

Detailed Description

Defined Constants and Types for the STM32L0xx Reset and Clock Control

Version: 1.0.0

Author: © 2014 Karl Palsson karlp.nosp@m.@twe.nosp@m.ak.ne.nosp@m.t.au

Date: 17 November 2014

LGPL License Terms libopencm3 License

Author: © 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz

Macro Definition Documentation

◆ _REG_BIT

#define _REG_BIT	(	base,
		bit
	)	(((base) << 5) + (bit))

Definition at line 553 of file l0/rcc.h.

◆ RCC_AHBENR

#define RCC_AHBENR MMIO32(RCC_BASE + 0x30)

Definition at line 61 of file l0/rcc.h.

◆ RCC_AHBRSTR

#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x20)

Definition at line 57 of file l0/rcc.h.

◆ RCC_AHBSMENR

#define RCC_AHBSMENR MMIO32(RCC_BASE + 0x40)

Definition at line 65 of file l0/rcc.h.

◆ RCC_AHBSMENR_CRCSMEN

#define RCC_AHBSMENR_CRCSMEN (1 << 12)

Definition at line 398 of file l0/rcc.h.

◆ RCC_AHBSMENR_CRYPSMEN

#define RCC_AHBSMENR_CRYPSMEN (1 << 24)

Definition at line 395 of file l0/rcc.h.

◆ RCC_AHBSMENR_DMASMEN

#define RCC_AHBSMENR_DMASMEN (1 << 0)

Definition at line 400 of file l0/rcc.h.

◆ RCC_AHBSMENR_MIFSMEN

#define RCC_AHBSMENR_MIFSMEN (1 << 8)

Definition at line 399 of file l0/rcc.h.

◆ RCC_AHBSMENR_RNGSMEN

#define RCC_AHBSMENR_RNGSMEN (1 << 20)

Definition at line 396 of file l0/rcc.h.

◆ RCC_AHBSMENR_TSCSMEN

#define RCC_AHBSMENR_TSCSMEN (1 << 16)

Definition at line 397 of file l0/rcc.h.

◆ RCC_APB1ENR

#define RCC_APB1ENR MMIO32(RCC_BASE + 0x38)

Definition at line 63 of file l0/rcc.h.

◆ RCC_APB1RSTR

#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x28)

Definition at line 59 of file l0/rcc.h.

◆ RCC_APB1SMENR

#define RCC_APB1SMENR MMIO32(RCC_BASE + 0x48)

Definition at line 67 of file l0/rcc.h.

◆ RCC_APB1SMENR_CRSSMEN

#define RCC_APB1SMENR_CRSSMEN (1 << 27)

Definition at line 419 of file l0/rcc.h.

◆ RCC_APB1SMENR_DACSMEN

#define RCC_APB1SMENR_DACSMEN (1 << 29)

Definition at line 417 of file l0/rcc.h.

◆ RCC_APB1SMENR_I2C1SMEN

#define RCC_APB1SMENR_I2C1SMEN (1 << 21)

Definition at line 422 of file l0/rcc.h.

◆ RCC_APB1SMENR_I2C2SMEN

#define RCC_APB1SMENR_I2C2SMEN (1 << 22)

Definition at line 421 of file l0/rcc.h.

◆ RCC_APB1SMENR_I2C3SMEN

#define RCC_APB1SMENR_I2C3SMEN (1 << 30)

Definition at line 416 of file l0/rcc.h.

◆ RCC_APB1SMENR_LCDSMEN

#define RCC_APB1SMENR_LCDSMEN (1 << 9)

Definition at line 429 of file l0/rcc.h.

◆ RCC_APB1SMENR_LPTIM1SMEN

#define RCC_APB1SMENR_LPTIM1SMEN (1 << 31)

Definition at line 415 of file l0/rcc.h.

◆ RCC_APB1SMENR_LPUART1SMEN

#define RCC_APB1SMENR_LPUART1SMEN (1 << 18)

Definition at line 425 of file l0/rcc.h.

◆ RCC_APB1SMENR_PWRSMEN

#define RCC_APB1SMENR_PWRSMEN (1 << 28)

Definition at line 418 of file l0/rcc.h.

◆ RCC_APB1SMENR_SPI2SMEN

#define RCC_APB1SMENR_SPI2SMEN (1 << 14)

Definition at line 427 of file l0/rcc.h.

◆ RCC_APB1SMENR_TIM2SMEN

#define RCC_APB1SMENR_TIM2SMEN (1 << 0)

Definition at line 433 of file l0/rcc.h.

◆ RCC_APB1SMENR_TIM3SMEN

#define RCC_APB1SMENR_TIM3SMEN (1 << 1)

Definition at line 432 of file l0/rcc.h.

◆ RCC_APB1SMENR_TIM6SMEN

#define RCC_APB1SMENR_TIM6SMEN (1 << 4)

Definition at line 431 of file l0/rcc.h.

◆ RCC_APB1SMENR_TIM7SMEN

#define RCC_APB1SMENR_TIM7SMEN (1 << 5)

Definition at line 430 of file l0/rcc.h.

◆ RCC_APB1SMENR_USART2SMEN

#define RCC_APB1SMENR_USART2SMEN (1 << 17)

Definition at line 426 of file l0/rcc.h.

◆ RCC_APB1SMENR_USART4SMEN

#define RCC_APB1SMENR_USART4SMEN (1 << 19)

Definition at line 424 of file l0/rcc.h.

◆ RCC_APB1SMENR_USART5SMEN

#define RCC_APB1SMENR_USART5SMEN (1 << 20)

Definition at line 423 of file l0/rcc.h.

◆ RCC_APB1SMENR_USBSMEN

#define RCC_APB1SMENR_USBSMEN (1 << 23)

Definition at line 420 of file l0/rcc.h.

◆ RCC_APB1SMENR_WWDGSMEN

#define RCC_APB1SMENR_WWDGSMEN (1 << 11)

Definition at line 428 of file l0/rcc.h.

◆ RCC_APB2ENR

#define RCC_APB2ENR MMIO32(RCC_BASE + 0x34)

Definition at line 62 of file l0/rcc.h.

◆ RCC_APB2RSTR

#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24)

Definition at line 58 of file l0/rcc.h.

◆ RCC_APB2SMENR

#define RCC_APB2SMENR MMIO32(RCC_BASE + 0x44)

Definition at line 66 of file l0/rcc.h.

◆ RCC_APB2SMENR_ADC1SMEN

#define RCC_APB2SMENR_ADC1SMEN (1 << 9)

Definition at line 407 of file l0/rcc.h.

◆ RCC_APB2SMENR_DBGSMEN

#define RCC_APB2SMENR_DBGSMEN (1 << 22)

Definition at line 404 of file l0/rcc.h.

◆ RCC_APB2SMENR_MIFSMEN

#define RCC_APB2SMENR_MIFSMEN (1 << 7)

Definition at line 408 of file l0/rcc.h.

◆ RCC_APB2SMENR_SPI1SMEN

#define RCC_APB2SMENR_SPI1SMEN (1 << 12)

Definition at line 406 of file l0/rcc.h.

◆ RCC_APB2SMENR_SYSCFGSMEN

#define RCC_APB2SMENR_SYSCFGSMEN (1 << 0)

Definition at line 411 of file l0/rcc.h.

◆ RCC_APB2SMENR_TIM21SMEN

#define RCC_APB2SMENR_TIM21SMEN (1 << 2)

Definition at line 410 of file l0/rcc.h.

◆ RCC_APB2SMENR_TIM22SMEN

#define RCC_APB2SMENR_TIM22SMEN (1 << 5)

Definition at line 409 of file l0/rcc.h.

◆ RCC_APB2SMENR_USART1SMEN

#define RCC_APB2SMENR_USART1SMEN (1 << 14)

Definition at line 405 of file l0/rcc.h.

◆ RCC_CCIPR

#define RCC_CCIPR MMIO32(RCC_BASE + 0x4c)

Definition at line 68 of file l0/rcc.h.

◆ RCC_CCIPR_HSI48SEL

#define RCC_CCIPR_HSI48SEL (1<<26)

Definition at line 437 of file l0/rcc.h.

◆ RCC_CCIPR_I2CxSEL_MASK

#define RCC_CCIPR_I2CxSEL_MASK 0x3

Definition at line 453 of file l0/rcc.h.

◆ RCC_CCIPR_LPTIM1SEL_APB

#define RCC_CCIPR_LPTIM1SEL_APB 0

Definition at line 439 of file l0/rcc.h.

◆ RCC_CCIPR_LPTIM1SEL_HSI16

#define RCC_CCIPR_LPTIM1SEL_HSI16 2

Definition at line 441 of file l0/rcc.h.

◆ RCC_CCIPR_LPTIM1SEL_LSE

#define RCC_CCIPR_LPTIM1SEL_LSE 3

Definition at line 442 of file l0/rcc.h.

◆ RCC_CCIPR_LPTIM1SEL_LSI

#define RCC_CCIPR_LPTIM1SEL_LSI 1

Definition at line 440 of file l0/rcc.h.

◆ RCC_CCIPR_LPTIM1SEL_MASK

#define RCC_CCIPR_LPTIM1SEL_MASK 0x3

Definition at line 444 of file l0/rcc.h.

◆ RCC_CCIPR_LPTIM1SEL_SHIFT

#define RCC_CCIPR_LPTIM1SEL_SHIFT 18

Definition at line 443 of file l0/rcc.h.

◆ RCC_CCIPR_LPUARTxSEL_HSI

#define RCC_CCIPR_LPUARTxSEL_HSI RCC_CCIPR_USARTxSEL_HSI

Definition at line 474 of file l0/rcc.h.

◆ RCC_CCIPR_LPUARTxSEL_LSE

#define RCC_CCIPR_LPUARTxSEL_LSE RCC_CCIPR_USARTxSEL_LSE

Definition at line 475 of file l0/rcc.h.

◆ RCC_CCIPR_LPUARTxSEL_MASK

#define RCC_CCIPR_LPUARTxSEL_MASK 0x3

Definition at line 477 of file l0/rcc.h.

◆ RCC_CCIPR_LPUARTxSEL_PCLK

#define RCC_CCIPR_LPUARTxSEL_PCLK RCC_CCIPR_USARTxSEL_PCLK

Definition at line 472 of file l0/rcc.h.

◆ RCC_CCIPR_LPUARTxSEL_SYSCK

#define RCC_CCIPR_LPUARTxSEL_SYSCK RCC_CCIPR_USARTxSEL_SYSCLK

Definition at line 473 of file l0/rcc.h.

◆ RCC_CCIPR_USARTxSEL_MASK

#define RCC_CCIPR_USARTxSEL_MASK RCC_CCIPR_LPUARTxSEL_MASK

Definition at line 478 of file l0/rcc.h.

◆ RCC_CFGR

#define RCC_CFGR MMIO32(RCC_BASE + 0x0c)

Definition at line 52 of file l0/rcc.h.

◆ RCC_CFGR_HPRE_MASK

#define RCC_CFGR_HPRE_MASK 0xf

Definition at line 205 of file l0/rcc.h.

◆ RCC_CFGR_HPRE_SHIFT

#define RCC_CFGR_HPRE_SHIFT 4

Definition at line 206 of file l0/rcc.h.

◆ RCC_CFGR_MCO_HSE

#define RCC_CFGR_MCO_HSE 0x4

Definition at line 137 of file l0/rcc.h.

◆ RCC_CFGR_MCO_HSI16

#define RCC_CFGR_MCO_HSI16 0x2

Definition at line 135 of file l0/rcc.h.

◆ RCC_CFGR_MCO_HSI48

#define RCC_CFGR_MCO_HSI48 0x8

Definition at line 141 of file l0/rcc.h.

◆ RCC_CFGR_MCO_LSE

#define RCC_CFGR_MCO_LSE 0x7

Definition at line 140 of file l0/rcc.h.

◆ RCC_CFGR_MCO_LSI

#define RCC_CFGR_MCO_LSI 0x6

Definition at line 139 of file l0/rcc.h.

◆ RCC_CFGR_MCO_MASK

#define RCC_CFGR_MCO_MASK 0xf

Definition at line 143 of file l0/rcc.h.

◆ RCC_CFGR_MCO_MSI

#define RCC_CFGR_MCO_MSI 0x3

Definition at line 136 of file l0/rcc.h.

◆ RCC_CFGR_MCO_NOCLK

#define RCC_CFGR_MCO_NOCLK 0x0

Definition at line 133 of file l0/rcc.h.

◆ RCC_CFGR_MCO_PLL

#define RCC_CFGR_MCO_PLL 0x5

Definition at line 138 of file l0/rcc.h.

◆ RCC_CFGR_MCO_SHIFT

#define RCC_CFGR_MCO_SHIFT 24

Definition at line 142 of file l0/rcc.h.

◆ RCC_CFGR_MCO_SYSCLK

#define RCC_CFGR_MCO_SYSCLK 0x1

Definition at line 134 of file l0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV1

#define RCC_CFGR_MCOPRE_DIV1 0

Definition at line 126 of file l0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV16

#define RCC_CFGR_MCOPRE_DIV16 4

Definition at line 130 of file l0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV2

#define RCC_CFGR_MCOPRE_DIV2 1

Definition at line 127 of file l0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV4

#define RCC_CFGR_MCOPRE_DIV4 2

Definition at line 128 of file l0/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV8

#define RCC_CFGR_MCOPRE_DIV8 3

Definition at line 129 of file l0/rcc.h.

◆ RCC_CFGR_PLLDIV_MASK

#define RCC_CFGR_PLLDIV_MASK 0x3

Definition at line 152 of file l0/rcc.h.

◆ RCC_CFGR_PLLDIV_SHIFT

#define RCC_CFGR_PLLDIV_SHIFT 22

Definition at line 151 of file l0/rcc.h.

◆ RCC_CFGR_PLLMUL_MASK

#define RCC_CFGR_PLLMUL_MASK 0xf

Definition at line 167 of file l0/rcc.h.

◆ RCC_CFGR_PLLMUL_SHIFT

#define RCC_CFGR_PLLMUL_SHIFT 18

Definition at line 166 of file l0/rcc.h.

◆ RCC_CFGR_PLLSRC_HSE_CLK

#define RCC_CFGR_PLLSRC_HSE_CLK 0x1

Definition at line 171 of file l0/rcc.h.

◆ RCC_CFGR_PLLSRC_HSI16_CLK

#define RCC_CFGR_PLLSRC_HSI16_CLK 0x0

Definition at line 170 of file l0/rcc.h.

◆ RCC_CFGR_PPRE1_MASK

#define RCC_CFGR_PPRE1_MASK 0x7

Definition at line 180 of file l0/rcc.h.

◆ RCC_CFGR_PPRE1_SHIFT

#define RCC_CFGR_PPRE1_SHIFT 8

Definition at line 179 of file l0/rcc.h.

◆ RCC_CFGR_PPRE2_MASK

#define RCC_CFGR_PPRE2_MASK 0x7

Definition at line 178 of file l0/rcc.h.

◆ RCC_CFGR_PPRE2_SHIFT

#define RCC_CFGR_PPRE2_SHIFT 11

Definition at line 177 of file l0/rcc.h.

◆ RCC_CFGR_STOPWUCK_HSI16

#define RCC_CFGR_STOPWUCK_HSI16 (1<<15)

Definition at line 175 of file l0/rcc.h.

◆ RCC_CFGR_STOPWUCK_MSI

#define RCC_CFGR_STOPWUCK_MSI (0<<15)

Definition at line 174 of file l0/rcc.h.

◆ RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_HSE 0x2

Definition at line 219 of file l0/rcc.h.

◆ RCC_CFGR_SW_HSI16

#define RCC_CFGR_SW_HSI16 0x1

Definition at line 218 of file l0/rcc.h.

◆ RCC_CFGR_SW_MASK

#define RCC_CFGR_SW_MASK 0x3

Definition at line 221 of file l0/rcc.h.

◆ RCC_CFGR_SW_MSI

#define RCC_CFGR_SW_MSI 0x0

Definition at line 217 of file l0/rcc.h.

◆ RCC_CFGR_SW_PLL

#define RCC_CFGR_SW_PLL 0x3

Definition at line 220 of file l0/rcc.h.

◆ RCC_CFGR_SW_SHIFT

#define RCC_CFGR_SW_SHIFT 0

Definition at line 222 of file l0/rcc.h.

◆ RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_HSE 0x2

Definition at line 211 of file l0/rcc.h.

◆ RCC_CFGR_SWS_HSI16

#define RCC_CFGR_SWS_HSI16 0x1

Definition at line 210 of file l0/rcc.h.

◆ RCC_CFGR_SWS_MASK

#define RCC_CFGR_SWS_MASK 0x3

Definition at line 213 of file l0/rcc.h.

◆ RCC_CFGR_SWS_MSI

#define RCC_CFGR_SWS_MSI 0x0

Definition at line 209 of file l0/rcc.h.

◆ RCC_CFGR_SWS_PLL

#define RCC_CFGR_SWS_PLL 0x3

Definition at line 212 of file l0/rcc.h.

◆ RCC_CFGR_SWS_SHIFT

#define RCC_CFGR_SWS_SHIFT 2

Definition at line 214 of file l0/rcc.h.

◆ RCC_CICR

#define RCC_CICR MMIO32(RCC_BASE + 0x18)

Definition at line 55 of file l0/rcc.h.

◆ RCC_CICR_CSSHSEC

#define RCC_CICR_CSSHSEC (1 << 8)

Definition at line 268 of file l0/rcc.h.

◆ RCC_CICR_CSSLSEC

#define RCC_CICR_CSSLSEC (1 << 7)

Definition at line 269 of file l0/rcc.h.

◆ RCC_CICR_HSERDYC

#define RCC_CICR_HSERDYC (1 << 3)

Definition at line 273 of file l0/rcc.h.

◆ RCC_CICR_HSI16RDYC

#define RCC_CICR_HSI16RDYC (1 << 2)

Definition at line 274 of file l0/rcc.h.

◆ RCC_CICR_HSI48RDYC

#define RCC_CICR_HSI48RDYC (1 << 6)

Definition at line 270 of file l0/rcc.h.

◆ RCC_CICR_LSERDYC

#define RCC_CICR_LSERDYC (1 << 1)

Definition at line 275 of file l0/rcc.h.

◆ RCC_CICR_LSIRDYC

#define RCC_CICR_LSIRDYC (1 << 0)

Definition at line 276 of file l0/rcc.h.

◆ RCC_CICR_MSIRDYC

#define RCC_CICR_MSIRDYC (1 << 5)

Definition at line 271 of file l0/rcc.h.

◆ RCC_CICR_PLLRDYC

#define RCC_CICR_PLLRDYC (1 << 4)

Definition at line 272 of file l0/rcc.h.

◆ RCC_CIER

#define RCC_CIER MMIO32(RCC_BASE + 0x10)

Definition at line 53 of file l0/rcc.h.

◆ RCC_CIER_CSSLSE

#define RCC_CIER_CSSLSE (1 << 7)

Definition at line 244 of file l0/rcc.h.

◆ RCC_CIER_HSERDYIE

#define RCC_CIER_HSERDYIE (1 << 3)

Definition at line 249 of file l0/rcc.h.

◆ RCC_CIER_HSI16RDYIE

#define RCC_CIER_HSI16RDYIE (1 << 2)

Definition at line 250 of file l0/rcc.h.

◆ RCC_CIER_HSI48RDYIE

#define RCC_CIER_HSI48RDYIE (1 << 6)

Definition at line 246 of file l0/rcc.h.

◆ RCC_CIER_LSERDYIE

#define RCC_CIER_LSERDYIE (1 << 1)

Definition at line 251 of file l0/rcc.h.

◆ RCC_CIER_LSIRDYIE

#define RCC_CIER_LSIRDYIE (1 << 0)

Definition at line 252 of file l0/rcc.h.

◆ RCC_CIER_MSIRDYIE

#define RCC_CIER_MSIRDYIE (1 << 5)

Definition at line 247 of file l0/rcc.h.

◆ RCC_CIER_PLLRDYIE

#define RCC_CIER_PLLRDYIE (1 << 4)

Definition at line 248 of file l0/rcc.h.

◆ RCC_CIFR

#define RCC_CIFR MMIO32(RCC_BASE + 0x14)

Definition at line 54 of file l0/rcc.h.

◆ RCC_CIFR_CSSHSEF

#define RCC_CIFR_CSSHSEF (1 << 8)

Definition at line 256 of file l0/rcc.h.

◆ RCC_CIFR_CSSLSEF

#define RCC_CIFR_CSSLSEF (1 << 7)

Definition at line 257 of file l0/rcc.h.

◆ RCC_CIFR_HSERDYF

#define RCC_CIFR_HSERDYF (1 << 3)

Definition at line 261 of file l0/rcc.h.

◆ RCC_CIFR_HSI16RDYF

#define RCC_CIFR_HSI16RDYF (1 << 2)

Definition at line 262 of file l0/rcc.h.

◆ RCC_CIFR_HSI48RDYF

#define RCC_CIFR_HSI48RDYF (1 << 6)

Definition at line 258 of file l0/rcc.h.

◆ RCC_CIFR_LSERDYF

#define RCC_CIFR_LSERDYF (1 << 1)

Definition at line 263 of file l0/rcc.h.

◆ RCC_CIFR_LSIRDYF

#define RCC_CIFR_LSIRDYF (1 << 0)

Definition at line 264 of file l0/rcc.h.

◆ RCC_CIFR_MSIRDYF

#define RCC_CIFR_MSIRDYF (1 << 5)

Definition at line 259 of file l0/rcc.h.

◆ RCC_CIFR_PLLRDYF

#define RCC_CIFR_PLLRDYF (1 << 4)

Definition at line 260 of file l0/rcc.h.

◆ RCC_CR

#define RCC_CR MMIO32(RCC_BASE + 0x00)

Definition at line 49 of file l0/rcc.h.

◆ RCC_CR_CSSHSEON

#define RCC_CR_CSSHSEON (1 << 19)

Definition at line 81 of file l0/rcc.h.

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP (1 << 18)

Definition at line 82 of file l0/rcc.h.

◆ RCC_CR_HSEON

#define RCC_CR_HSEON (1 << 16)

Definition at line 84 of file l0/rcc.h.

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY (1 << 17)

Definition at line 83 of file l0/rcc.h.

◆ RCC_CR_HSI16DIVEN

#define RCC_CR_HSI16DIVEN (1 << 3)

Definition at line 88 of file l0/rcc.h.

◆ RCC_CR_HSI16DIVF

#define RCC_CR_HSI16DIVF (1 << 4)

Definition at line 87 of file l0/rcc.h.

◆ RCC_CR_HSI16KERON

#define RCC_CR_HSI16KERON (1 << 1)

Definition at line 90 of file l0/rcc.h.

◆ RCC_CR_HSI16ON

#define RCC_CR_HSI16ON (1 << 0)

Definition at line 91 of file l0/rcc.h.

◆ RCC_CR_HSI16RDY

#define RCC_CR_HSI16RDY (1 << 2)

Definition at line 89 of file l0/rcc.h.

◆ RCC_CR_MSION

#define RCC_CR_MSION (1 << 8)

Definition at line 86 of file l0/rcc.h.

◆ RCC_CR_MSIRDY

#define RCC_CR_MSIRDY (1 << 9)

Definition at line 85 of file l0/rcc.h.

◆ RCC_CR_PLLON

#define RCC_CR_PLLON (1 << 24)

Definition at line 74 of file l0/rcc.h.

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY (1 << 25)

Definition at line 73 of file l0/rcc.h.

◆ RCC_CR_RTCPRE_DIV16

#define RCC_CR_RTCPRE_DIV16 3

Definition at line 80 of file l0/rcc.h.

◆ RCC_CR_RTCPRE_DIV2

#define RCC_CR_RTCPRE_DIV2 0

Definition at line 77 of file l0/rcc.h.

◆ RCC_CR_RTCPRE_DIV4

#define RCC_CR_RTCPRE_DIV4 1

Definition at line 78 of file l0/rcc.h.

◆ RCC_CR_RTCPRE_DIV8

#define RCC_CR_RTCPRE_DIV8 2

Definition at line 79 of file l0/rcc.h.

◆ RCC_CR_RTCPRE_MASK

#define RCC_CR_RTCPRE_MASK 0x3

Definition at line 76 of file l0/rcc.h.

◆ RCC_CR_RTCPRE_SHIFT

#define RCC_CR_RTCPRE_SHIFT 20

Definition at line 75 of file l0/rcc.h.

◆ RCC_CRRCR

#define RCC_CRRCR MMIO32(RCC_BASE + 0x08)

Definition at line 51 of file l0/rcc.h.

◆ RCC_CRRCR_HSI48CAL_MASK

#define RCC_CRRCR_HSI48CAL_MASK 0xff

Definition at line 119 of file l0/rcc.h.

◆ RCC_CRRCR_HSI48CAL_SHIFT

#define RCC_CRRCR_HSI48CAL_SHIFT 8

Definition at line 118 of file l0/rcc.h.

◆ RCC_CRRCR_HSI48ON

#define RCC_CRRCR_HSI48ON (1<<0)

Definition at line 121 of file l0/rcc.h.

◆ RCC_CRRCR_HSI48RDY

#define RCC_CRRCR_HSI48RDY (1<<1)

Definition at line 120 of file l0/rcc.h.

◆ RCC_CSR

#define RCC_CSR MMIO32(RCC_BASE + 0x50)

Definition at line 69 of file l0/rcc.h.

◆ RCC_CSR_CSSLSED

#define RCC_CSR_CSSLSED (1 << 14)

Definition at line 511 of file l0/rcc.h.

◆ RCC_CSR_CSSLSEON

#define RCC_CSR_CSSLSEON (1 << 13)

Definition at line 512 of file l0/rcc.h.

◆ RCC_CSR_FWRSTF

#define RCC_CSR_FWRSTF (1 << 24)

Definition at line 498 of file l0/rcc.h.

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF (1 << 29)

Definition at line 493 of file l0/rcc.h.

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF (1 << 31)

Definition at line 491 of file l0/rcc.h.

◆ RCC_CSR_LSEBYP

#define RCC_CSR_LSEBYP (1 << 10)

Definition at line 519 of file l0/rcc.h.

◆ RCC_CSR_LSEDRV_HIGHEST

#define RCC_CSR_LSEDRV_HIGHEST 3

Definition at line 518 of file l0/rcc.h.

◆ RCC_CSR_LSEDRV_LOWEST

#define RCC_CSR_LSEDRV_LOWEST 0

Definition at line 515 of file l0/rcc.h.

◆ RCC_CSR_LSEDRV_MASK

#define RCC_CSR_LSEDRV_MASK 0x3

Definition at line 514 of file l0/rcc.h.

◆ RCC_CSR_LSEDRV_MHIGH

#define RCC_CSR_LSEDRV_MHIGH 2

Definition at line 517 of file l0/rcc.h.

◆ RCC_CSR_LSEDRV_MLOW

#define RCC_CSR_LSEDRV_MLOW 1

Definition at line 516 of file l0/rcc.h.

◆ RCC_CSR_LSEDRV_SHIFT

#define RCC_CSR_LSEDRV_SHIFT 11

Definition at line 513 of file l0/rcc.h.

◆ RCC_CSR_LSEON

#define RCC_CSR_LSEON (1 << 8)

Definition at line 521 of file l0/rcc.h.

◆ RCC_CSR_LSERDY

#define RCC_CSR_LSERDY (1 << 9)

Definition at line 520 of file l0/rcc.h.

◆ RCC_CSR_LSION

#define RCC_CSR_LSION (1 << 0)

Definition at line 523 of file l0/rcc.h.

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY (1 << 1)

Definition at line 522 of file l0/rcc.h.

◆ RCC_CSR_OBLRSTF

#define RCC_CSR_OBLRSTF (1 << 25)

Definition at line 497 of file l0/rcc.h.

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF (1 << 26)

Definition at line 496 of file l0/rcc.h.

◆ RCC_CSR_PORRSTF

#define RCC_CSR_PORRSTF (1 << 27)

Definition at line 495 of file l0/rcc.h.

◆ RCC_CSR_RESET_FLAGS

#define RCC_CSR_RESET_FLAGS

Value:

                (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\
                RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\
                RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF | RCC_CSR_FWRSTF)

Definition at line 500 of file l0/rcc.h.

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF (1 << 23)

Definition at line 499 of file l0/rcc.h.

◆ RCC_CSR_RTCEN

#define RCC_CSR_RTCEN (1 << 18)

Definition at line 504 of file l0/rcc.h.

◆ RCC_CSR_RTCRST

#define RCC_CSR_RTCRST (1 << 19)

Definition at line 503 of file l0/rcc.h.

◆ RCC_CSR_RTCSEL_HSE

#define RCC_CSR_RTCSEL_HSE (0x3)

Definition at line 510 of file l0/rcc.h.

◆ RCC_CSR_RTCSEL_LSE

#define RCC_CSR_RTCSEL_LSE (0x1)

Definition at line 508 of file l0/rcc.h.

◆ RCC_CSR_RTCSEL_LSI

#define RCC_CSR_RTCSEL_LSI (0x2)

Definition at line 509 of file l0/rcc.h.

◆ RCC_CSR_RTCSEL_MASK

#define RCC_CSR_RTCSEL_MASK (0x3)

Definition at line 506 of file l0/rcc.h.

◆ RCC_CSR_RTCSEL_NONE

#define RCC_CSR_RTCSEL_NONE (0x0)

Definition at line 507 of file l0/rcc.h.

◆ RCC_CSR_RTCSEL_SHIFT

#define RCC_CSR_RTCSEL_SHIFT (16)

Definition at line 505 of file l0/rcc.h.

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF (1 << 28)

Definition at line 494 of file l0/rcc.h.

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF (1 << 30)

Definition at line 492 of file l0/rcc.h.

◆ RCC_ICSCR

#define RCC_ICSCR MMIO32(RCC_BASE + 0x04)

Definition at line 50 of file l0/rcc.h.

◆ RCC_ICSCR_HSI16CAL_MASK

#define RCC_ICSCR_HSI16CAL_MASK 0xff

Definition at line 114 of file l0/rcc.h.

◆ RCC_ICSCR_HSI16CAL_SHIFT

#define RCC_ICSCR_HSI16CAL_SHIFT 0

Definition at line 113 of file l0/rcc.h.

◆ RCC_ICSCR_HSI16TRIM_MASK

#define RCC_ICSCR_HSI16TRIM_MASK 0x1f

Definition at line 112 of file l0/rcc.h.

◆ RCC_ICSCR_HSI16TRIM_SHIFT

#define RCC_ICSCR_HSI16TRIM_SHIFT 8

Definition at line 111 of file l0/rcc.h.

◆ RCC_ICSCR_MSICAL_MASK

#define RCC_ICSCR_MSICAL_MASK 0xff

Definition at line 99 of file l0/rcc.h.

◆ RCC_ICSCR_MSICAL_SHIFT

#define RCC_ICSCR_MSICAL_SHIFT 16

Definition at line 98 of file l0/rcc.h.

◆ RCC_ICSCR_MSIRANGE_131KHZ

#define RCC_ICSCR_MSIRANGE_131KHZ 0x1

Definition at line 104 of file l0/rcc.h.

◆ RCC_ICSCR_MSIRANGE_1MHZ

#define RCC_ICSCR_MSIRANGE_1MHZ 0x4

Definition at line 107 of file l0/rcc.h.

◆ RCC_ICSCR_MSIRANGE_262KHZ

#define RCC_ICSCR_MSIRANGE_262KHZ 0x2

Definition at line 105 of file l0/rcc.h.

◆ RCC_ICSCR_MSIRANGE_2MHZ

#define RCC_ICSCR_MSIRANGE_2MHZ 0x5

Definition at line 108 of file l0/rcc.h.

◆ RCC_ICSCR_MSIRANGE_4MHZ

#define RCC_ICSCR_MSIRANGE_4MHZ 0x6

Definition at line 109 of file l0/rcc.h.

◆ RCC_ICSCR_MSIRANGE_524KHZ

#define RCC_ICSCR_MSIRANGE_524KHZ 0x3

Definition at line 106 of file l0/rcc.h.

◆ RCC_ICSCR_MSIRANGE_65KHZ

#define RCC_ICSCR_MSIRANGE_65KHZ 0x0

Definition at line 103 of file l0/rcc.h.

◆ RCC_ICSCR_MSIRANGE_MASK

#define RCC_ICSCR_MSIRANGE_MASK 0x7

Definition at line 102 of file l0/rcc.h.

◆ RCC_ICSCR_MSIRANGE_SHIFT

#define RCC_ICSCR_MSIRANGE_SHIFT 13

Definition at line 101 of file l0/rcc.h.

◆ RCC_ICSCR_MSITRIM_MASK

#define RCC_ICSCR_MSITRIM_MASK 0xff

Definition at line 97 of file l0/rcc.h.

◆ RCC_ICSCR_MSITRIM_SHIFT

#define RCC_ICSCR_MSITRIM_SHIFT 24

Definition at line 96 of file l0/rcc.h.

◆ RCC_IOPENR

#define RCC_IOPENR MMIO32(RCC_BASE + 0x2c)

Definition at line 60 of file l0/rcc.h.

◆ RCC_IOPENR_IOPAEN

#define RCC_IOPENR_IOPAEN (1<<0)

Definition at line 338 of file l0/rcc.h.

◆ RCC_IOPENR_IOPBEN

#define RCC_IOPENR_IOPBEN (1<<1)

Definition at line 337 of file l0/rcc.h.

◆ RCC_IOPENR_IOPCEN

#define RCC_IOPENR_IOPCEN (1<<2)

Definition at line 336 of file l0/rcc.h.

◆ RCC_IOPENR_IOPDEN

#define RCC_IOPENR_IOPDEN (1<<3)

Definition at line 335 of file l0/rcc.h.

◆ RCC_IOPENR_IOPEEN

#define RCC_IOPENR_IOPEEN (1<<4)

Definition at line 334 of file l0/rcc.h.

◆ RCC_IOPENR_IOPHEN

#define RCC_IOPENR_IOPHEN (1<<7)

Definition at line 333 of file l0/rcc.h.

◆ RCC_IOPPRSTR_IOPARST

#define RCC_IOPPRSTR_IOPARST (1<<0)

Definition at line 285 of file l0/rcc.h.

◆ RCC_IOPPRSTR_IOPBRST

#define RCC_IOPPRSTR_IOPBRST (1<<1)

Definition at line 284 of file l0/rcc.h.

◆ RCC_IOPPRSTR_IOPCRST

#define RCC_IOPPRSTR_IOPCRST (1<<2)

Definition at line 283 of file l0/rcc.h.

◆ RCC_IOPPRSTR_IOPDRST

#define RCC_IOPPRSTR_IOPDRST (1<<3)

Definition at line 282 of file l0/rcc.h.

◆ RCC_IOPPRSTR_IOPERST

#define RCC_IOPPRSTR_IOPERST (1<<4)

Definition at line 281 of file l0/rcc.h.

◆ RCC_IOPPRSTR_IOPHRST

#define RCC_IOPPRSTR_IOPHRST (1<<7)

Definition at line 280 of file l0/rcc.h.

◆ RCC_IOPRSTR

#define RCC_IOPRSTR MMIO32(RCC_BASE + 0x1c)

Definition at line 56 of file l0/rcc.h.

◆ RCC_IOPSMEN

#define RCC_IOPSMEN MMIO32(RCC_BASE + 0x3c)

Definition at line 64 of file l0/rcc.h.

◆ RCC_IOPSMENR_IOPASMEN

#define RCC_IOPSMENR_IOPASMEN (1<<0)

Definition at line 391 of file l0/rcc.h.

◆ RCC_IOPSMENR_IOPBSMEN

#define RCC_IOPSMENR_IOPBSMEN (1<<1)

Definition at line 390 of file l0/rcc.h.

◆ RCC_IOPSMENR_IOPCSMEN

#define RCC_IOPSMENR_IOPCSMEN (1<<2)

Definition at line 389 of file l0/rcc.h.

◆ RCC_IOPSMENR_IOPDSMEN

#define RCC_IOPSMENR_IOPDSMEN (1<<3)

Definition at line 388 of file l0/rcc.h.

◆ RCC_IOPSMENR_IOPESMEN

#define RCC_IOPSMENR_IOPESMEN (1<<4)

Definition at line 387 of file l0/rcc.h.

◆ RCC_IOPSMENR_IOPHSMEN

#define RCC_IOPSMENR_IOPHSMEN (1<<7)

Definition at line 386 of file l0/rcc.h.

Enumeration Type Documentation

◆ rcc_osc

enum rcc_osc

Enumerator
RCC_PLL
RCC_HSE
RCC_HSI48
RCC_HSI16
RCC_MSI
RCC_LSE
RCC_LSI

Definition at line 548 of file l0/rcc.h.

◆ rcc_periph_clken

enum rcc_periph_clken

Enumerator
RCC_GPIOA
RCC_GPIOB
RCC_GPIOC
RCC_GPIOD
RCC_GPIOE
RCC_GPIOH
RCC_DMA
RCC_MIF
RCC_CRC
RCC_TSC
RCC_RNG
RCC_CRYPT
RCC_SYSCFG
RCC_TIM21
RCC_TIM22
RCC_FW
RCC_ADC1
RCC_SPI1
RCC_USART1
RCC_DBG
RCC_TIM2
RCC_TIM3
RCC_TIM6
RCC_TIM7
RCC_LCD
RCC_WWDG
RCC_SPI2
RCC_USART2
RCC_LPUART1
RCC_USART4
RCC_USART5
RCC_I2C1
RCC_I2C2
RCC_USB
RCC_CRS
RCC_PWR
RCC_DAC
RCC_I2C3
RCC_LPTIM1
SCC_GPIOA
SCC_GPIOB
SCC_GPIOC
SCC_GPIOD
SCC_GPIOE
SCC_GPIOH
SCC_DMA
SCC_MIF
SCC_SRAM
SCC_CRC
SCC_TSC
SCC_RNG
SCC_CRYPT
SCC_SYSCFG
SCC_TIM21
SCC_TIM22
SCC_ADC1
SCC_SPI1
SCC_USART1
SCC_DBG
SCC_TIM2
SCC_TIM3
SCC_TIM6
SCC_TIM7
SCC_LCD
SCC_WWDG
SCC_SPI2
SCC_USART2
SCC_LPUART1
SCC_USART4
SCC_USART5
SCC_I2C1
SCC_I2C2
SCC_USB
SCC_CRS
SCC_PWR
SCC_DAC
SCC_I2C3
SCC_LPTIM1

Definition at line 555 of file l0/rcc.h.

◆ rcc_periph_rst

enum rcc_periph_rst

Enumerator
RST_GPIOA
RST_GPIOB
RST_GPIOC
RST_GPIOD
RST_GPIOE
RST_GPIOH
RST_DMA
RST_MIF
RST_CRC
RST_TSC
RST_RNG
RST_CRYPT
RST_SYSCFG
RST_TIM21
RST_TIM22
RST_ADC1
RST_SPI1
RST_USART1
RST_DBG
RST_TIM2
RST_TIM3
RST_TIM6
RST_TIM7
RST_LCD
RST_WWDG
RST_SPI2
RST_USART2
RST_LPUART1
RST_USART4
RST_USART5
RST_I2C1
RST_I2C2
RST_USB
RST_CRS
RST_PWR
RST_DAC
RST_I2C3
RST_LPTIM1

Definition at line 651 of file l0/rcc.h.

Function Documentation

◆ rcc_clock_setup_pll()

void rcc_clock_setup_pll ( const struct rcc_clock_scale * clock )

RCC Setup PLL and use it as Sysclk source.

Parameters

[in] clock full struct with desired parameters

Definition at line 580 of file rcc.c.

References rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb1_frequency, rcc_clock_scale::apb2_frequency, flash_prefetch_enable(), flash_set_ws(), rcc_clock_scale::flash_waitstates, rcc_clock_scale::hpre, rcc_clock_scale::pll_div, rcc_clock_scale::pll_mul, rcc_clock_scale::pll_source, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, pwr_set_vos_scale(), rcc_ahb_frequency, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR_PLLSRC_HSE_CLK, RCC_HSE, RCC_HSI16, rcc_is_osc_ready(), rcc_osc_off(), rcc_osc_on(), rcc_periph_clock_enable(), RCC_PLL, RCC_PWR, rcc_set_hpre(), rcc_set_pll_divider(), rcc_set_pll_multiplier(), rcc_set_pll_source(), rcc_set_ppre1(), rcc_set_ppre2(), rcc_set_sysclk_source(), rcc_wait_for_osc_ready(), and rcc_clock_scale::voltage_scale.

Here is the call graph for this function:

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t div_val )

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters

div_val Masked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

Referenced by rcc_uart_i2c_clksel_freq_hz().

Here is the caller graph for this function:

◆ rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq ( uint32_t i2c )

Get the peripheral clock speed for the I2C device at base specified.

Parameters

i2c	Base address of I2C to get clock frequency for.

Definition at line 552 of file rcc.c.

References I2C1_BASE, I2C3_BASE, rcc_apb1_frequency, RCC_CCIPR_I2C1SEL_SHIFT, RCC_CCIPR_I2C3SEL_SHIFT, and rcc_uart_i2c_clksel_freq_hz().

Here is the call graph for this function:

◆ rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq ( uint32_t spi )

Get the peripheral clock speed for the SPI device at base specified.

Parameters

spi	Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).

Definition at line 567 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, and SPI1_BASE.

◆ rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq ( uint32_t timer )

Get the peripheral clock speed for the Timer at base specified.

Parameters

timer Base address of TIM to get clock frequency for.

Definition at line 533 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR, RCC_CFGR_PPRE1_MASK, RCC_CFGR_PPRE1_NODIV, RCC_CFGR_PPRE1_SHIFT, RCC_CFGR_PPRE2_MASK, RCC_CFGR_PPRE2_NODIV, RCC_CFGR_PPRE2_SHIFT, TIM2_BASE, and TIM7_BASE.

◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t usart )

Get the peripheral clock speed for the USART at base specified.

Parameters

usart Base address of USART to get clock frequency for.

Definition at line 518 of file rcc.c.

References LPUART1_BASE, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CCIPR_LPUART1SEL_SHIFT, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, rcc_uart_i2c_clksel_freq_hz(), and USART1_BASE.

Referenced by usart_set_baudrate().

Here is the call graph for this function:

Here is the caller graph for this function:

◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc osc )

Is the given oscillator ready?

Parameters

osc	Oscillator ID

Returns: true if the hardware indicates the oscillator is ready.

Definition at line 237 of file rcc.c.

References RCC_CR, RCC_CR_HSERDY, RCC_CR_HSI16RDY, RCC_CR_MSIRDY, RCC_CR_PLLRDY, RCC_CRRCR, RCC_CRRCR_HSI48RDY, RCC_CSR, RCC_CSR_LSERDY, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll(), and rcc_wait_for_osc_ready().

Here is the caller graph for this function:

◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc osc )

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc osc )

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_CSR_LSEBYP, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc osc )

Definition at line 74 of file rcc.c.

References RCC_CR, RCC_CRRCR, RCC_CSR, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc osc )

Definition at line 47 of file rcc.c.

References RCC_CR, RCC_CR_HSEON, RCC_CR_HSI16ON, RCC_CR_MSION, RCC_CR_PLLON, RCC_CRRCR, RCC_CRRCR_HSI48ON, RCC_CSR, RCC_CSR_LSEON, RCC_CSR_LSION, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc osc )

RCC Clear the Oscillator Ready Interrupt Flag.

Clear the interrupt flag that was set when a clock oscillator became ready to use.

Parameters

[in] osc Oscillator ID

Definition at line 110 of file rcc.c.

References RCC_CICR, RCC_CICR_HSERDYC, RCC_CICR_HSI16RDYC, RCC_CICR_HSI48RDYC, RCC_CICR_LSERDYC, RCC_CICR_LSIRDYC, RCC_CICR_MSIRDYC, RCC_CICR_PLLRDYC, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc osc )

RCC Disable the Oscillator Ready Interrupt.

Parameters

[in] osc Oscillator ID

Definition at line 174 of file rcc.c.

References RCC_CIER, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc osc )

RCC Enable the Oscillator Ready Interrupt.

Parameters

[in] osc Oscillator ID

Definition at line 142 of file rcc.c.

References RCC_CIER, RCC_CIER_HSERDYIE, RCC_CIER_HSI16RDYIE, RCC_CIER_HSI48RDYIE, RCC_CIER_LSERDYIE, RCC_CIER_LSIRDYIE, RCC_CIER_MSIRDYIE, RCC_CIER_PLLRDYIE, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc osc )

RCC Read the Oscillator Ready Interrupt Flag.

Parameters

[in] osc Oscillator ID

Returns: int. Boolean value for flag set.

Definition at line 207 of file rcc.c.

References cm3_assert_not_reached, RCC_CIFR, RCC_CIFR_HSERDYF, RCC_CIFR_HSI16RDYF, RCC_CIFR_HSI48RDYF, RCC_CIFR_LSERDYF, RCC_CIFR_LSIRDYF, RCC_CIFR_MSIRDYF, RCC_CIFR_PLLRDYF, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken clken )

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken clken )

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by crs_autotrim_usb_enable(), rcc_clock_setup_pll(), and st_usbfs_v2_usbd_init().

Here is the caller graph for this function:

◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst rst )

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst rst )

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst rst )

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset	(	volatile uint32_t *	reg,
		uint32_t	clear_reset
	)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	clear_reset	Unsigned int32. Logical OR of all resets to be removed: If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be used for disabling. If register is RCC_AHBENR, from RCC_APHBENR enable values If register is RCC_APB1ENR, from RCC_APB1ENR enable values If register is RCC_APB2ENR, from RCC_APPB2ENR enable values

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be set If register is RCC_AHBENR, from RCC_APHBENR enable values If register is RCC_APB1ENR, from RCC_APB1ENR enable values If register is RCC_APB2ENR, from RCC_APPB2ENR enable values

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset	(	volatile uint32_t *	reg,
		uint32_t	reset
	)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	reset	Unsigned int32. Logical OR of all resets. If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 88 of file rcc_common_all.c.

◆ rcc_set_hpre()

void rcc_set_hpre ( uint32_t hpre )

RCC Set the AHB Prescale Factor.

Parameters

[in] hpre Unsigned int32. AHB prescale factor RCC_CFGR AHB prescale Factors

Definition at line 387 of file rcc.c.

References RCC_CFGR, RCC_CFGR_HPRE_MASK, and RCC_CFGR_HPRE_SHIFT.

Referenced by rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_hsi48_source_pll()

void rcc_set_hsi48_source_pll ( void )

RCC Set HSI48 clock source to the PLL.

Definition at line 274 of file rcc.c.

References RCC_CCIPR.

◆ rcc_set_hsi48_source_rc48()

void rcc_set_hsi48_source_rc48 ( void )

RCC Set HSI48 clock source to the RC48 (CRS)

Definition at line 266 of file rcc.c.

References RCC_CCIPR, and RCC_CCIPR_HSI48SEL.

◆ rcc_set_lptim1_sel()

void rcc_set_lptim1_sel ( uint32_t lptim1_sel )

Set the LPTIM1 clock source.

Parameters

lptim1_sel peripheral clock source rcc_ccpipr_lptim1sel

Definition at line 409 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_MASK, and RCC_CCIPR_LPTIM1SEL_SHIFT.

◆ rcc_set_lpuart1_sel()

void rcc_set_lpuart1_sel ( uint32_t lpuart1_sel )

Set the LPUART1 clock source.

Parameters

lpuart1_sel periphral clock source rcc_ccpipr_lpuart1sel

Definition at line 421 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_SHIFT, and RCC_CCIPR_LPUARTxSEL_MASK.

◆ rcc_set_mco()

void rcc_set_mco ( uint32_t mcosrc )

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters

[in] mcosrc the unshifted source bits

Definition at line 191 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

◆ rcc_set_msi_range()

void rcc_set_msi_range ( uint32_t msi_range )

Set the range of the MSI oscillator.

Parameters

msi_range desired range rcc_icscr_msirange

Definition at line 398 of file rcc.c.

References RCC_ICSCR, RCC_ICSCR_MSIRANGE_MASK, and RCC_ICSCR_MSIRANGE_SHIFT.

◆ rcc_set_peripheral_clk_sel()

void rcc_set_peripheral_clk_sel	(	uint32_t	periph,
		uint32_t	sel
	)

Set the peripheral clock source.

Parameters

periph	peripheral of desire, eg XXX_BASE
sel	peripheral clock source

Definition at line 454 of file rcc.c.

References I2C1_BASE, I2C3_BASE, LPTIM1_BASE, LPUART1_BASE, RCC_CCIPR, RCC_CCIPR_I2C1SEL_SHIFT, RCC_CCIPR_I2C3SEL_SHIFT, RCC_CCIPR_I2CxSEL_MASK, RCC_CCIPR_LPTIM1SEL_MASK, RCC_CCIPR_LPTIM1SEL_SHIFT, RCC_CCIPR_LPUART1SEL_SHIFT, RCC_CCIPR_LPUARTxSEL_MASK, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, RCC_CCIPR_USARTxSEL_MASK, USART1_BASE, and USART2_BASE.

◆ rcc_set_pll_divider()

void rcc_set_pll_divider ( uint32_t factor )

RCC Set the PLL Division Factor.

Note: This only has effect when the PLL is disabled.

Parameters

[in] factor PLL multiplication factor PLLDIV PLL division factor

Definition at line 331 of file rcc.c.

References RCC_CFGR, RCC_CFGR_PLLDIV_MASK, and RCC_CFGR_PLLDIV_SHIFT.

Referenced by rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_pll_multiplier()

void rcc_set_pll_multiplier ( uint32_t factor )

RCC Set the PLL Multiplication Factor.

Note: This only has effect when the PLL is disabled.

Parameters

[in] factor PLL multiplication factor PLLMUL PLL multiplication factor

Definition at line 315 of file rcc.c.

References RCC_CFGR, RCC_CFGR_PLLMUL_MASK, and RCC_CFGR_PLLMUL_SHIFT.

Referenced by rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_pll_source()

void rcc_set_pll_source ( uint32_t pllsrc )

Set the pll source.

Parameters

pllsrc RCC_CFGR_PLLSRC_HSI16_CLK or RCC_CFGR_PLLSRC_HSE_CLK

Definition at line 342 of file rcc.c.

References RCC_CFGR, and RCC_CFGR_PLLSRC_HSE_CLK.

Referenced by rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_ppre1()

void rcc_set_ppre1 ( uint32_t ppre )

RCC Set the APB1 Prescale Factor.

Note: The APB1 clock frequency must not exceed 32MHz.

Parameters

[in] ppre APB prescale factor rcc_cfgr_apb1pre

Definition at line 359 of file rcc.c.

References RCC_CFGR, RCC_CFGR_PPRE1_MASK, and RCC_CFGR_PPRE1_SHIFT.

Referenced by rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_ppre2()

void rcc_set_ppre2 ( uint32_t ppre )

RCC Set the APB2 Prescale Factor.

Note: The APB2 clock frequency must not exceed 32MHz.

Parameters

[in] ppre APB prescale factor rcc_cfgr_apb2pre

Definition at line 374 of file rcc.c.

References RCC_CFGR, RCC_CFGR_PPRE2_MASK, and RCC_CFGR_PPRE2_SHIFT.

Referenced by rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_sysclk_source()

void rcc_set_sysclk_source ( enum rcc_osc osc )

RCC Set the Source for the System Clock.

Parameters

[in] osc Oscillator ID. Only HSE, HSI16, MSI and PLL have effect.

Definition at line 285 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SW_HSE, RCC_CFGR_SW_HSI16, RCC_CFGR_SW_MSI, RCC_CFGR_SW_PLL, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

Here is the caller graph for this function:

◆ rcc_set_usart1_sel()

void rcc_set_usart1_sel ( uint32_t usart1_sel )

Set the USART1 clock source.

Parameters

usart1_sel periphral clock source rcc_ccpipr_usart1sel

Definition at line 432 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_USART1SEL_SHIFT, and RCC_CCIPR_USARTxSEL_MASK.

◆ rcc_set_usart2_sel()

void rcc_set_usart2_sel ( uint32_t usart2_sel )

Set the USART2 clock source.

Parameters

usart2_sel periphral clock source rcc_ccpipr_usartxsel

Definition at line 443 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_USART2SEL_SHIFT, and RCC_CCIPR_USARTxSEL_MASK.

◆ rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready ( enum rcc_osc osc )

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters

osc	Oscillator ID

Definition at line 258 of file rcc.c.

References rcc_is_osc_ready().

Referenced by rcc_clock_setup_pll().

Here is the call graph for this function:

Here is the caller graph for this function:

Variable Documentation

◆ rcc_ahb_frequency

uint32_t rcc_ahb_frequency

extern

Definition at line 43 of file rcc.c.

Referenced by rcc_clock_setup_pll(), and rcc_uart_i2c_clksel_freq_hz().

◆ rcc_apb1_frequency

uint32_t rcc_apb1_frequency

extern

Definition at line 44 of file rcc.c.

Referenced by rcc_clock_setup_pll(), rcc_get_i2c_clk_freq(), rcc_get_spi_clk_freq(), rcc_get_timer_clk_freq(), and rcc_get_usart_clk_freq().

◆ rcc_apb2_frequency

uint32_t rcc_apb2_frequency

extern

Definition at line 45 of file rcc.c.

Referenced by rcc_clock_setup_pll(), rcc_get_spi_clk_freq(), rcc_get_timer_clk_freq(), and rcc_get_usart_clk_freq().

Data Structures

Modules

Macros

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ _REG_BIT

◆ RCC_AHBENR

◆ RCC_AHBRSTR

◆ RCC_AHBSMENR

◆ RCC_AHBSMENR_CRCSMEN

◆ RCC_AHBSMENR_CRYPSMEN

◆ RCC_AHBSMENR_DMASMEN

◆ RCC_AHBSMENR_MIFSMEN

◆ RCC_AHBSMENR_RNGSMEN

◆ RCC_AHBSMENR_TSCSMEN

◆ RCC_APB1ENR

◆ RCC_APB1RSTR

◆ RCC_APB1SMENR

◆ RCC_APB1SMENR_CRSSMEN

◆ RCC_APB1SMENR_DACSMEN

◆ RCC_APB1SMENR_I2C1SMEN

◆ RCC_APB1SMENR_I2C2SMEN

◆ RCC_APB1SMENR_I2C3SMEN

◆ RCC_APB1SMENR_LCDSMEN

◆ RCC_APB1SMENR_LPTIM1SMEN

◆ RCC_APB1SMENR_LPUART1SMEN

◆ RCC_APB1SMENR_PWRSMEN

◆ RCC_APB1SMENR_SPI2SMEN

◆ RCC_APB1SMENR_TIM2SMEN

◆ RCC_APB1SMENR_TIM3SMEN

◆ RCC_APB1SMENR_TIM6SMEN

◆ RCC_APB1SMENR_TIM7SMEN

◆ RCC_APB1SMENR_USART2SMEN

◆ RCC_APB1SMENR_USART4SMEN

◆ RCC_APB1SMENR_USART5SMEN

◆ RCC_APB1SMENR_USBSMEN

◆ RCC_APB1SMENR_WWDGSMEN

◆ RCC_APB2ENR

◆ RCC_APB2RSTR

◆ RCC_APB2SMENR

◆ RCC_APB2SMENR_ADC1SMEN

◆ RCC_APB2SMENR_DBGSMEN

◆ RCC_APB2SMENR_MIFSMEN

◆ RCC_APB2SMENR_SPI1SMEN

◆ RCC_APB2SMENR_SYSCFGSMEN

◆ RCC_APB2SMENR_TIM21SMEN

◆ RCC_APB2SMENR_TIM22SMEN

◆ RCC_APB2SMENR_USART1SMEN

◆ RCC_CCIPR

◆ RCC_CCIPR_HSI48SEL

◆ RCC_CCIPR_I2CxSEL_MASK

◆ RCC_CCIPR_LPTIM1SEL_APB

◆ RCC_CCIPR_LPTIM1SEL_HSI16

◆ RCC_CCIPR_LPTIM1SEL_LSE

◆ RCC_CCIPR_LPTIM1SEL_LSI

◆ RCC_CCIPR_LPTIM1SEL_MASK

◆ RCC_CCIPR_LPTIM1SEL_SHIFT

◆ RCC_CCIPR_LPUARTxSEL_HSI

◆ RCC_CCIPR_LPUARTxSEL_LSE

◆ RCC_CCIPR_LPUARTxSEL_MASK

◆ RCC_CCIPR_LPUARTxSEL_PCLK

◆ RCC_CCIPR_LPUARTxSEL_SYSCK

◆ RCC_CCIPR_USARTxSEL_MASK

◆ RCC_CFGR

◆ RCC_CFGR_HPRE_MASK

◆ RCC_CFGR_HPRE_SHIFT

◆ RCC_CFGR_MCO_HSE

◆ RCC_CFGR_MCO_HSI16

◆ RCC_CFGR_MCO_HSI48

◆ RCC_CFGR_MCO_LSE

◆ RCC_CFGR_MCO_LSI

◆ RCC_CFGR_MCO_MASK

◆ RCC_CFGR_MCO_MSI

◆ RCC_CFGR_MCO_NOCLK

◆ RCC_CFGR_MCO_PLL

◆ RCC_CFGR_MCO_SHIFT

◆ RCC_CFGR_MCO_SYSCLK