libopencm3 STM32L0xx Reset and Clock Control More...

Collaboration diagram for RCC peripheral API:

Macros
#define	_RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5))

#define	_RCC_BIT(i) (1 << ((i) & 0x1f))

Functions
void	rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Enable Peripheral Clocks. More...

void	rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Disable Peripheral Clocks. More...

void	rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
	RCC Reset Peripherals. More...

void	rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
	RCC Remove Reset on Peripherals. More...

void	rcc_periph_clock_enable (enum rcc_periph_clken clken)
	Enable Peripheral Clock in running mode. More...

void	rcc_periph_clock_disable (enum rcc_periph_clken clken)
	Disable Peripheral Clock in running mode. More...

void	rcc_periph_reset_pulse (enum rcc_periph_rst rst)
	Reset Peripheral, pulsed. More...

void	rcc_periph_reset_hold (enum rcc_periph_rst rst)
	Reset Peripheral, hold. More...

void	rcc_periph_reset_release (enum rcc_periph_rst rst)
	Reset Peripheral, release. More...

void	rcc_set_mco (uint32_t mcosrc)
	Select the source of Microcontroller Clock Output. More...

void	rcc_osc_bypass_enable (enum rcc_osc osc)
	RCC Enable Bypass. More...

void	rcc_osc_bypass_disable (enum rcc_osc osc)
	RCC Disable Bypass. More...

uint16_t	rcc_get_div_from_hpre (uint8_t div_val)
	This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...

void	rcc_osc_on (enum rcc_osc osc)

void	rcc_osc_off (enum rcc_osc osc)

void	rcc_osc_ready_int_clear (enum rcc_osc osc)
	RCC Clear the Oscillator Ready Interrupt Flag. More...

void	rcc_osc_ready_int_enable (enum rcc_osc osc)
	RCC Enable the Oscillator Ready Interrupt. More...

void	rcc_osc_ready_int_disable (enum rcc_osc osc)
	RCC Disable the Oscillator Ready Interrupt. More...

int	rcc_osc_ready_int_flag (enum rcc_osc osc)
	RCC Read the Oscillator Ready Interrupt Flag. More...

bool	rcc_is_osc_ready (enum rcc_osc osc)
	Is the given oscillator ready? More...

void	rcc_wait_for_osc_ready (enum rcc_osc osc)
	Wait for Oscillator Ready. More...

void	rcc_set_hsi48_source_rc48 (void)
	RCC Set HSI48 clock source to the RC48 (CRS) More...

void	rcc_set_hsi48_source_pll (void)
	RCC Set HSI48 clock source to the PLL. More...

void	rcc_set_sysclk_source (enum rcc_osc osc)
	RCC Set the Source for the System Clock. More...

void	rcc_set_pll_multiplier (uint32_t factor)
	RCC Set the PLL Multiplication Factor. More...

void	rcc_set_pll_divider (uint32_t factor)
	RCC Set the PLL Division Factor. More...

void	rcc_set_pll_source (uint32_t pllsrc)
	Set the pll source. More...

void	rcc_set_ppre1 (uint32_t ppre)
	RCC Set the APB1 Prescale Factor. More...

void	rcc_set_ppre2 (uint32_t ppre)
	RCC Set the APB2 Prescale Factor. More...

void	rcc_set_hpre (uint32_t hpre)
	RCC Set the AHB Prescale Factor. More...

void	rcc_set_msi_range (uint32_t msi_range)
	Set the range of the MSI oscillator. More...

void	rcc_set_lptim1_sel (uint32_t lptim1_sel)
	Set the LPTIM1 clock source. More...

void	rcc_set_lpuart1_sel (uint32_t lpuart1_sel)
	Set the LPUART1 clock source. More...

void	rcc_set_usart1_sel (uint32_t usart1_sel)
	Set the USART1 clock source. More...

void	rcc_set_usart2_sel (uint32_t usart2_sel)
	Set the USART2 clock source. More...

void	rcc_set_peripheral_clk_sel (uint32_t periph, uint32_t sel)
	Set the peripheral clock source. More...

static uint32_t	rcc_uart_i2c_clksel_freq_hz (uint32_t apb_clk, uint8_t shift)

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the USART at base specified. More...

uint32_t	rcc_get_timer_clk_freq (uint32_t timer)
	Get the peripheral clock speed for the Timer at base specified. More...

uint32_t	rcc_get_i2c_clk_freq (uint32_t i2c)
	Get the peripheral clock speed for the I2C device at base specified. More...

uint32_t	rcc_get_spi_clk_freq (uint32_t spi)
	Get the peripheral clock speed for the SPI device at base specified. More...

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
	RCC Setup PLL and use it as Sysclk source. More...

Variables
uint32_t	rcc_ahb_frequency = 2097000

uint32_t	rcc_apb1_frequency = 2097000

uint32_t	rcc_apb2_frequency = 2097000

Detailed Description

libopencm3 STM32L0xx Reset and Clock Control

Version: 1.0.0

Date: November 2014

This library supports the Reset and Clock Control System in the STM32F0xx series of ARM Cortex Microcontrollers by ST Microelectronics.

LGPL License Terms libopencm3 License

Macro Definition Documentation

◆ _RCC_BIT

#define _RCC_BIT ( i ) (1 << ((i) & 0x1f))

Definition at line 117 of file rcc_common_all.c.

◆ _RCC_REG

#define _RCC_REG ( i ) MMIO32(RCC_BASE + ((i) >> 5))

Definition at line 116 of file rcc_common_all.c.

Function Documentation

◆ rcc_clock_setup_pll()

void rcc_clock_setup_pll ( const struct rcc_clock_scale * clock )

RCC Setup PLL and use it as Sysclk source.

Parameters

[in] clock full struct with desired parameters

Definition at line 580 of file rcc.c.

References rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb1_frequency, rcc_clock_scale::apb2_frequency, flash_prefetch_enable(), flash_set_ws(), rcc_clock_scale::flash_waitstates, rcc_clock_scale::hpre, rcc_clock_scale::pll_div, rcc_clock_scale::pll_mul, rcc_clock_scale::pll_source, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, pwr_set_vos_scale(), rcc_ahb_frequency, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR_PLLSRC_HSE_CLK, RCC_HSE, RCC_HSI16, rcc_is_osc_ready(), rcc_osc_off(), rcc_osc_on(), rcc_periph_clock_enable(), RCC_PLL, RCC_PWR, rcc_set_hpre(), rcc_set_pll_divider(), rcc_set_pll_multiplier(), rcc_set_pll_source(), rcc_set_ppre1(), rcc_set_ppre2(), rcc_set_sysclk_source(), rcc_wait_for_osc_ready(), and rcc_clock_scale::voltage_scale.

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◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t div_val )

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters

div_val Masked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

Referenced by rcc_uart_i2c_clksel_freq_hz().

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◆ rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq ( uint32_t i2c )

Get the peripheral clock speed for the I2C device at base specified.

Parameters

i2c	Base address of I2C to get clock frequency for.

Definition at line 552 of file rcc.c.

References I2C1_BASE, I2C3_BASE, rcc_apb1_frequency, RCC_CCIPR_I2C1SEL_SHIFT, RCC_CCIPR_I2C3SEL_SHIFT, and rcc_uart_i2c_clksel_freq_hz().

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◆ rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq ( uint32_t spi )

Get the peripheral clock speed for the SPI device at base specified.

Parameters

spi	Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).

Definition at line 567 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, and SPI1_BASE.

◆ rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq ( uint32_t timer )

Get the peripheral clock speed for the Timer at base specified.

Parameters

timer Base address of TIM to get clock frequency for.

Definition at line 533 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR, RCC_CFGR_PPRE1_MASK, RCC_CFGR_PPRE1_NODIV, RCC_CFGR_PPRE1_SHIFT, RCC_CFGR_PPRE2_MASK, RCC_CFGR_PPRE2_NODIV, RCC_CFGR_PPRE2_SHIFT, TIM2_BASE, and TIM7_BASE.

◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t usart )

Get the peripheral clock speed for the USART at base specified.

Parameters

usart Base address of USART to get clock frequency for.

Definition at line 518 of file rcc.c.

References LPUART1_BASE, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CCIPR_LPUART1SEL_SHIFT, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, rcc_uart_i2c_clksel_freq_hz(), and USART1_BASE.

Referenced by usart_set_baudrate().

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◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc osc )

Is the given oscillator ready?

Parameters

osc	Oscillator ID

Returns: true if the hardware indicates the oscillator is ready.

Definition at line 237 of file rcc.c.

References RCC_CR, RCC_CR_HSERDY, RCC_CR_HSI16RDY, RCC_CR_MSIRDY, RCC_CR_PLLRDY, RCC_CRRCR, RCC_CRRCR_HSI48RDY, RCC_CSR, RCC_CSR_LSERDY, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll(), and rcc_wait_for_osc_ready().

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◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc osc )

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc osc )

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_CSR_LSEBYP, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc osc )

Definition at line 74 of file rcc.c.

References RCC_CR, RCC_CRRCR, RCC_CSR, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc osc )

Definition at line 47 of file rcc.c.

References RCC_CR, RCC_CR_HSEON, RCC_CR_HSI16ON, RCC_CR_MSION, RCC_CR_PLLON, RCC_CRRCR, RCC_CRRCR_HSI48ON, RCC_CSR, RCC_CSR_LSEON, RCC_CSR_LSION, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc osc )

RCC Clear the Oscillator Ready Interrupt Flag.

Clear the interrupt flag that was set when a clock oscillator became ready to use.

Parameters

[in] osc Oscillator ID

Definition at line 110 of file rcc.c.

References RCC_CICR, RCC_CICR_HSERDYC, RCC_CICR_HSI16RDYC, RCC_CICR_HSI48RDYC, RCC_CICR_LSERDYC, RCC_CICR_LSIRDYC, RCC_CICR_MSIRDYC, RCC_CICR_PLLRDYC, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc osc )

RCC Disable the Oscillator Ready Interrupt.

Parameters

[in] osc Oscillator ID

Definition at line 174 of file rcc.c.

References RCC_CIER, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc osc )

RCC Enable the Oscillator Ready Interrupt.

Parameters

[in] osc Oscillator ID

Definition at line 142 of file rcc.c.

References RCC_CIER, RCC_CIER_HSERDYIE, RCC_CIER_HSI16RDYIE, RCC_CIER_HSI48RDYIE, RCC_CIER_LSERDYIE, RCC_CIER_LSIRDYIE, RCC_CIER_MSIRDYIE, RCC_CIER_PLLRDYIE, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc osc )

RCC Read the Oscillator Ready Interrupt Flag.

Parameters

[in] osc Oscillator ID

Returns: int. Boolean value for flag set.

Definition at line 207 of file rcc.c.

References cm3_assert_not_reached, RCC_CIFR, RCC_CIFR_HSERDYF, RCC_CIFR_HSI16RDYF, RCC_CIFR_HSI48RDYF, RCC_CIFR_LSERDYF, RCC_CIFR_LSIRDYF, RCC_CIFR_MSIRDYF, RCC_CIFR_PLLRDYF, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken clken )

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken clken )

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by crs_autotrim_usb_enable(), rcc_clock_setup_pll(), and st_usbfs_v2_usbd_init().

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◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst rst )

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst rst )

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst rst )

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset	(	volatile uint32_t *	reg,
		uint32_t	clear_reset
	)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	clear_reset	Unsigned int32. Logical OR of all resets to be removed: If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be used for disabling. If register is RCC_AHBENR, from RCC_APHBENR enable values If register is RCC_APB1ENR, from RCC_APB1ENR enable values If register is RCC_APB2ENR, from RCC_APPB2ENR enable values

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be set If register is RCC_AHBENR, from RCC_APHBENR enable values If register is RCC_APB1ENR, from RCC_APB1ENR enable values If register is RCC_APB2ENR, from RCC_APPB2ENR enable values

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset	(	volatile uint32_t *	reg,
		uint32_t	reset
	)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	reset	Unsigned int32. Logical OR of all resets. If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 88 of file rcc_common_all.c.

◆ rcc_set_hpre()

void rcc_set_hpre ( uint32_t hpre )

RCC Set the AHB Prescale Factor.

Parameters

[in] hpre Unsigned int32. AHB prescale factor RCC_CFGR AHB prescale Factors

Definition at line 387 of file rcc.c.

References RCC_CFGR, RCC_CFGR_HPRE_MASK, and RCC_CFGR_HPRE_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_hsi48_source_pll()

void rcc_set_hsi48_source_pll ( void )

RCC Set HSI48 clock source to the PLL.

Definition at line 274 of file rcc.c.

References RCC_CCIPR.

◆ rcc_set_hsi48_source_rc48()

void rcc_set_hsi48_source_rc48 ( void )

RCC Set HSI48 clock source to the RC48 (CRS)

Definition at line 266 of file rcc.c.

References RCC_CCIPR, and RCC_CCIPR_HSI48SEL.

◆ rcc_set_lptim1_sel()

void rcc_set_lptim1_sel ( uint32_t lptim1_sel )

Set the LPTIM1 clock source.

Parameters

lptim1_sel peripheral clock source rcc_ccpipr_lptim1sel

Definition at line 409 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_MASK, and RCC_CCIPR_LPTIM1SEL_SHIFT.

◆ rcc_set_lpuart1_sel()

void rcc_set_lpuart1_sel ( uint32_t lpuart1_sel )

Set the LPUART1 clock source.

Parameters

lpuart1_sel periphral clock source rcc_ccpipr_lpuart1sel

Definition at line 421 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_SHIFT, and RCC_CCIPR_LPUARTxSEL_MASK.

◆ rcc_set_mco()

void rcc_set_mco ( uint32_t mcosrc )

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters

[in] mcosrc the unshifted source bits

Definition at line 191 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

◆ rcc_set_msi_range()

void rcc_set_msi_range ( uint32_t msi_range )

Set the range of the MSI oscillator.

Parameters

msi_range desired range rcc_icscr_msirange

Definition at line 398 of file rcc.c.

References RCC_ICSCR, RCC_ICSCR_MSIRANGE_MASK, and RCC_ICSCR_MSIRANGE_SHIFT.

◆ rcc_set_peripheral_clk_sel()

void rcc_set_peripheral_clk_sel	(	uint32_t	periph,
		uint32_t	sel
	)

Set the peripheral clock source.

Parameters

periph	peripheral of desire, eg XXX_BASE
sel	peripheral clock source

Definition at line 454 of file rcc.c.

References I2C1_BASE, I2C3_BASE, LPTIM1_BASE, LPUART1_BASE, RCC_CCIPR, RCC_CCIPR_I2C1SEL_SHIFT, RCC_CCIPR_I2C3SEL_SHIFT, RCC_CCIPR_I2CxSEL_MASK, RCC_CCIPR_LPTIM1SEL_MASK, RCC_CCIPR_LPTIM1SEL_SHIFT, RCC_CCIPR_LPUART1SEL_SHIFT, RCC_CCIPR_LPUARTxSEL_MASK, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, RCC_CCIPR_USARTxSEL_MASK, USART1_BASE, and USART2_BASE.

◆ rcc_set_pll_divider()

void rcc_set_pll_divider ( uint32_t factor )

RCC Set the PLL Division Factor.

Note: This only has effect when the PLL is disabled.

Parameters

[in] factor PLL multiplication factor PLLDIV PLL division factor

Definition at line 331 of file rcc.c.

References RCC_CFGR, RCC_CFGR_PLLDIV_MASK, and RCC_CFGR_PLLDIV_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_pll_multiplier()

void rcc_set_pll_multiplier ( uint32_t factor )

RCC Set the PLL Multiplication Factor.

Note: This only has effect when the PLL is disabled.

Parameters

[in] factor PLL multiplication factor PLLMUL PLL multiplication factor

Definition at line 315 of file rcc.c.

References RCC_CFGR, RCC_CFGR_PLLMUL_MASK, and RCC_CFGR_PLLMUL_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_pll_source()

void rcc_set_pll_source ( uint32_t pllsrc )

Set the pll source.

Parameters

pllsrc RCC_CFGR_PLLSRC_HSI16_CLK or RCC_CFGR_PLLSRC_HSE_CLK

Definition at line 342 of file rcc.c.

References RCC_CFGR, and RCC_CFGR_PLLSRC_HSE_CLK.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_ppre1()

void rcc_set_ppre1 ( uint32_t ppre )

RCC Set the APB1 Prescale Factor.

Note: The APB1 clock frequency must not exceed 32MHz.

Parameters

[in] ppre APB prescale factor rcc_cfgr_apb1pre

Definition at line 359 of file rcc.c.

References RCC_CFGR, RCC_CFGR_PPRE1_MASK, and RCC_CFGR_PPRE1_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_ppre2()

void rcc_set_ppre2 ( uint32_t ppre )

RCC Set the APB2 Prescale Factor.

Note: The APB2 clock frequency must not exceed 32MHz.

Parameters

[in] ppre APB prescale factor rcc_cfgr_apb2pre

Definition at line 374 of file rcc.c.

References RCC_CFGR, RCC_CFGR_PPRE2_MASK, and RCC_CFGR_PPRE2_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_sysclk_source()

void rcc_set_sysclk_source ( enum rcc_osc osc )

RCC Set the Source for the System Clock.

Parameters

[in] osc Oscillator ID. Only HSE, HSI16, MSI and PLL have effect.

Definition at line 285 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SW_HSE, RCC_CFGR_SW_HSI16, RCC_CFGR_SW_MSI, RCC_CFGR_SW_PLL, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_usart1_sel()

void rcc_set_usart1_sel ( uint32_t usart1_sel )

Set the USART1 clock source.

Parameters

usart1_sel periphral clock source rcc_ccpipr_usart1sel

Definition at line 432 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_USART1SEL_SHIFT, and RCC_CCIPR_USARTxSEL_MASK.

◆ rcc_set_usart2_sel()

void rcc_set_usart2_sel ( uint32_t usart2_sel )

Set the USART2 clock source.

Parameters

usart2_sel periphral clock source rcc_ccpipr_usartxsel

Definition at line 443 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_USART2SEL_SHIFT, and RCC_CCIPR_USARTxSEL_MASK.

◆ rcc_uart_i2c_clksel_freq_hz()

static uint32_t rcc_uart_i2c_clksel_freq_hz	(	uint32_t	apb_clk,
		uint8_t	shift
	)

static

Definition at line 500 of file rcc.c.

References cm3_assert_not_reached, rcc_ahb_frequency, RCC_CCIPR, RCC_CCIPR_I2CxSEL_MASK, RCC_CCIPR_USARTxSEL_HSI, RCC_CCIPR_USARTxSEL_PCLK, RCC_CCIPR_USARTxSEL_SYSCLK, RCC_CFGR, RCC_CFGR_HPRE_MASK, RCC_CFGR_HPRE_SHIFT, and rcc_get_div_from_hpre().

Referenced by rcc_get_i2c_clk_freq(), and rcc_get_usart_clk_freq().

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◆ rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready ( enum rcc_osc osc )

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters

osc	Oscillator ID

Definition at line 258 of file rcc.c.

References rcc_is_osc_ready().

Referenced by rcc_clock_setup_pll().

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Variable Documentation

◆ rcc_ahb_frequency

uint32_t rcc_ahb_frequency = 2097000

Definition at line 43 of file rcc.c.

Referenced by rcc_clock_setup_pll(), and rcc_uart_i2c_clksel_freq_hz().

◆ rcc_apb1_frequency

uint32_t rcc_apb1_frequency = 2097000

Definition at line 44 of file rcc.c.

Referenced by rcc_clock_setup_pll(), rcc_get_i2c_clk_freq(), rcc_get_spi_clk_freq(), rcc_get_timer_clk_freq(), and rcc_get_usart_clk_freq().

◆ rcc_apb2_frequency

uint32_t rcc_apb2_frequency = 2097000

Definition at line 45 of file rcc.c.

Referenced by rcc_clock_setup_pll(), rcc_get_spi_clk_freq(), rcc_get_timer_clk_freq(), and rcc_get_usart_clk_freq().

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ _RCC_BIT

◆ _RCC_REG

Function Documentation

◆ rcc_clock_setup_pll()

◆ rcc_get_div_from_hpre()

◆ rcc_get_i2c_clk_freq()

◆ rcc_get_spi_clk_freq()

◆ rcc_get_timer_clk_freq()

◆ rcc_get_usart_clk_freq()

◆ rcc_is_osc_ready()

◆ rcc_osc_bypass_disable()

◆ rcc_osc_bypass_enable()

◆ rcc_osc_off()

◆ rcc_osc_on()

◆ rcc_osc_ready_int_clear()

◆ rcc_osc_ready_int_disable()

◆ rcc_osc_ready_int_enable()

◆ rcc_osc_ready_int_flag()

◆ rcc_periph_clock_disable()

◆ rcc_periph_clock_enable()

◆ rcc_periph_reset_hold()

◆ rcc_periph_reset_pulse()

◆ rcc_periph_reset_release()

◆ rcc_peripheral_clear_reset()

◆ rcc_peripheral_disable_clock()

◆ rcc_peripheral_enable_clock()

◆ rcc_peripheral_reset()

◆ rcc_set_hpre()

◆ rcc_set_hsi48_source_pll()

◆ rcc_set_hsi48_source_rc48()

◆ rcc_set_lptim1_sel()

◆ rcc_set_lpuart1_sel()

◆ rcc_set_mco()

◆ rcc_set_msi_range()

◆ rcc_set_peripheral_clk_sel()

◆ rcc_set_pll_divider()

◆ rcc_set_pll_multiplier()

◆ rcc_set_pll_source()

◆ rcc_set_ppre1()

◆ rcc_set_ppre2()

◆ rcc_set_sysclk_source()

◆ rcc_set_usart1_sel()

◆ rcc_set_usart2_sel()

◆ rcc_uart_i2c_clksel_freq_hz()

◆ rcc_wait_for_osc_ready()

Variable Documentation

◆ rcc_ahb_frequency

◆ rcc_apb1_frequency

◆ rcc_apb2_frequency