Defined Constants and Types for the STM32L1xx Reset and Clock Control More...

Collaboration diagram for RCC Defines:

Data Structures
struct	rcc_clock_scale

Modules
	RCC_ICSCR definitions
	Internal clock sources calibration register.

	RCC_CFGR APBx prescale factors
	These can be used for both APB1 and APB2 prescaling.

	RCC_CFGR AHB prescale factors

	RCC_CFGR Deprecated dividers
	Older compatible definitions to ease migration.

	RCC_AHBRSTR reset values values

	RCC_APB2RSTR reset values values

	RCC_APB1RSTR reset values values

	RCC_AHBENR enable values

	RCC_APB2ENR enable values

	RCC_APB1ENR enable values

Macros
#define	RCC_CR MMIO32(RCC_BASE + 0x00)

#define	RCC_ICSCR MMIO32(RCC_BASE + 0x04)

#define	RCC_CFGR MMIO32(RCC_BASE + 0x08)

#define	RCC_CIR MMIO32(RCC_BASE + 0x0c)

#define	RCC_AHBRSTR MMIO32(RCC_BASE + 0x10)

#define	RCC_APB2RSTR MMIO32(RCC_BASE + 0x14)

#define	RCC_APB1RSTR MMIO32(RCC_BASE + 0x18)

#define	RCC_AHBENR MMIO32(RCC_BASE + 0x1c)

#define	RCC_APB2ENR MMIO32(RCC_BASE + 0x20)

#define	RCC_APB1ENR MMIO32(RCC_BASE + 0x24)

#define	RCC_AHBLPENR MMIO32(RCC_BASE + 0x28)

#define	RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c)

#define	RCC_APB1LPENR MMIO32(RCC_BASE + 0x30)

#define	RCC_CSR MMIO32(RCC_BASE + 0x34)

#define	RCC_CR_RTCPRE_SHIFT 29

#define	RCC_CR_RTCPRE_SHIFT 29

#define	RCC_CR_RTCPRE_MASK 0x3

#define	RCC_CR_RTCPRE_MASK 0x3

#define	RCC_CR_CSSON (1 << 28)

#define	RCC_CR_PLLRDY (1 << 25)

#define	RCC_CR_PLLON (1 << 24)

#define	RCC_CR_HSEBYP (1 << 18)

#define	RCC_CR_HSERDY (1 << 17)

#define	RCC_CR_HSEON (1 << 16)

#define	RCC_CR_MSIRDY (1 << 9)

#define	RCC_CR_MSION (1 << 8)

#define	RCC_CR_HSIRDY (1 << 1)

#define	RCC_CR_HSION (1 << 0)

#define	RCC_CR_RTCPRE_DIV2 0

#define	RCC_CR_RTCPRE_DIV4 1

#define	RCC_CR_RTCPRE_DIV8 2

#define	RCC_CR_RTCPRE_DIV16 3

#define	RCC_CFGR_MCOPRE_DIV1 0

#define	RCC_CFGR_MCOPRE_DIV2 1

#define	RCC_CFGR_MCOPRE_DIV4 2

#define	RCC_CFGR_MCOPRE_DIV8 3

#define	RCC_CFGR_MCOPRE_DIV16 4

#define	RCC_CFGR_MCOPRE_SHIFT 28

#define	RCC_CFGR_MCOPRE_MASK 0x7

#define	RCC_CFGR_MCO_NOCLK 0x0

#define	RCC_CFGR_MCO_SYSCLK 0x1

#define	RCC_CFGR_MCO_HSI 0x2

#define	RCC_CFGR_MCO_MSI 0x3

#define	RCC_CFGR_MCO_HSE 0x4

#define	RCC_CFGR_MCO_PLL 0x5

#define	RCC_CFGR_MCO_LSI 0x6

#define	RCC_CFGR_MCO_LSE 0x7

#define	RCC_CFGR_MCO_SHIFT 24

#define	RCC_CFGR_MCO_MASK 0x7

#define	RCC_CFGR_PLLDIV_DIV2 0x1

#define	RCC_CFGR_PLLDIV_DIV3 0x2

#define	RCC_CFGR_PLLDIV_DIV4 0x3

#define	RCC_CFGR_PLLDIV_SHIFT 22

#define	RCC_CFGR_PLLDIV_MASK 0x3

#define	RCC_CFGR_PLLMUL_MUL3 0x0

#define	RCC_CFGR_PLLMUL_MUL4 0x1

#define	RCC_CFGR_PLLMUL_MUL6 0x2

#define	RCC_CFGR_PLLMUL_MUL8 0x3

#define	RCC_CFGR_PLLMUL_MUL12 0x4

#define	RCC_CFGR_PLLMUL_MUL16 0x5

#define	RCC_CFGR_PLLMUL_MUL24 0x6

#define	RCC_CFGR_PLLMUL_MUL32 0x7

#define	RCC_CFGR_PLLMUL_MUL48 0x8

#define	RCC_CFGR_PLLMUL_SHIFT 18

#define	RCC_CFGR_PLLMUL_MASK 0xf

#define	RCC_CFGR_PLLSRC_HSI_CLK 0x0

#define	RCC_CFGR_PLLSRC_HSE_CLK 0x1

#define	RCC_CFGR_PPRE2_SHIFT 11

#define	RCC_CFGR_PPRE2_MASK 0x7

#define	RCC_CFGR_PPRE1_SHIFT 8

#define	RCC_CFGR_PPRE1_MASK 0x7

#define	RCC_CFGR_HPRE_MASK 0xf

#define	RCC_CFGR_HPRE_SHIFT 4

#define	RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0

#define	RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1

#define	RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2

#define	RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3

#define	RCC_CFGR_SWS_MASK 0x3

#define	RCC_CFGR_SWS_SHIFT 2

#define	RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0

#define	RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1

#define	RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2

#define	RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3

#define	RCC_CFGR_SW_MASK 0x3

#define	RCC_CFGR_SW_SHIFT 0

#define	RCC_CIR_CSSC (1 << 23)

#define	RCC_CIR_MSIRDYC (1 << 21)

#define	RCC_CIR_PLLRDYC (1 << 20)

#define	RCC_CIR_HSERDYC (1 << 19)

#define	RCC_CIR_HSIRDYC (1 << 18)

#define	RCC_CIR_LSERDYC (1 << 17)

#define	RCC_CIR_LSIRDYC (1 << 16)

#define	RCC_CIR_MSIRDYIE (1 << 13)

#define	RCC_CIR_PLLRDYIE (1 << 12)

#define	RCC_CIR_HSERDYIE (1 << 11)

#define	RCC_CIR_HSIRDYIE (1 << 10)

#define	RCC_CIR_LSERDYIE (1 << 9)

#define	RCC_CIR_LSIRDYIE (1 << 8)

#define	RCC_CIR_CSSF (1 << 7)

#define	RCC_CIR_MSIRDYF (1 << 5) /* (*) /

#define	RCC_CIR_PLLRDYF (1 << 4)

#define	RCC_CIR_HSERDYF (1 << 3)

#define	RCC_CIR_HSIRDYF (1 << 2)

#define	RCC_CIR_LSERDYF (1 << 1)

#define	RCC_CIR_LSIRDYF (1 << 0)

#define	RCC_AHBLPENR_DMA1LPEN (1 << 24)

#define	RCC_AHBLPENR_SRAMLPEN (1 << 16)

#define	RCC_AHBLPENR_FLITFLPEN (1 << 15)

#define	RCC_AHBLPENR_CRCLPEN (1 << 12)

#define	RCC_AHBLPENR_GPIOHLPEN (1 << 5)

#define	RCC_AHBLPENR_GPIOELPEN (1 << 4)

#define	RCC_AHBLPENR_GPIODLPEN (1 << 3)

#define	RCC_AHBLPENR_GPIOCLPEN (1 << 2)

#define	RCC_AHBLPENR_GPIOBLPEN (1 << 1)

#define	RCC_AHBLPENR_GPIOALPEN (1 << 0)

#define	RCC_APB2LPENR_USART1LPEN (1 << 14)

#define	RCC_APB2LPENR_SPI1LPEN (1 << 12)

#define	RCC_APB2LPENR_ADC1LPEN (1 << 9)

#define	RCC_APB2LPENR_TIM11LPEN (1 << 4)

#define	RCC_APB2LPENR_TIM10LPEN (1 << 3)

#define	RCC_APB2LPENR_TIM9LPEN (1 << 2)

#define	RCC_APB2LPENR_SYSCFGLPEN (1 << 0)

#define	RCC_APB1LPENR_COMPLPEN (1 << 31)

#define	RCC_APB1LPENR_DACLPEN (1 << 29)

#define	RCC_APB1LPENR_PWRLPEN (1 << 28)

#define	RCC_APB1LPENR_USBLPEN (1 << 23)

#define	RCC_APB1LPENR_I2C2LPEN (1 << 22)

#define	RCC_APB1LPENR_I2C1LPEN (1 << 21)

#define	RCC_APB1LPENR_USART3LPEN (1 << 18)

#define	RCC_APB1LPENR_USART2LPEN (1 << 17)

#define	RCC_APB1LPENR_SPI2LPEN (1 << 14)

#define	RCC_APB1LPENR_WWDGLPEN (1 << 11)

#define	RCC_APB1LPENR_LCDLPEN (1 << 9)

#define	RCC_APB1LPENR_TIM7LPEN (1 << 5)

#define	RCC_APB1LPENR_TIM6LPEN (1 << 4)

#define	RCC_APB1LPENR_TIM4LPEN (1 << 2)

#define	RCC_APB1LPENR_TIM3LPEN (1 << 1)

#define	RCC_APB1LPENR_TIM2LPEN (1 << 0)

#define	RCC_CSR_LPWRRSTF (1 << 31)

#define	RCC_CSR_WWDGRSTF (1 << 30)

#define	RCC_CSR_IWDGRSTF (1 << 29)

#define	RCC_CSR_SFTRSTF (1 << 28)

#define	RCC_CSR_PORRSTF (1 << 27)

#define	RCC_CSR_PINRSTF (1 << 26)

#define	RCC_CSR_OBLRSTF (1 << 25)

#define	RCC_CSR_RMVF (1 << 24)

#define	RCC_CSR_RESET_FLAGS

#define	RCC_CSR_RTCRST (1 << 23)

#define	RCC_CSR_RTCEN (1 << 22)

#define	RCC_CSR_RTCSEL_SHIFT (16)

#define	RCC_CSR_RTCSEL_MASK (0x3)

#define	RCC_CSR_RTCSEL_NONE (0x0)

#define	RCC_CSR_RTCSEL_LSE (0x1)

#define	RCC_CSR_RTCSEL_LSI (0x2)

#define	RCC_CSR_RTCSEL_HSE (0x3)

#define	RCC_CSR_LSECSSD (1 << 12)

#define	RCC_CSR_LSECSSON (1 << 11)

#define	RCC_CSR_LSEBYP (1 << 10)

#define	RCC_CSR_LSERDY (1 << 9)

#define	RCC_CSR_LSEON (1 << 8)

#define	RCC_CSR_LSIRDY (1 << 1)

#define	RCC_CSR_LSION (1 << 0)

#define	_REG_BIT(base, bit) (((base) << 5) + (bit))

Enumerations
enum	rcc_clock_config_entry { RCC_CLOCK_VRANGE1_HSI_PLL_24MHZ , RCC_CLOCK_VRANGE1_HSI_PLL_32MHZ , RCC_CLOCK_VRANGE1_HSI_RAW_16MHZ , RCC_CLOCK_VRANGE1_HSI_RAW_4MHZ , RCC_CLOCK_VRANGE1_MSI_RAW_4MHZ , RCC_CLOCK_VRANGE1_MSI_RAW_2MHZ , RCC_CLOCK_CONFIG_END }

enum	rcc_osc { RCC_PLL , RCC_HSE , RCC_HSI , RCC_MSI , RCC_LSE , RCC_LSI }

enum	rcc_periph_clken { RCC_GPIOA = _REG_BIT(0x1c, 0) , RCC_GPIOB = _REG_BIT(0x1c, 1) , RCC_GPIOC = _REG_BIT(0x1c, 2) , RCC_GPIOD = _REG_BIT(0x1c, 3) , RCC_GPIOE = _REG_BIT(0x1c, 4) , RCC_GPIOH = _REG_BIT(0x1c, 5) , RCC_GPIOF = _REG_BIT(0x1c, 6) , RCC_GPIOG = _REG_BIT(0x1c, 7) , RCC_CRC = _REG_BIT(0x1c, 12) , RCC_FLITF = _REG_BIT(0x1c, 15) , RCC_DMA1 = _REG_BIT(0x1c, 24) , RCC_DMA2 = _REG_BIT(0x1c, 25) , RCC_AES = _REG_BIT(0x1c, 27) , RCC_FSMC = _REG_BIT(0x1c, 30) , RCC_SYSCFG = _REG_BIT(0x20, 0) , RCC_TIM9 = _REG_BIT(0x20, 2) , RCC_TIM10 = _REG_BIT(0x20, 3) , RCC_TIM11 = _REG_BIT(0x20, 4) , RCC_ADC1 = _REG_BIT(0x20, 9) , RCC_SDIO = _REG_BIT(0x20, 11) , RCC_SPI1 = _REG_BIT(0x20, 12) , RCC_USART1 = _REG_BIT(0x20, 14) , RCC_TIM2 = _REG_BIT(0x24, 0) , RCC_TIM3 = _REG_BIT(0x24, 1) , RCC_TIM4 = _REG_BIT(0x24, 2) , RCC_TIM5 = _REG_BIT(0x24, 3) , RCC_TIM6 = _REG_BIT(0x24, 4) , RCC_TIM7 = _REG_BIT(0x24, 5) , RCC_LCD = _REG_BIT(0x24, 9) , RCC_WWDG = _REG_BIT(0x24, 11) , RCC_SPI2 = _REG_BIT(0x24, 14) , RCC_SPI3 = _REG_BIT(0x24, 15) , RCC_USART2 = _REG_BIT(0x24, 17) , RCC_USART3 = _REG_BIT(0x24, 18) , RCC_UART4 = _REG_BIT(0x24, 19) , RCC_UART5 = _REG_BIT(0x24, 20) , RCC_I2C1 = _REG_BIT(0x24, 21) , RCC_I2C2 = _REG_BIT(0x24, 22) , RCC_USB = _REG_BIT(0x24, 23) , RCC_PWR = _REG_BIT(0x24, 28) , RCC_DAC = _REG_BIT(0x24, 29) , RCC_COMP = _REG_BIT(0x24, 31) , SCC_GPIOA = _REG_BIT(0x28, 0) , SCC_GPIOB = _REG_BIT(0x28, 1) , SCC_GPIOC = _REG_BIT(0x28, 2) , SCC_GPIOD = _REG_BIT(0x28, 3) , SCC_GPIOE = _REG_BIT(0x28, 4) , SCC_GPIOH = _REG_BIT(0x28, 5) , SCC_GPIOF = _REG_BIT(0x28, 6) , SCC_GPIOG = _REG_BIT(0x28, 7) , SCC_CRC = _REG_BIT(0x28, 12) , SCC_FLITF = _REG_BIT(0x28, 15) , SCC_SRAM = _REG_BIT(0x28, 16) , SCC_DMA1 = _REG_BIT(0x28, 24) , SCC_DMA2 = _REG_BIT(0x28, 25) , SCC_AES = _REG_BIT(0x28, 27) , SCC_FSMC = _REG_BIT(0x28, 30) , SCC_SYSCFG = _REG_BIT(0x2c, 0) , SCC_TIM9 = _REG_BIT(0x2c, 2) , SCC_TIM10 = _REG_BIT(0x2c, 3) , SCC_TIM11 = _REG_BIT(0x2c, 4) , SCC_ADC1 = _REG_BIT(0x2c, 9) , SCC_SDIO = _REG_BIT(0x2c, 11) , SCC_SPI1 = _REG_BIT(0x2c, 12) , SCC_USART1 = _REG_BIT(0x2c, 14) , SCC_TIM2 = _REG_BIT(0x24, 0) , SCC_TIM3 = _REG_BIT(0x24, 1) , SCC_TIM4 = _REG_BIT(0x24, 2) , SCC_TIM5 = _REG_BIT(0x24, 3) , SCC_TIM6 = _REG_BIT(0x24, 4) , SCC_TIM7 = _REG_BIT(0x24, 5) , SCC_LCD = _REG_BIT(0x24, 9) , SCC_WWDG = _REG_BIT(0x24, 11) , SCC_SPI2 = _REG_BIT(0x24, 14) , SCC_SPI3 = _REG_BIT(0x24, 15) , SCC_USART2 = _REG_BIT(0x24, 17) , SCC_USART3 = _REG_BIT(0x24, 18) , SCC_UART4 = _REG_BIT(0x24, 19) , SCC_UART5 = _REG_BIT(0x24, 20) , SCC_I2C1 = _REG_BIT(0x24, 21) , SCC_I2C2 = _REG_BIT(0x24, 22) , SCC_USB = _REG_BIT(0x24, 23) , SCC_PWR = _REG_BIT(0x24, 28) , SCC_DAC = _REG_BIT(0x24, 29) , SCC_COMP = _REG_BIT(0x24, 31) }

enum	rcc_periph_rst { RST_GPIOA = _REG_BIT(0x10, 0) , RST_GPIOB = _REG_BIT(0x10, 1) , RST_GPIOC = _REG_BIT(0x10, 2) , RST_GPIOD = _REG_BIT(0x10, 3) , RST_GPIOE = _REG_BIT(0x10, 4) , RST_GPIOH = _REG_BIT(0x10, 5) , RST_GPIOF = _REG_BIT(0x10, 6) , RST_GPIOG = _REG_BIT(0x10, 7) , RST_CRC = _REG_BIT(0x10, 12) , RST_FLITF = _REG_BIT(0x10, 15) , RST_DMA1 = _REG_BIT(0x10, 24) , RST_DMA2 = _REG_BIT(0x10, 25) , RST_AES = _REG_BIT(0x10, 27) , RST_FSMC = _REG_BIT(0x10, 30) , RST_SYSCFG = _REG_BIT(0x14, 0) , RST_TIM9 = _REG_BIT(0x14, 2) , RST_TIM10 = _REG_BIT(0x14, 3) , RST_TIM11 = _REG_BIT(0x14, 4) , RST_ADC1 = _REG_BIT(0x14, 9) , RST_SDIO = _REG_BIT(0x14, 11) , RST_SPI1 = _REG_BIT(0x14, 12) , RST_USART1 = _REG_BIT(0x14, 14) , RST_TIM2 = _REG_BIT(0x18, 0) , RST_TIM3 = _REG_BIT(0x18, 1) , RST_TIM4 = _REG_BIT(0x18, 2) , RST_TIM5 = _REG_BIT(0x18, 3) , RST_TIM6 = _REG_BIT(0x18, 4) , RST_TIM7 = _REG_BIT(0x18, 5) , RST_LCD = _REG_BIT(0x18, 9) , RST_WWDG = _REG_BIT(0x18, 11) , RST_SPI2 = _REG_BIT(0x18, 14) , RST_SPI3 = _REG_BIT(0x18, 15) , RST_USART2 = _REG_BIT(0x18, 17) , RST_USART3 = _REG_BIT(0x18, 18) , RST_UART4 = _REG_BIT(0x18, 19) , RST_UART5 = _REG_BIT(0x18, 20) , RST_I2C1 = _REG_BIT(0x18, 21) , RST_I2C2 = _REG_BIT(0x18, 22) , RST_USB = _REG_BIT(0x18, 23) , RST_PWR = _REG_BIT(0x18, 28) , RST_DAC = _REG_BIT(0x18, 29) , RST_COMP = _REG_BIT(0x18, 31) }

Functions
void	rcc_osc_ready_int_clear (enum rcc_osc osc)

void	rcc_osc_ready_int_enable (enum rcc_osc osc)

void	rcc_osc_ready_int_disable (enum rcc_osc osc)

int	rcc_osc_ready_int_flag (enum rcc_osc osc)

void	rcc_css_int_clear (void)

int	rcc_css_int_flag (void)

void	rcc_wait_for_sysclk_status (enum rcc_osc osc)

void	rcc_osc_on (enum rcc_osc osc)

void	rcc_osc_off (enum rcc_osc osc)

void	rcc_css_enable (void)

void	rcc_css_disable (void)

void	rcc_set_msi_range (uint32_t range)
	Set the range of the MSI oscillator. More...

void	rcc_set_sysclk_source (uint32_t clk)

void	rcc_set_pll_configuration (uint32_t source, uint32_t multiplier, uint32_t divisor)

void	rcc_set_pll_source (uint32_t pllsrc)

void	rcc_set_adcpre (uint32_t adcpre)

void	rcc_set_ppre2 (uint32_t ppre2)

void	rcc_set_ppre1 (uint32_t ppre1)

void	rcc_set_hpre (uint32_t hpre)

void	rcc_set_usbpre (uint32_t usbpre)

void	rcc_set_rtcpre (uint32_t rtcpre)

uint32_t	rcc_system_clock_source (void)

void	rcc_rtc_select_clock (uint32_t clock)

void	rcc_clock_setup_msi (const struct rcc_clock_scale *clock)

void	rcc_clock_setup_hsi (const struct rcc_clock_scale *clock)
	Switch sysclock to HSI with the given parameters. More...

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)

void	rcc_backupdomain_reset (void)

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the USART at base specified. More...

uint32_t	rcc_get_timer_clk_freq (uint32_t timer)
	Get the peripheral clock speed for the Timer at base specified. More...

uint32_t	rcc_get_i2c_clk_freq (uint32_t i2c)
	Get the peripheral clock speed for the I2C device at base specified. More...

uint32_t	rcc_get_spi_clk_freq (uint32_t spi)
	Get the peripheral clock speed for the SPI device at base specified. More...

void	rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Enable Peripheral Clocks. More...

void	rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Disable Peripheral Clocks. More...

void	rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
	RCC Reset Peripherals. More...

void	rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
	RCC Remove Reset on Peripherals. More...

void	rcc_periph_clock_enable (enum rcc_periph_clken clken)
	Enable Peripheral Clock in running mode. More...

void	rcc_periph_clock_disable (enum rcc_periph_clken clken)
	Disable Peripheral Clock in running mode. More...

void	rcc_periph_reset_pulse (enum rcc_periph_rst rst)
	Reset Peripheral, pulsed. More...

void	rcc_periph_reset_hold (enum rcc_periph_rst rst)
	Reset Peripheral, hold. More...

void	rcc_periph_reset_release (enum rcc_periph_rst rst)
	Reset Peripheral, release. More...

void	rcc_set_mco (uint32_t mcosrc)
	Select the source of Microcontroller Clock Output. More...

void	rcc_osc_bypass_enable (enum rcc_osc osc)
	RCC Enable Bypass. More...

void	rcc_osc_bypass_disable (enum rcc_osc osc)
	RCC Disable Bypass. More...

bool	rcc_is_osc_ready (enum rcc_osc osc)
	Is the given oscillator ready? More...

void	rcc_wait_for_osc_ready (enum rcc_osc osc)
	Wait for Oscillator Ready. More...

uint16_t	rcc_get_div_from_hpre (uint8_t div_val)
	This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...

Variables
const struct rcc_clock_scale	rcc_clock_config [RCC_CLOCK_CONFIG_END]

uint32_t	rcc_ahb_frequency

uint32_t	rcc_apb1_frequency

uint32_t	rcc_apb2_frequency

Detailed Description

Defined Constants and Types for the STM32L1xx Reset and Clock Control

Version: 1.0.0

Author: © 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>; © 2009 Uwe Hermann uwe@h.nosp@m.erma.nosp@m.nn-uw.nosp@m.e.de; © 2012 Karl Palsson karlp.nosp@m.@twe.nosp@m.ak.ne.nosp@m.t.au

Date: 11 November 2012

LGPL License Terms libopencm3 License

Author: © 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz

Macro Definition Documentation

◆ _REG_BIT

#define _REG_BIT	(	base,
		bit
	)	(((base) << 5) + (bit))

Definition at line 481 of file l1/rcc.h.

◆ RCC_AHBENR

#define RCC_AHBENR MMIO32(RCC_BASE + 0x1c)

Definition at line 62 of file l1/rcc.h.

◆ RCC_AHBLPENR

#define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28)

Definition at line 65 of file l1/rcc.h.

◆ RCC_AHBLPENR_CRCLPEN

#define RCC_AHBLPENR_CRCLPEN (1 << 12)

Definition at line 379 of file l1/rcc.h.

◆ RCC_AHBLPENR_DMA1LPEN

#define RCC_AHBLPENR_DMA1LPEN (1 << 24)

Definition at line 376 of file l1/rcc.h.

◆ RCC_AHBLPENR_FLITFLPEN

#define RCC_AHBLPENR_FLITFLPEN (1 << 15)

Definition at line 378 of file l1/rcc.h.

◆ RCC_AHBLPENR_GPIOALPEN

#define RCC_AHBLPENR_GPIOALPEN (1 << 0)

Definition at line 385 of file l1/rcc.h.

◆ RCC_AHBLPENR_GPIOBLPEN

#define RCC_AHBLPENR_GPIOBLPEN (1 << 1)

Definition at line 384 of file l1/rcc.h.

◆ RCC_AHBLPENR_GPIOCLPEN

#define RCC_AHBLPENR_GPIOCLPEN (1 << 2)

Definition at line 383 of file l1/rcc.h.

◆ RCC_AHBLPENR_GPIODLPEN

#define RCC_AHBLPENR_GPIODLPEN (1 << 3)

Definition at line 382 of file l1/rcc.h.

◆ RCC_AHBLPENR_GPIOELPEN

#define RCC_AHBLPENR_GPIOELPEN (1 << 4)

Definition at line 381 of file l1/rcc.h.

◆ RCC_AHBLPENR_GPIOHLPEN

#define RCC_AHBLPENR_GPIOHLPEN (1 << 5)

Definition at line 380 of file l1/rcc.h.

◆ RCC_AHBLPENR_SRAMLPEN

#define RCC_AHBLPENR_SRAMLPEN (1 << 16)

Definition at line 377 of file l1/rcc.h.

◆ RCC_AHBRSTR

#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10)

Definition at line 59 of file l1/rcc.h.

◆ RCC_APB1ENR

#define RCC_APB1ENR MMIO32(RCC_BASE + 0x24)

Definition at line 64 of file l1/rcc.h.

◆ RCC_APB1LPENR

#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30)

Definition at line 67 of file l1/rcc.h.

◆ RCC_APB1LPENR_COMPLPEN

#define RCC_APB1LPENR_COMPLPEN (1 << 31)

Definition at line 395 of file l1/rcc.h.

◆ RCC_APB1LPENR_DACLPEN

#define RCC_APB1LPENR_DACLPEN (1 << 29)

Definition at line 396 of file l1/rcc.h.

◆ RCC_APB1LPENR_I2C1LPEN

#define RCC_APB1LPENR_I2C1LPEN (1 << 21)

Definition at line 400 of file l1/rcc.h.

◆ RCC_APB1LPENR_I2C2LPEN

#define RCC_APB1LPENR_I2C2LPEN (1 << 22)

Definition at line 399 of file l1/rcc.h.

◆ RCC_APB1LPENR_LCDLPEN

#define RCC_APB1LPENR_LCDLPEN (1 << 9)

Definition at line 405 of file l1/rcc.h.

◆ RCC_APB1LPENR_PWRLPEN

#define RCC_APB1LPENR_PWRLPEN (1 << 28)

Definition at line 397 of file l1/rcc.h.

◆ RCC_APB1LPENR_SPI2LPEN

#define RCC_APB1LPENR_SPI2LPEN (1 << 14)

Definition at line 403 of file l1/rcc.h.

◆ RCC_APB1LPENR_TIM2LPEN

#define RCC_APB1LPENR_TIM2LPEN (1 << 0)

Definition at line 410 of file l1/rcc.h.

◆ RCC_APB1LPENR_TIM3LPEN

#define RCC_APB1LPENR_TIM3LPEN (1 << 1)

Definition at line 409 of file l1/rcc.h.

◆ RCC_APB1LPENR_TIM4LPEN

#define RCC_APB1LPENR_TIM4LPEN (1 << 2)

Definition at line 408 of file l1/rcc.h.

◆ RCC_APB1LPENR_TIM6LPEN

#define RCC_APB1LPENR_TIM6LPEN (1 << 4)

Definition at line 407 of file l1/rcc.h.

◆ RCC_APB1LPENR_TIM7LPEN

#define RCC_APB1LPENR_TIM7LPEN (1 << 5)

Definition at line 406 of file l1/rcc.h.

◆ RCC_APB1LPENR_USART2LPEN

#define RCC_APB1LPENR_USART2LPEN (1 << 17)

Definition at line 402 of file l1/rcc.h.

◆ RCC_APB1LPENR_USART3LPEN

#define RCC_APB1LPENR_USART3LPEN (1 << 18)

Definition at line 401 of file l1/rcc.h.

◆ RCC_APB1LPENR_USBLPEN

#define RCC_APB1LPENR_USBLPEN (1 << 23)

Definition at line 398 of file l1/rcc.h.

◆ RCC_APB1LPENR_WWDGLPEN

#define RCC_APB1LPENR_WWDGLPEN (1 << 11)

Definition at line 404 of file l1/rcc.h.

◆ RCC_APB1RSTR

#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18)

Definition at line 61 of file l1/rcc.h.

◆ RCC_APB2ENR

#define RCC_APB2ENR MMIO32(RCC_BASE + 0x20)

Definition at line 63 of file l1/rcc.h.

◆ RCC_APB2LPENR

#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c)

Definition at line 66 of file l1/rcc.h.

◆ RCC_APB2LPENR_ADC1LPEN

#define RCC_APB2LPENR_ADC1LPEN (1 << 9)

Definition at line 389 of file l1/rcc.h.

◆ RCC_APB2LPENR_SPI1LPEN

#define RCC_APB2LPENR_SPI1LPEN (1 << 12)

Definition at line 388 of file l1/rcc.h.

◆ RCC_APB2LPENR_SYSCFGLPEN

#define RCC_APB2LPENR_SYSCFGLPEN (1 << 0)

Definition at line 393 of file l1/rcc.h.

◆ RCC_APB2LPENR_TIM10LPEN

#define RCC_APB2LPENR_TIM10LPEN (1 << 3)

Definition at line 391 of file l1/rcc.h.

◆ RCC_APB2LPENR_TIM11LPEN

#define RCC_APB2LPENR_TIM11LPEN (1 << 4)

Definition at line 390 of file l1/rcc.h.

◆ RCC_APB2LPENR_TIM9LPEN

#define RCC_APB2LPENR_TIM9LPEN (1 << 2)

Definition at line 392 of file l1/rcc.h.

◆ RCC_APB2LPENR_USART1LPEN

#define RCC_APB2LPENR_USART1LPEN (1 << 14)

Definition at line 387 of file l1/rcc.h.

◆ RCC_APB2RSTR

#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14)

Definition at line 60 of file l1/rcc.h.

◆ RCC_CFGR

#define RCC_CFGR MMIO32(RCC_BASE + 0x08)

Definition at line 57 of file l1/rcc.h.

◆ RCC_CFGR_HPRE_MASK

#define RCC_CFGR_HPRE_MASK 0xf

Definition at line 194 of file l1/rcc.h.

◆ RCC_CFGR_HPRE_SHIFT

#define RCC_CFGR_HPRE_SHIFT 4

Definition at line 195 of file l1/rcc.h.

◆ RCC_CFGR_MCO_HSE

#define RCC_CFGR_MCO_HSE 0x4

Definition at line 136 of file l1/rcc.h.

◆ RCC_CFGR_MCO_HSI

#define RCC_CFGR_MCO_HSI 0x2

Definition at line 134 of file l1/rcc.h.

◆ RCC_CFGR_MCO_LSE

#define RCC_CFGR_MCO_LSE 0x7

Definition at line 139 of file l1/rcc.h.

◆ RCC_CFGR_MCO_LSI

#define RCC_CFGR_MCO_LSI 0x6

Definition at line 138 of file l1/rcc.h.

◆ RCC_CFGR_MCO_MASK

#define RCC_CFGR_MCO_MASK 0x7

Definition at line 141 of file l1/rcc.h.

◆ RCC_CFGR_MCO_MSI

#define RCC_CFGR_MCO_MSI 0x3

Definition at line 135 of file l1/rcc.h.

◆ RCC_CFGR_MCO_NOCLK

#define RCC_CFGR_MCO_NOCLK 0x0

Definition at line 132 of file l1/rcc.h.

◆ RCC_CFGR_MCO_PLL

#define RCC_CFGR_MCO_PLL 0x5

Definition at line 137 of file l1/rcc.h.

◆ RCC_CFGR_MCO_SHIFT

#define RCC_CFGR_MCO_SHIFT 24

Definition at line 140 of file l1/rcc.h.

◆ RCC_CFGR_MCO_SYSCLK

#define RCC_CFGR_MCO_SYSCLK 0x1

Definition at line 133 of file l1/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV1

#define RCC_CFGR_MCOPRE_DIV1 0

Definition at line 123 of file l1/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV16

#define RCC_CFGR_MCOPRE_DIV16 4

Definition at line 127 of file l1/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV2

#define RCC_CFGR_MCOPRE_DIV2 1

Definition at line 124 of file l1/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV4

#define RCC_CFGR_MCOPRE_DIV4 2

Definition at line 125 of file l1/rcc.h.

◆ RCC_CFGR_MCOPRE_DIV8

#define RCC_CFGR_MCOPRE_DIV8 3

Definition at line 126 of file l1/rcc.h.

◆ RCC_CFGR_MCOPRE_MASK

#define RCC_CFGR_MCOPRE_MASK 0x7

Definition at line 129 of file l1/rcc.h.

◆ RCC_CFGR_MCOPRE_SHIFT

#define RCC_CFGR_MCOPRE_SHIFT 28

Definition at line 128 of file l1/rcc.h.

◆ RCC_CFGR_PLLDIV_DIV2

#define RCC_CFGR_PLLDIV_DIV2 0x1

Definition at line 144 of file l1/rcc.h.

◆ RCC_CFGR_PLLDIV_DIV3

#define RCC_CFGR_PLLDIV_DIV3 0x2

Definition at line 145 of file l1/rcc.h.

◆ RCC_CFGR_PLLDIV_DIV4

#define RCC_CFGR_PLLDIV_DIV4 0x3

Definition at line 146 of file l1/rcc.h.

◆ RCC_CFGR_PLLDIV_MASK

#define RCC_CFGR_PLLDIV_MASK 0x3

Definition at line 148 of file l1/rcc.h.

◆ RCC_CFGR_PLLDIV_SHIFT

#define RCC_CFGR_PLLDIV_SHIFT 22

Definition at line 147 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_MASK

#define RCC_CFGR_PLLMUL_MASK 0xf

Definition at line 161 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL12

#define RCC_CFGR_PLLMUL_MUL12 0x4

Definition at line 155 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL16

#define RCC_CFGR_PLLMUL_MUL16 0x5

Definition at line 156 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL24

#define RCC_CFGR_PLLMUL_MUL24 0x6

Definition at line 157 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL3

#define RCC_CFGR_PLLMUL_MUL3 0x0

Definition at line 151 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL32

#define RCC_CFGR_PLLMUL_MUL32 0x7

Definition at line 158 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL4

#define RCC_CFGR_PLLMUL_MUL4 0x1

Definition at line 152 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL48

#define RCC_CFGR_PLLMUL_MUL48 0x8

Definition at line 159 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL6

#define RCC_CFGR_PLLMUL_MUL6 0x2

Definition at line 153 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_MUL8

#define RCC_CFGR_PLLMUL_MUL8 0x3

Definition at line 154 of file l1/rcc.h.

◆ RCC_CFGR_PLLMUL_SHIFT

#define RCC_CFGR_PLLMUL_SHIFT 18

Definition at line 160 of file l1/rcc.h.

◆ RCC_CFGR_PLLSRC_HSE_CLK

#define RCC_CFGR_PLLSRC_HSE_CLK 0x1

Definition at line 165 of file l1/rcc.h.

◆ RCC_CFGR_PLLSRC_HSI_CLK

#define RCC_CFGR_PLLSRC_HSI_CLK 0x0

Definition at line 164 of file l1/rcc.h.

◆ RCC_CFGR_PPRE1_MASK

#define RCC_CFGR_PPRE1_MASK 0x7

Definition at line 170 of file l1/rcc.h.

◆ RCC_CFGR_PPRE1_SHIFT

#define RCC_CFGR_PPRE1_SHIFT 8

Definition at line 169 of file l1/rcc.h.

◆ RCC_CFGR_PPRE2_MASK

#define RCC_CFGR_PPRE2_MASK 0x7

Definition at line 168 of file l1/rcc.h.

◆ RCC_CFGR_PPRE2_SHIFT

#define RCC_CFGR_PPRE2_SHIFT 11

Definition at line 167 of file l1/rcc.h.

◆ RCC_CFGR_SW_MASK

#define RCC_CFGR_SW_MASK 0x3

Definition at line 210 of file l1/rcc.h.

◆ RCC_CFGR_SW_SHIFT

#define RCC_CFGR_SW_SHIFT 0

Definition at line 211 of file l1/rcc.h.

◆ RCC_CFGR_SW_SYSCLKSEL_HSECLK

#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2

Definition at line 208 of file l1/rcc.h.

◆ RCC_CFGR_SW_SYSCLKSEL_HSICLK

#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1

Definition at line 207 of file l1/rcc.h.

◆ RCC_CFGR_SW_SYSCLKSEL_MSICLK

#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0

Definition at line 206 of file l1/rcc.h.

◆ RCC_CFGR_SW_SYSCLKSEL_PLLCLK

#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3

Definition at line 209 of file l1/rcc.h.

◆ RCC_CFGR_SWS_MASK

#define RCC_CFGR_SWS_MASK 0x3

Definition at line 202 of file l1/rcc.h.

◆ RCC_CFGR_SWS_SHIFT

#define RCC_CFGR_SWS_SHIFT 2

Definition at line 203 of file l1/rcc.h.

◆ RCC_CFGR_SWS_SYSCLKSEL_HSECLK

#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2

Definition at line 200 of file l1/rcc.h.

◆ RCC_CFGR_SWS_SYSCLKSEL_HSICLK

#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1

Definition at line 199 of file l1/rcc.h.

◆ RCC_CFGR_SWS_SYSCLKSEL_MSICLK

#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0

Definition at line 198 of file l1/rcc.h.

◆ RCC_CFGR_SWS_SYSCLKSEL_PLLCLK

#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3

Definition at line 201 of file l1/rcc.h.

◆ RCC_CIR

#define RCC_CIR MMIO32(RCC_BASE + 0x0c)

Definition at line 58 of file l1/rcc.h.

◆ RCC_CIR_CSSC

#define RCC_CIR_CSSC (1 << 23)

Definition at line 245 of file l1/rcc.h.

◆ RCC_CIR_CSSF

#define RCC_CIR_CSSF (1 << 7)

Definition at line 264 of file l1/rcc.h.

◆ RCC_CIR_HSERDYC

#define RCC_CIR_HSERDYC (1 << 19)

Definition at line 250 of file l1/rcc.h.

◆ RCC_CIR_HSERDYF

#define RCC_CIR_HSERDYF (1 << 3)

Definition at line 269 of file l1/rcc.h.

◆ RCC_CIR_HSERDYIE

#define RCC_CIR_HSERDYIE (1 << 11)

Definition at line 258 of file l1/rcc.h.

◆ RCC_CIR_HSIRDYC

#define RCC_CIR_HSIRDYC (1 << 18)

Definition at line 251 of file l1/rcc.h.

◆ RCC_CIR_HSIRDYF

#define RCC_CIR_HSIRDYF (1 << 2)

Definition at line 270 of file l1/rcc.h.

◆ RCC_CIR_HSIRDYIE

#define RCC_CIR_HSIRDYIE (1 << 10)

Definition at line 259 of file l1/rcc.h.

◆ RCC_CIR_LSERDYC

#define RCC_CIR_LSERDYC (1 << 17)

Definition at line 252 of file l1/rcc.h.

◆ RCC_CIR_LSERDYF

#define RCC_CIR_LSERDYF (1 << 1)

Definition at line 271 of file l1/rcc.h.

◆ RCC_CIR_LSERDYIE

#define RCC_CIR_LSERDYIE (1 << 9)

Definition at line 260 of file l1/rcc.h.

◆ RCC_CIR_LSIRDYC

#define RCC_CIR_LSIRDYC (1 << 16)

Definition at line 253 of file l1/rcc.h.

◆ RCC_CIR_LSIRDYF

#define RCC_CIR_LSIRDYF (1 << 0)

Definition at line 272 of file l1/rcc.h.

◆ RCC_CIR_LSIRDYIE

#define RCC_CIR_LSIRDYIE (1 << 8)

Definition at line 261 of file l1/rcc.h.

◆ RCC_CIR_MSIRDYC

#define RCC_CIR_MSIRDYC (1 << 21)

Definition at line 248 of file l1/rcc.h.

◆ RCC_CIR_MSIRDYF

#define RCC_CIR_MSIRDYF (1 << 5) /* (**) */

Definition at line 267 of file l1/rcc.h.

◆ RCC_CIR_MSIRDYIE

#define RCC_CIR_MSIRDYIE (1 << 13)

Definition at line 256 of file l1/rcc.h.

◆ RCC_CIR_PLLRDYC

#define RCC_CIR_PLLRDYC (1 << 20)

Definition at line 249 of file l1/rcc.h.

◆ RCC_CIR_PLLRDYF

#define RCC_CIR_PLLRDYF (1 << 4)

Definition at line 268 of file l1/rcc.h.

◆ RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLRDYIE (1 << 12)

Definition at line 257 of file l1/rcc.h.

◆ RCC_CR

#define RCC_CR MMIO32(RCC_BASE + 0x00)

Definition at line 55 of file l1/rcc.h.

◆ RCC_CR_CSSON

#define RCC_CR_CSSON (1 << 28)

Definition at line 74 of file l1/rcc.h.

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP (1 << 18)

Definition at line 77 of file l1/rcc.h.

◆ RCC_CR_HSEON

#define RCC_CR_HSEON (1 << 16)

Definition at line 79 of file l1/rcc.h.

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY (1 << 17)

Definition at line 78 of file l1/rcc.h.

◆ RCC_CR_HSION

#define RCC_CR_HSION (1 << 0)

Definition at line 83 of file l1/rcc.h.

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY (1 << 1)

Definition at line 82 of file l1/rcc.h.

◆ RCC_CR_MSION

#define RCC_CR_MSION (1 << 8)

Definition at line 81 of file l1/rcc.h.

◆ RCC_CR_MSIRDY

#define RCC_CR_MSIRDY (1 << 9)

Definition at line 80 of file l1/rcc.h.

◆ RCC_CR_PLLON

#define RCC_CR_PLLON (1 << 24)

Definition at line 76 of file l1/rcc.h.

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY (1 << 25)

Definition at line 75 of file l1/rcc.h.

◆ RCC_CR_RTCPRE_DIV16

#define RCC_CR_RTCPRE_DIV16 3

Definition at line 88 of file l1/rcc.h.

◆ RCC_CR_RTCPRE_DIV2

#define RCC_CR_RTCPRE_DIV2 0

Definition at line 85 of file l1/rcc.h.

◆ RCC_CR_RTCPRE_DIV4

#define RCC_CR_RTCPRE_DIV4 1

Definition at line 86 of file l1/rcc.h.

◆ RCC_CR_RTCPRE_DIV8

#define RCC_CR_RTCPRE_DIV8 2

Definition at line 87 of file l1/rcc.h.

◆ RCC_CR_RTCPRE_MASK [1/2]

#define RCC_CR_RTCPRE_MASK 0x3

Definition at line 90 of file l1/rcc.h.

◆ RCC_CR_RTCPRE_MASK [2/2]

#define RCC_CR_RTCPRE_MASK 0x3

Definition at line 90 of file l1/rcc.h.

◆ RCC_CR_RTCPRE_SHIFT [1/2]

#define RCC_CR_RTCPRE_SHIFT 29

Definition at line 89 of file l1/rcc.h.

◆ RCC_CR_RTCPRE_SHIFT [2/2]

#define RCC_CR_RTCPRE_SHIFT 29

Definition at line 89 of file l1/rcc.h.

◆ RCC_CSR

#define RCC_CSR MMIO32(RCC_BASE + 0x34)

Definition at line 68 of file l1/rcc.h.

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF (1 << 29)

Definition at line 417 of file l1/rcc.h.

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF (1 << 31)

Definition at line 415 of file l1/rcc.h.

◆ RCC_CSR_LSEBYP

#define RCC_CSR_LSEBYP (1 << 10)

Definition at line 436 of file l1/rcc.h.

◆ RCC_CSR_LSECSSD

#define RCC_CSR_LSECSSD (1 << 12)

Definition at line 434 of file l1/rcc.h.

◆ RCC_CSR_LSECSSON

#define RCC_CSR_LSECSSON (1 << 11)

Definition at line 435 of file l1/rcc.h.

◆ RCC_CSR_LSEON

#define RCC_CSR_LSEON (1 << 8)

Definition at line 438 of file l1/rcc.h.

◆ RCC_CSR_LSERDY

#define RCC_CSR_LSERDY (1 << 9)

Definition at line 437 of file l1/rcc.h.

◆ RCC_CSR_LSION

#define RCC_CSR_LSION (1 << 0)

Definition at line 440 of file l1/rcc.h.

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY (1 << 1)

Definition at line 439 of file l1/rcc.h.

◆ RCC_CSR_OBLRSTF

#define RCC_CSR_OBLRSTF (1 << 25)

Definition at line 421 of file l1/rcc.h.

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF (1 << 26)

Definition at line 420 of file l1/rcc.h.

◆ RCC_CSR_PORRSTF

#define RCC_CSR_PORRSTF (1 << 27)

Definition at line 419 of file l1/rcc.h.

◆ RCC_CSR_RESET_FLAGS

#define RCC_CSR_RESET_FLAGS

Value:

                (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF |\
                RCC_CSR_IWDGRSTF | RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF |\
                RCC_CSR_PINRSTF | RCC_CSR_OBLRSTF)

Definition at line 423 of file l1/rcc.h.

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF (1 << 24)

Definition at line 422 of file l1/rcc.h.

◆ RCC_CSR_RTCEN

#define RCC_CSR_RTCEN (1 << 22)

Definition at line 427 of file l1/rcc.h.

◆ RCC_CSR_RTCRST

#define RCC_CSR_RTCRST (1 << 23)

Definition at line 426 of file l1/rcc.h.

◆ RCC_CSR_RTCSEL_HSE

#define RCC_CSR_RTCSEL_HSE (0x3)

Definition at line 433 of file l1/rcc.h.

◆ RCC_CSR_RTCSEL_LSE

#define RCC_CSR_RTCSEL_LSE (0x1)

Definition at line 431 of file l1/rcc.h.

◆ RCC_CSR_RTCSEL_LSI

#define RCC_CSR_RTCSEL_LSI (0x2)

Definition at line 432 of file l1/rcc.h.

◆ RCC_CSR_RTCSEL_MASK

#define RCC_CSR_RTCSEL_MASK (0x3)

Definition at line 429 of file l1/rcc.h.

◆ RCC_CSR_RTCSEL_NONE

#define RCC_CSR_RTCSEL_NONE (0x0)

Definition at line 430 of file l1/rcc.h.

◆ RCC_CSR_RTCSEL_SHIFT

#define RCC_CSR_RTCSEL_SHIFT (16)

Definition at line 428 of file l1/rcc.h.

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF (1 << 28)

Definition at line 418 of file l1/rcc.h.

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF (1 << 30)

Definition at line 416 of file l1/rcc.h.

◆ RCC_ICSCR

#define RCC_ICSCR MMIO32(RCC_BASE + 0x04)

Definition at line 56 of file l1/rcc.h.

Enumeration Type Documentation

◆ rcc_clock_config_entry

enum rcc_clock_config_entry

Enumerator
RCC_CLOCK_VRANGE1_HSI_PLL_24MHZ
RCC_CLOCK_VRANGE1_HSI_PLL_32MHZ
RCC_CLOCK_VRANGE1_HSI_RAW_16MHZ
RCC_CLOCK_VRANGE1_HSI_RAW_4MHZ
RCC_CLOCK_VRANGE1_MSI_RAW_4MHZ
RCC_CLOCK_VRANGE1_MSI_RAW_2MHZ
RCC_CLOCK_CONFIG_END

Definition at line 457 of file l1/rcc.h.

◆ rcc_osc

enum rcc_osc

Enumerator
RCC_PLL
RCC_HSE
RCC_HSI
RCC_MSI
RCC_LSE
RCC_LSI

Definition at line 477 of file l1/rcc.h.

◆ rcc_periph_clken

enum rcc_periph_clken

Enumerator
RCC_GPIOA
RCC_GPIOB
RCC_GPIOC
RCC_GPIOD
RCC_GPIOE
RCC_GPIOH
RCC_GPIOF
RCC_GPIOG
RCC_CRC
RCC_FLITF
RCC_DMA1
RCC_DMA2
RCC_AES
RCC_FSMC
RCC_SYSCFG
RCC_TIM9
RCC_TIM10
RCC_TIM11
RCC_ADC1
RCC_SDIO
RCC_SPI1
RCC_USART1
RCC_TIM2
RCC_TIM3
RCC_TIM4
RCC_TIM5
RCC_TIM6
RCC_TIM7
RCC_LCD
RCC_WWDG
RCC_SPI2
RCC_SPI3
RCC_USART2
RCC_USART3
RCC_UART4
RCC_UART5
RCC_I2C1
RCC_I2C2
RCC_USB
RCC_PWR
RCC_DAC
RCC_COMP
SCC_GPIOA
SCC_GPIOB
SCC_GPIOC
SCC_GPIOD
SCC_GPIOE
SCC_GPIOH
SCC_GPIOF
SCC_GPIOG
SCC_CRC
SCC_FLITF
SCC_SRAM
SCC_DMA1
SCC_DMA2
SCC_AES
SCC_FSMC
SCC_SYSCFG
SCC_TIM9
SCC_TIM10
SCC_TIM11
SCC_ADC1
SCC_SDIO
SCC_SPI1
SCC_USART1
SCC_TIM2
SCC_TIM3
SCC_TIM4
SCC_TIM5
SCC_TIM6
SCC_TIM7
SCC_LCD
SCC_WWDG
SCC_SPI2
SCC_SPI3
SCC_USART2
SCC_USART3
SCC_UART4
SCC_UART5
SCC_I2C1
SCC_I2C2
SCC_USB
SCC_PWR
SCC_DAC
SCC_COMP

Definition at line 483 of file l1/rcc.h.

◆ rcc_periph_rst

enum rcc_periph_rst

Enumerator
RST_GPIOA
RST_GPIOB
RST_GPIOC
RST_GPIOD
RST_GPIOE
RST_GPIOH
RST_GPIOF
RST_GPIOG
RST_CRC
RST_FLITF
RST_DMA1
RST_DMA2
RST_AES
RST_FSMC
RST_SYSCFG
RST_TIM9
RST_TIM10
RST_TIM11
RST_ADC1
RST_SDIO
RST_SPI1
RST_USART1
RST_TIM2
RST_TIM3
RST_TIM4
RST_TIM5
RST_TIM6
RST_TIM7
RST_LCD
RST_WWDG
RST_SPI2
RST_SPI3
RST_USART2
RST_USART3
RST_UART4
RST_UART5
RST_I2C1
RST_I2C2
RST_USB
RST_PWR
RST_DAC
RST_COMP

Definition at line 582 of file l1/rcc.h.

Function Documentation

◆ rcc_backupdomain_reset()

void rcc_backupdomain_reset ( void )

◆ rcc_clock_setup_hsi()

void rcc_clock_setup_hsi ( const struct rcc_clock_scale * clock )

Switch sysclock to HSI with the given parameters.

This should be usable from any point in time, but only if you have used library functions to manage clocks. It relies on the global rcc_ahb_frequency to ensure that it reliably scales voltage up or down as appropriate.

Parameters

clock full struct with desired parameters

Definition at line 473 of file rcc.c.

References rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb1_frequency, rcc_clock_scale::apb2_frequency, flash_64bit_enable(), flash_prefetch_enable(), flash_set_ws(), rcc_clock_scale::flash_waitstates, rcc_clock_scale::hpre, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, PWR_CSR, PWR_CSR_VOSF, pwr_set_vos_scale(), rcc_ahb_frequency, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR_SW_SYSCLKSEL_HSICLK, RCC_HSI, rcc_osc_on(), rcc_periph_clock_enable(), RCC_PWR, rcc_set_hpre(), rcc_set_ppre1(), rcc_set_ppre2(), rcc_set_sysclk_source(), rcc_wait_for_osc_ready(), and rcc_clock_scale::voltage_scale.

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◆ rcc_clock_setup_msi()

void rcc_clock_setup_msi ( const struct rcc_clock_scale * clock )

◆ rcc_clock_setup_pll()

void rcc_clock_setup_pll ( const struct rcc_clock_scale * clock )

Definition at line 512 of file rcc.c.

References rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb1_frequency, rcc_clock_scale::apb2_frequency, flash_64bit_enable(), flash_prefetch_enable(), flash_set_ws(), rcc_clock_scale::flash_waitstates, rcc_clock_scale::hpre, rcc_clock_scale::pll_div, rcc_clock_scale::pll_mul, rcc_clock_scale::pll_source, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, pwr_set_vos_scale(), rcc_ahb_frequency, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR_PLLSRC_HSE_CLK, RCC_CFGR_SW_SYSCLKSEL_PLLCLK, RCC_HSE, RCC_HSI, rcc_osc_off(), rcc_osc_on(), rcc_periph_clock_enable(), RCC_PLL, RCC_PWR, rcc_set_hpre(), rcc_set_pll_configuration(), rcc_set_ppre1(), rcc_set_ppre2(), rcc_set_sysclk_source(), rcc_wait_for_osc_ready(), and rcc_clock_scale::voltage_scale.

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◆ rcc_css_disable()

void rcc_css_disable ( void )

Definition at line 334 of file rcc.c.

References RCC_CR.

◆ rcc_css_enable()

void rcc_css_enable ( void )

Definition at line 329 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void )

Definition at line 222 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void )

Definition at line 227 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSF.

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t div_val )

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters

div_val Masked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

◆ rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq ( uint32_t i2c )

Get the peripheral clock speed for the I2C device at base specified.

Parameters

i2c	Base address of I2C to get clock frequency for.

Definition at line 594 of file rcc.c.

References rcc_apb1_frequency.

◆ rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq ( uint32_t spi )

Get the peripheral clock speed for the SPI device at base specified.

Parameters

spi	Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).

Definition at line 603 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, and SPI1_BASE.

◆ rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq ( uint32_t timer )

Get the peripheral clock speed for the Timer at base specified.

Parameters

timer Base address of TIM to get clock frequency for.

Definition at line 576 of file rcc.c.

References rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR, RCC_CFGR_PPRE1_HCLK_NODIV, RCC_CFGR_PPRE1_MASK, RCC_CFGR_PPRE1_SHIFT, RCC_CFGR_PPRE2_HCLK_NODIV, RCC_CFGR_PPRE2_MASK, RCC_CFGR_PPRE2_SHIFT, TIM2_BASE, and TIM7_BASE.

◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t usart )

Get the peripheral clock speed for the USART at base specified.

Parameters

usart Base address of USART to get clock frequency for.

Definition at line 563 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, and USART1_BASE.

Referenced by usart_set_baudrate().

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◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc osc )

Is the given oscillator ready?

Parameters

osc	Oscillator ID

Returns: true if the hardware indicates the oscillator is ready.

Definition at line 232 of file rcc.c.

References RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_MSIRDY, RCC_CR_PLLRDY, RCC_CSR, RCC_CSR_LSERDY, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_wait_for_osc_ready().

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◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc osc )

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc osc )

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_CSR_LSEBYP, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc osc )

Definition at line 305 of file rcc.c.

References RCC_CR, RCC_CSR, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc osc )

Definition at line 281 of file rcc.c.

References RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_MSION, RCC_CR_PLLON, RCC_CSR, RCC_CSR_LSEON, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_hsi(), rcc_clock_setup_msi(), and rcc_clock_setup_pll().

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◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc osc )

Definition at line 123 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYC, RCC_CIR_HSIRDYC, RCC_CIR_LSERDYC, RCC_CIR_LSIRDYC, RCC_CIR_MSIRDYC, RCC_CIR_PLLRDYC, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc osc )

Definition at line 171 of file rcc.c.

References RCC_CIR, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc osc )

Definition at line 147 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYIE, RCC_CIR_HSIRDYIE, RCC_CIR_LSERDYIE, RCC_CIR_LSIRDYIE, RCC_CIR_MSIRDYIE, RCC_CIR_PLLRDYIE, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc osc )

Definition at line 195 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYF, RCC_CIR_HSIRDYF, RCC_CIR_LSERDYF, RCC_CIR_LSIRDYF, RCC_CIR_MSIRDYF, RCC_CIR_PLLRDYF, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken clken )

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken clken )

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by rcc_clock_setup_hsi(), rcc_clock_setup_msi(), rcc_clock_setup_pll(), and st_usbfs_v1_usbd_init().

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◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst rst )

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst rst )

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst rst )

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset	(	volatile uint32_t *	reg,
		uint32_t	clear_reset
	)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	clear_reset	Unsigned int32. Logical OR of all resets to be removed: If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values values If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values values If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values values

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be used for disabling. If register is RCC_AHBENR, from RCC_AHBENR enable values If register is RCC_APB1ENR, from RCC_APB1ENR enable values If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be set If register is RCC_AHBENR, from RCC_AHBENR enable values If register is RCC_APB1ENR, from RCC_APB1ENR enable values If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset	(	volatile uint32_t *	reg,
		uint32_t	reset
	)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	reset	Unsigned int32. Logical OR of all resets. If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values values If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values values If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values values