libopencm3 STM32L1xx Reset and Clock Control More...

Collaboration diagram for RCC peripheral API:

Macros
#define	_RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5))

#define	_RCC_BIT(i) (1 << ((i) & 0x1f))

Functions
void	rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Enable Peripheral Clocks. More...

void	rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Disable Peripheral Clocks. More...

void	rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
	RCC Reset Peripherals. More...

void	rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
	RCC Remove Reset on Peripherals. More...

void	rcc_periph_clock_enable (enum rcc_periph_clken clken)
	Enable Peripheral Clock in running mode. More...

void	rcc_periph_clock_disable (enum rcc_periph_clken clken)
	Disable Peripheral Clock in running mode. More...

void	rcc_periph_reset_pulse (enum rcc_periph_rst rst)
	Reset Peripheral, pulsed. More...

void	rcc_periph_reset_hold (enum rcc_periph_rst rst)
	Reset Peripheral, hold. More...

void	rcc_periph_reset_release (enum rcc_periph_rst rst)
	Reset Peripheral, release. More...

void	rcc_set_mco (uint32_t mcosrc)
	Select the source of Microcontroller Clock Output. More...

void	rcc_osc_bypass_enable (enum rcc_osc osc)
	RCC Enable Bypass. More...

void	rcc_osc_bypass_disable (enum rcc_osc osc)
	RCC Disable Bypass. More...

uint16_t	rcc_get_div_from_hpre (uint8_t div_val)
	This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...

void	rcc_osc_ready_int_clear (enum rcc_osc osc)

void	rcc_osc_ready_int_enable (enum rcc_osc osc)

void	rcc_osc_ready_int_disable (enum rcc_osc osc)

int	rcc_osc_ready_int_flag (enum rcc_osc osc)

void	rcc_css_int_clear (void)

int	rcc_css_int_flag (void)

bool	rcc_is_osc_ready (enum rcc_osc osc)
	Is the given oscillator ready? More...

void	rcc_wait_for_osc_ready (enum rcc_osc osc)
	Wait for Oscillator Ready. More...

void	rcc_wait_for_sysclk_status (enum rcc_osc osc)

void	rcc_osc_on (enum rcc_osc osc)

void	rcc_osc_off (enum rcc_osc osc)

void	rcc_css_enable (void)

void	rcc_css_disable (void)

void	rcc_set_msi_range (uint32_t range)
	Set the range of the MSI oscillator. More...

void	rcc_set_sysclk_source (uint32_t clk)

void	rcc_set_pll_configuration (uint32_t source, uint32_t multiplier, uint32_t divisor)

void	rcc_set_pll_source (uint32_t pllsrc)

void	rcc_set_ppre2 (uint32_t ppre2)

void	rcc_set_ppre1 (uint32_t ppre1)

void	rcc_set_hpre (uint32_t hpre)

void	rcc_set_rtcpre (uint32_t rtcpre)

uint32_t	rcc_system_clock_source (void)

void	rcc_rtc_select_clock (uint32_t clock)

void	rcc_clock_setup_msi (const struct rcc_clock_scale *clock)

void	rcc_clock_setup_hsi (const struct rcc_clock_scale *clock)
	Switch sysclock to HSI with the given parameters. More...

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the USART at base specified. More...

uint32_t	rcc_get_timer_clk_freq (uint32_t timer)
	Get the peripheral clock speed for the Timer at base specified. More...

uint32_t	rcc_get_i2c_clk_freq (uint32_t i2c)
	Get the peripheral clock speed for the I2C device at base specified. More...

uint32_t	rcc_get_spi_clk_freq (uint32_t spi)
	Get the peripheral clock speed for the SPI device at base specified. More...

Variables
uint32_t	rcc_ahb_frequency = 2097000

uint32_t	rcc_apb1_frequency = 2097000

uint32_t	rcc_apb2_frequency = 2097000

const struct rcc_clock_scale	rcc_clock_config [RCC_CLOCK_CONFIG_END]

Detailed Description

libopencm3 STM32L1xx Reset and Clock Control

Version: 1.0.0

This library supports the Reset and Clock Control System in the STM32L1xx series of ARM Cortex Microcontrollers by ST Microelectronics.

Clock settings and resets for many peripherals are given here rather than in the corresponding peripheral library.

The library also provides a number of common configurations for the processor system clock. Not all possible configurations are included.

Macro Definition Documentation

◆ _RCC_BIT

#define _RCC_BIT ( i ) (1 << ((i) & 0x1f))

Definition at line 117 of file rcc_common_all.c.

◆ _RCC_REG

#define _RCC_REG ( i ) MMIO32(RCC_BASE + ((i) >> 5))

Definition at line 116 of file rcc_common_all.c.

Function Documentation

◆ rcc_clock_setup_hsi()

void rcc_clock_setup_hsi ( const struct rcc_clock_scale * clock )

Switch sysclock to HSI with the given parameters.

This should be usable from any point in time, but only if you have used library functions to manage clocks. It relies on the global rcc_ahb_frequency to ensure that it reliably scales voltage up or down as appropriate.

Parameters

clock full struct with desired parameters

Definition at line 473 of file rcc.c.

References rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb1_frequency, rcc_clock_scale::apb2_frequency, flash_64bit_enable(), flash_prefetch_enable(), flash_set_ws(), rcc_clock_scale::flash_waitstates, rcc_clock_scale::hpre, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, PWR_CSR, PWR_CSR_VOSF, pwr_set_vos_scale(), rcc_ahb_frequency, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR_SW_SYSCLKSEL_HSICLK, RCC_HSI, rcc_osc_on(), rcc_periph_clock_enable(), RCC_PWR, rcc_set_hpre(), rcc_set_ppre1(), rcc_set_ppre2(), rcc_set_sysclk_source(), rcc_wait_for_osc_ready(), and rcc_clock_scale::voltage_scale.

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◆ rcc_clock_setup_msi()

void rcc_clock_setup_msi ( const struct rcc_clock_scale * clock )

◆ rcc_clock_setup_pll()

void rcc_clock_setup_pll ( const struct rcc_clock_scale * clock )

Definition at line 512 of file rcc.c.

References rcc_clock_scale::ahb_frequency, rcc_clock_scale::apb1_frequency, rcc_clock_scale::apb2_frequency, flash_64bit_enable(), flash_prefetch_enable(), flash_set_ws(), rcc_clock_scale::flash_waitstates, rcc_clock_scale::hpre, rcc_clock_scale::pll_div, rcc_clock_scale::pll_mul, rcc_clock_scale::pll_source, rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, pwr_set_vos_scale(), rcc_ahb_frequency, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR_PLLSRC_HSE_CLK, RCC_CFGR_SW_SYSCLKSEL_PLLCLK, RCC_HSE, RCC_HSI, rcc_osc_off(), rcc_osc_on(), rcc_periph_clock_enable(), RCC_PLL, RCC_PWR, rcc_set_hpre(), rcc_set_pll_configuration(), rcc_set_ppre1(), rcc_set_ppre2(), rcc_set_sysclk_source(), rcc_wait_for_osc_ready(), and rcc_clock_scale::voltage_scale.

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◆ rcc_css_disable()

void rcc_css_disable ( void )

Definition at line 334 of file rcc.c.

References RCC_CR.

◆ rcc_css_enable()

void rcc_css_enable ( void )

Definition at line 329 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void )

Definition at line 222 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void )

Definition at line 227 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSF.

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t div_val )

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters

div_val Masked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

◆ rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq ( uint32_t i2c )

Get the peripheral clock speed for the I2C device at base specified.

Parameters

i2c	Base address of I2C to get clock frequency for.

Definition at line 594 of file rcc.c.

References rcc_apb1_frequency.

◆ rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq ( uint32_t spi )

Get the peripheral clock speed for the SPI device at base specified.

Parameters

spi	Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).

Definition at line 603 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, and SPI1_BASE.

◆ rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq ( uint32_t timer )

Get the peripheral clock speed for the Timer at base specified.

Parameters

timer Base address of TIM to get clock frequency for.

Definition at line 576 of file rcc.c.

References rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR, RCC_CFGR_PPRE1_HCLK_NODIV, RCC_CFGR_PPRE1_MASK, RCC_CFGR_PPRE1_SHIFT, RCC_CFGR_PPRE2_HCLK_NODIV, RCC_CFGR_PPRE2_MASK, RCC_CFGR_PPRE2_SHIFT, TIM2_BASE, and TIM7_BASE.

◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t usart )

Get the peripheral clock speed for the USART at base specified.

Parameters

usart Base address of USART to get clock frequency for.

Definition at line 563 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, and USART1_BASE.

Referenced by usart_set_baudrate().

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◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc osc )

Is the given oscillator ready?

Parameters

osc	Oscillator ID

Returns: true if the hardware indicates the oscillator is ready.

Definition at line 232 of file rcc.c.

References RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_MSIRDY, RCC_CR_PLLRDY, RCC_CSR, RCC_CSR_LSERDY, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_wait_for_osc_ready().

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◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc osc )

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc osc )

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_CSR_LSEBYP, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc osc )

Definition at line 305 of file rcc.c.

References RCC_CR, RCC_CSR, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc osc )

Definition at line 281 of file rcc.c.

References RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_MSION, RCC_CR_PLLON, RCC_CSR, RCC_CSR_LSEON, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

Referenced by rcc_clock_setup_hsi(), rcc_clock_setup_msi(), and rcc_clock_setup_pll().

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◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc osc )

Definition at line 123 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYC, RCC_CIR_HSIRDYC, RCC_CIR_LSERDYC, RCC_CIR_LSIRDYC, RCC_CIR_MSIRDYC, RCC_CIR_PLLRDYC, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc osc )

Definition at line 171 of file rcc.c.

References RCC_CIR, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc osc )

Definition at line 147 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYIE, RCC_CIR_HSIRDYIE, RCC_CIR_LSERDYIE, RCC_CIR_LSIRDYIE, RCC_CIR_MSIRDYIE, RCC_CIR_PLLRDYIE, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc osc )

Definition at line 195 of file rcc.c.

References RCC_CIR, RCC_CIR_HSERDYF, RCC_CIR_HSIRDYF, RCC_CIR_LSERDYF, RCC_CIR_LSIRDYF, RCC_CIR_MSIRDYF, RCC_CIR_PLLRDYF, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_MSI, and RCC_PLL.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken clken )

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken clken )

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by rcc_clock_setup_hsi(), rcc_clock_setup_msi(), rcc_clock_setup_pll(), and st_usbfs_v1_usbd_init().

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◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst rst )

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst rst )

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst rst )

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset	(	volatile uint32_t *	reg,
		uint32_t	clear_reset
	)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	clear_reset	Unsigned int32. Logical OR of all resets to be removed: If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values values If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values values If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values values

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be used for disabling. If register is RCC_AHBENR, from RCC_AHBENR enable values If register is RCC_APB1ENR, from RCC_APB1ENR enable values If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be set If register is RCC_AHBENR, from RCC_AHBENR enable values If register is RCC_APB1ENR, from RCC_APB1ENR enable values If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset	(	volatile uint32_t *	reg,
		uint32_t	reset
	)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	reset	Unsigned int32. Logical OR of all resets. If register is RCC_AHBRSTR, from RCC_AHBRSTR reset values values If register is RCC_APB1RSTR, from RCC_APB1RSTR reset values values If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values values