libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
stm32/l1/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 * Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
6 *
7 * This library is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU Lesser General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public License
18 * along with this library. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef LIBOPENCM3_MEMORYMAP_H
22#define LIBOPENCM3_MEMORYMAP_H
23
24#include <libopencm3/cm3/memorymap.h>
25
26/* --- STM32 specific peripheral definitions ------------------------------- */
27
28/* Memory map for all busses */
29#define FLASH_BASE (0x08000000U)
30#define PERIPH_BASE (0x40000000U)
31#define INFO_BASE (0x1ff00000U)
32#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
33#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
34#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)
35
36/* Register boundary addresses */
37
38/* APB1 */
39#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
40#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
41#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
42#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
43#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
44#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
45#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400)
46#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
47#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
48#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
49/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
50#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
51#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
52/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
53#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
54#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
55#define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
56#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000)
57#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
58#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
59#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
60#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000)
61/* gap */
62#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
63#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
64#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c)
65#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
66#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
67
68/* APB2 */
69#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)
70#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
71#define TIM9_BASE (PERIPH_BASE_APB2 + 0x0800)
72#define TIM10_BASE (PERIPH_BASE_APB2 + 0x0c00)
73#define TIM11_BASE (PERIPH_BASE_APB2 + 0x1000)
74/* gap */
75#define ADC_BASE (PERIPH_BASE_APB2 + 0x2400)
76/* ADC is the name in the L1 refman, but all other stm32's use ADC1 */
77#define ADC1_BASE ADC_BASE
78/* gap */
79#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2c00)
80#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
81/* gap */
82#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
83
84/* AHB */
85#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB + 0x00000)
86#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB + 0x00400)
87#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB + 0x00800)
88#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
89#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
90#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
91#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800)
92#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00)
93/* gap */
94#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
95/* gap */
96#define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
97#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
98/* gap */
99#define DMA1_BASE (PERIPH_BASE_AHB + 0x06000)
100#define DMA2_BASE (PERIPH_BASE_AHB + 0x04000)
101
102/* PPIB */
103#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
104
105/* FSMC */
106#define FSMC_BASE (PERIPH_BASE + 0x60000000)
107/* AES */
108#define AES_BASE (PERIPH_BASE + 0x10000000)
109
110/* Device Electronic Signature */
111#define DESIG_FLASH_SIZE_BASE_CAT12 (INFO_BASE + 0x8004C)
112#define DESIG_FLASH_SIZE_BASE_CAT3456 (INFO_BASE + 0x800CC)
113#define DESIG_UNIQUE_ID_BASE_CAT12 (INFO_BASE + 0x80050)
114#define DESIG_UNIQUE_ID_BASE_CAT3456 (INFO_BASE + 0x800D0)
115
116/* ST provided factory calibration values @ 3.0V */
117#define ST_VREFINT_CAL MMIO16(0x1FF80078)
118#define ST_TSENSE_CAL1_30C MMIO16(0x1FF8007A)
119#define ST_TSENSE_CAL2_110C MMIO16(0x1FF8007E)
120
121#endif