libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
otg_hs.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20/*
21 * This file covers definitions for DesignWare USB OTG HS peripherals.
22 */
23
24#ifndef LIBOPENCM3_USB_DWC_OTG_HS_H
25#define LIBOPENCM3_USB_DWC_OTG_HS_H
26
27#include <libopencm3/cm3/common.h>
28#include <libopencm3/usb/dwc/otg_common.h>
29
30/* Memory map is required for USB_OTG_HS_BASE address */
31#if defined(STM32F2) || defined(STM32F4) || defined(STM32F7)
32# include <libopencm3/stm32/memorymap.h>
33#else
34# error "device family not supported by dwc/otg_hs."
35#endif
36
37/* OTG_HS specific registers */
38
39/* Host-mode Control and Status Registers */
40#define OTG_HCSPLT(x) (0x504 + 0x20*(x))
41#define OTG_HCDMA(x) (0x514 + 0x20*(x))
42
43/* Device-mode Control and Status Registers */
44#define OTG_DEACHHINT 0x838
45#define OTG_DEACHHINTMSK 0x83C
46#define OTG_DIEPEACHMSK1 0x844
47#define OTG_DOEPEACHMSK1 0x884
48#define OTG_DIEPDMA(x) (0x914 + 0x20*(x))
49#define OTG_DOEPDMA(x) (0xB14 + 0x20*(x))
50
51
52
53/***********************************************************************/
54
55/* Core Global Control and Status Registers */
56#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL)
57#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT)
58#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG)
59#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG)
60#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL)
61#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS)
62#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK)
63#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR)
64#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP)
65#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ)
66#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ)
67#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS)
68#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG)
69#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID)
70#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ)
71#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x))
72
73/* Host-mode Control and Status Registers */
74#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG)
75#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR)
76#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM)
77#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS)
78#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
79#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
80#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
81#define OTG_HS_HCCHAR(x) MMIO32(USB_OTG_HS_BASE + OTG_HCCHAR(x))
82#define OTG_HS_HCSPLT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCSPLT(x))
83#define OTG_HS_HCINT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINT(x))
84#define OTG_HS_HCINTMSK(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSK(x))
85#define OTG_HS_HCTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZ(x))
86#define OTG_HS_HCDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_HCDMA(x))
87
88/* Device-mode Control and Status Registers */
89#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
90#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL)
91#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS)
92#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK)
93#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK)
94#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT)
95#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK)
96#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS)
97#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE)
98#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK)
99#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0)
100#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x))
101#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0)
102#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x))
103#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x))
104#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
105#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
106#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
107#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
108 OTG_DIEPTSIZ(x))
109#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
110#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
111 OTG_DOEPTSIZ(x))
112#define OTG_HS_DEACHHINT MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINT)
113#define OTG_HS_DEACHHINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINTMSK)
114#define OTG_HS_DIEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEACHMSK1)
115#define OTG_HS_DOEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPEACHMSK1)
116#define OTG_HS_DIEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPDMA(x))
117#define OTG_HS_DOEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPDMA(x))
118
119/* Power and clock gating control and status register */
120#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
121
122/* Data FIFO */
123#define OTG_HS_FIFO(x) (&MMIO32(USB_OTG_HS_BASE + OTG_FIFO(x)))
124
125/* Device-mode CSRs*/
126/* OTG device each endpoint interrupt register (OTG_DEACHINT) */
127/* Bits 31:18 - Reserved */
128#define OTG_DEACHHINT_OEP1INT (1 << 17)
129/* Bits 16:2 - Reserved */
130#define OTG_DEACHHINT_IEP1INT (1 << 1)
131/* Bit 0 - Reserved */
132
133/* OTG device each in endpoint-1 interrupt register (OTG_DIEPEACHMSK1) */
134/* Bits 31:14 - Reserved */
135#define OTG_DIEPEACHMSK1_NAKM (1 << 13)
136/* Bits 12:10 - Reserved */
137#define OTG_DIEPEACHMSK1_BIM (1 << 9)
138#define OTG_DIEPEACHMSK1_TXFURM (1 << 8)
139/* Bit 7 - Reserved */
140#define OTG_DIEPEACHMSK1_INEPNEM (1 << 6)
141#define OTG_DIEPEACHMSK1_INEPNMM (1 << 5)
142#define OTG_DIEPEACHMSK1_ITTXFEMSK (1 << 4)
143#define OTG_DIEPEACHMSK1_TOM (1 << 3)
144/* Bit 2 - Reserved */
145#define OTG_DIEPEACHMSK1_EPDM (1 << 1)
146#define OTG_DIEPEACHMSK1_XFRCM (1 << 0)
147
148/* OTG device each OUT endpoint-1 interrupt register (OTG_DOEPEACHMSK1) */
149/* Bits 31:15 - Reserved */
150#define OTG_DOEPEACHMSK1_NYETM (1 << 14)
151#define OTG_DOEPEACHMSK1_NAKM (1 << 13)
152#define OTG_DOEPEACHMSK1_BERRM (1 << 12)
153/* Bits 11:10 - Reserved */
154#define OTG_DOEPEACHMSK1_BIM (1 << 9)
155#define OTG_DOEPEACHMSK1_OPEM (1 << 8)
156/* Bits 7:3 - Reserved */
157#define OTG_DOEPEACHMSK1_AHBERRM (1 << 2)
158#define OTG_DOEPEACHMSK1_EPDM (1 << 1)
159#define OTG_DOEPEACHMSK1_XFRCM (1 << 0)
160
161/* Host-mode CSRs */
162/* OTG host channel-x split control register (OTG_HCSPLTx) */
163#define OTG_HCSPLT_SPLITEN (1 << 31)
164/* Bits 30:17 - Reserved */
165#define OTG_HCSPLT_COMPLSPLT (1 << 16)
166#define OTG_HCSPLT_XACTPOS_ALL (0x3 << 14)
167#define OTG_HCSPLT_XACTPOS_BEGIN (0x2 << 14)
168#define OTG_HCSPLT_XACTPOS_MID (0x0 << 14)
169#define OTG_HCSPLT_XACTPOS_END (0x1 << 14)
170#define OTG_HCSPLT_HUBADDR_MASK (0x7f << 7)
171#define OTG_HCSPLT_PORTADDR_MASK (0x7f << 0)
172
173#endif
otg_common.h