High-level clock control API

Collaboration diagram for High-level clock control API:

Functions
void	rcc_change_pll_divisor (uint8_t pll_div400)
	Change the PLL divisor. More...
uint32_t	rcc_get_system_clock_frequency (void)
	Get the system clock frequency. More...
static uint32_t	xtal_to_freq (enum xtal_t xtal)
void	rcc_sysclk_config (enum osc_src src, enum xtal_t xtal, uint8_t pll_div400)
	Configure the system clock source. More...

Detailed Description

Function Documentation

rcc_change_pll_divisor()

void rcc_change_pll_divisor

(

uint8_t

pll_div400

)

Change the PLL divisor.

Changes the divisor applied to the 400MHz PLL clock. The PLL must have previously been configured by selecting an appropriate XTAL value, and turning on the PLL. This function does not reconfigure the XTAL value or oscillator source. It only changes the PLL divisor.

The PLL is bypassed before modifying the divisor, and the function blocks until the PLL is locked, then the bypass is disabled, before returning.

Parameters

[in]

pll_div400

The clock divisor to apply to the 400MHz PLL clock.

Definition at line 364 of file rcc.c.

References lm4f_rcc_sysclk_freq, rcc_pll_bypass_disable(), rcc_pll_bypass_enable(), rcc_set_pll_divisor(), and rcc_wait_for_pll_ready().

Referenced by rcc_sysclk_config().

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rcc_get_system_clock_frequency()

uint32_t rcc_get_system_clock_frequency

(

void

)

Get the system clock frequency.

Returns

System clock frequency in Hz

Definition at line 383 of file rcc.c.

References lm4f_rcc_sysclk_freq.

Referenced by uart_set_baudrate().

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rcc_sysclk_config()

void rcc_sysclk_config	(	enum osc_src	src,
		enum xtal_t	xtal,
		uint8_t	pll_div400
	)

Configure the system clock source.

Sets up the system clock, including configuring the oscillator source, and PLL to achieve the desired system clock frequency. Where applicable, The LM4F clock API uses the new RCC2 register to configure clock parameters.

Enables the main oscillator if the clock source is OSCSRC_MOSC. If the main oscillator was previously enabled, it will not be disabled. If desired, it can be separately disabled by a call to rcc_disable_main_osc().

Configures the system clock to run from the 400MHz PLL with a divisor of pll_div400 applied. If pll_div400 is 0, then the PLL is disabled, and the system clock is configured to run off a "raw" clock. If the PLL was previously powered on, it will not be disabled. If desired, it can de powered off by a call to rcc_pll_off().

Parameters

[in]	osc_src	Oscillator from where to derive the system clock.
[in]	xtal	Type of crystal connected to the OSCO/OSCI pins
[in]	pll_div400	The clock divisor to apply to the 400MHz PLL clock. If 0, then the PLL is disabled, and the system runs off a "raw" clock.

Returns

System clock frequency in Hz

Definition at line 443 of file rcc.c.

References lm4f_rcc_sysclk_freq, OSCSRC_30K_INT, OSCSRC_32K_EXT, OSCSRC_MOSC, OSCSRC_PIOSC, OSCSRC_PIOSC_D4, rcc_change_pll_divisor(), rcc_configure_xtal(), rcc_enable_main_osc(), rcc_enable_rcc2(), rcc_pll_bypass_enable(), rcc_pll_on(), rcc_set_osc_source(), and xtal_to_freq().

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xtal_to_freq()

static uint32_t xtal_to_freq ( enum xtal_t  xtal )

static

Definition at line 389 of file rcc.c.

References XTAL_4M.

Referenced by rcc_sysclk_config().

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