System Control Registers. More...
Macros | |
| #define | SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000) |
| Device Identification 0. More... | |
| #define | SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004) |
| Device Identification 1. More... | |
| #define | SYSCTL_PTBOCTL MMIO32(SYSCTL_BASE + 0x038) |
| Power-Temp Brownout Control. More... | |
| #define | SYSCTL_RIS MMIO32(SYSCTL_BASE + 0x050) |
| Raw Interrupt Status. More... | |
| #define | SYSCTL_IMC MMIO32(SYSCTL_BASE + 0x054) |
| Interrupt Mask Control. More... | |
| #define | SYSCTL_MISC MMIO32(SYSCTL_BASE + 0x058) |
| RW1C Masked Interrupt Status and Clear. More... | |
| #define | SYSCTL_RESC MMIO32(SYSCTL_BASE + 0x05C) |
| Reset Cause. More... | |
| #define | SYSCTL_PWRTC MMIO32(SYSCTL_BASE + 0x060) |
| RW1C Power-Temperature Cause. More... | |
| #define | SYSCTL_NMIC MMIO32(SYSCTL_BASE + 0x064) |
| NMI Cause Register. More... | |
| #define | SYSCTL_MOSCCTL MMIO32(SYSCTL_BASE + 0x07C) |
| Main Oscillator Control. More... | |
| #define | SYSCTL_RSCLKCFG MMIO32(SYSCTL_BASE + 0x0B0) |
| Run and Sleep Mode Configuration Register. More... | |
| #define | SYSCTL_MEMTIM0 MMIO32(SYSCTL_BASE + 0x0C0) |
| Memory Timing Parameter Register 0 for Main Flash and EEPROM. More... | |
| #define | SYSCTL_ALTCLKCFG MMIO32(SYSCTL_BASE + 0x138) |
| Alternate Clock Configuration. More... | |
| #define | SYSCTL_DSCLKCFG MMIO32(SYSCTL_BASE + 0x144) |
| Deep Sleep Clock Configuration Register. More... | |
| #define | SYSCTL_DIVSCLK MMIO32(SYSCTL_BASE + 0x148) |
| Divisor and Source Clock Configuration. More... | |
| #define | SYSCTL_SYSPROP MMIO32(SYSCTL_BASE + 0x14C) |
| System Properties. More... | |
| #define | SYSCTL_PIOSCCAL MMIO32(SYSCTL_BASE + 0x150) |
| Precision Internal Oscillator Calibration. More... | |
| #define | SYSCTL_PIOSCSTAT MMIO32(SYSCTL_BASE + 0x154) |
| Precision Internal Oscillator Statistics. More... | |
| #define | SYSCTL_PLLFREQ0 MMIO32(SYSCTL_BASE + 0x160) |
| PLL Frequency 0. More... | |
| #define | SYSCTL_PLLFREQ1 MMIO32(SYSCTL_BASE + 0x164) |
| PLL Frequency 1. More... | |
| #define | SYSCTL_PLLSTAT MMIO32(SYSCTL_BASE + 0x168) |
| PLL Status. More... | |
| #define | SYSCTL_SLPPWRCFG MMIO32(SYSCTL_BASE + 0x188) |
| Sleep Power Configuration. More... | |
| #define | SYSCTL_DSLPPWRCFG MMIO32(SYSCTL_BASE + 0x18C) |
| Deep-Sleep Power Configuration. More... | |
| #define | SYSCTL_NVMSTAT MMIO32(SYSCTL_BASE + 0x1A0) |
| Non-Volatile Memory Information. More... | |
| #define | SYSCTL_LDOSPCTL MMIO32(SYSCTL_BASE + 0x1B4) |
| LDO Sleep Power Control. More... | |
| #define | SYSCTL_LDOSPCAL MMIO32(SYSCTL_BASE + 0x1B8) |
| LDO Sleep Power Calibration. More... | |
| #define | SYSCTL_LDODPCTL MMIO32(SYSCTL_BASE + 0x1BC) |
| LDO Deep-Sleep Power Control. More... | |
| #define | SYSCTL_LDODPCAL MMIO32(SYSCTL_BASE + 0x1C0) |
| LDO Deep-Sleep Power Calibration. More... | |
| #define | SYSCTL_SDPMST MMIO32(SYSCTL_BASE + 0x1CC) |
| Sleep / Deep-Sleep Power Mode Status. More... | |
| #define | SYSCTL_RESBEHAVCTL MMIO32(SYSCTL_BASE + 0x1D8) |
| Reset Behavior Control Register. More... | |
| #define | SYSCTL_HSSR MMIO32(SYSCTL_BASE + 0x1F4) |
| Hardware System Service Request. More... | |
| #define | SYSCTL_USBPDS MMIO32(SYSCTL_BASE + 0x280) |
| USB Power Domain Status. More... | |
| #define | SYSCTL_USBMPC MMIO32(SYSCTL_BASE + 0x284) |
| USB Memory Power Control. More... | |
| #define | SYSCTL_EMACPDS MMIO32(SYSCTL_BASE + 0x288) |
| Ethernet MAC Power Domain Status. More... | |
| #define | SYSCTL_EMACMPC MMIO32(SYSCTL_BASE + 0x28C) |
| Ethernet MAC Memory Power Control. More... | |
| #define | SYSCTL_LCDPDS MMIO32(SYSCTL_BASE + 0x290) |
| LCD Power Domain Status. More... | |
| #define | SYSCTL_LCDMPC MMIO32(SYSCTL_BASE + 0x294) |
| LCD Memory Power Control. More... | |
| #define | SYSCTL_CAN0PDS MMIO32(SYSCTL_BASE + 0x298) |
| CAN 0 Power Domain Status. More... | |
| #define | SYSCTL_CAN0MPC MMIO32(SYSCTL_BASE + 0x29C) |
| CAN 0 Memory Power Control. More... | |
| #define | SYSCTL_CAN1PDS MMIO32(SYSCTL_BASE + 0x2A0) |
| CAN 1 Power Domain Status. More... | |
| #define | SYSCTL_CAN1MPC MMIO32(SYSCTL_BASE + 0x2A4) |
| CAN 1 Memory Power Control. More... | |
| #define | SYSCTL_PPWD MMIO32(SYSCTL_BASE + 0x300) |
| Watchdog Timer Peripheral Present. More... | |
| #define | SYSCTL_PPTIMER MMIO32(SYSCTL_BASE + 0x304) |
| 16/32-Bit General-Purpose Timer Peripheral Present More... | |
| #define | SYSCTL_PPGPIO MMIO32(SYSCTL_BASE + 0x308) |
| General-Purpose Input/Output Peripheral Present. More... | |
| #define | SYSCTL_PPDMA MMIO32(SYSCTL_BASE + 0x30C) |
| Micro Direct Memory Access Peripheral Present. More... | |
| #define | SYSCTL_PPEPI MMIO32(SYSCTL_BASE + 0x310) |
| EPI Peripheral Present. More... | |
| #define | SYSCTL_PPHIB MMIO32(SYSCTL_BASE + 0x314) |
| Hibernation Peripheral Present. More... | |
| #define | SYSCTL_PPUART MMIO32(SYSCTL_BASE + 0x318) |
| Universal Asynchronous Receiver/Transmitter Peripheral Present. More... | |
| #define | SYSCTL_PPSSI MMIO32(SYSCTL_BASE + 0x31C) |
| Synchronous Serial Interface Peripheral Present. More... | |
| #define | SYSCTL_PPI2C MMIO32(SYSCTL_BASE + 0x320) |
| Inter-Integrated Circuit Peripheral Present. More... | |
| #define | SYSCTL_PPUSB MMIO32(SYSCTL_BASE + 0x328) |
| Universal Serial Bus Peripheral Present. More... | |
| #define | SYSCTL_PPEPHY MMIO32(SYSCTL_BASE + 0x330) |
| Ethernet PHY Peripheral Present. More... | |
| #define | SYSCTL_PPCAN MMIO32(SYSCTL_BASE + 0x334) |
| Controller Area Network Peripheral Present. More... | |
| #define | SYSCTL_PPADC MMIO32(SYSCTL_BASE + 0x338) |
| Analog-to-Digital Converter Peripheral Present. More... | |
| #define | SYSCTL_PPACMP MMIO32(SYSCTL_BASE + 0x33C) |
| Analog Comparator Peripheral Present. More... | |
| #define | SYSCTL_PPPWM MMIO32(SYSCTL_BASE + 0x340) |
| Pulse Width Modulator Peripheral Present. More... | |
| #define | SYSCTL_PPQEI MMIO32(SYSCTL_BASE + 0x344) |
| Quadrature Encoder Interface Peripheral Present. More... | |
| #define | SYSCTL_PPEEPROM MMIO32(SYSCTL_BASE + 0x358) |
| EEPROM Peripheral Present. More... | |
| #define | SYSCTL_PPCCM MMIO32(SYSCTL_BASE + 0x374) |
| CRC and Cryptographic Modules Peripheral Present. More... | |
| #define | SYSCTL_PPLCD MMIO32(SYSCTL_BASE + 0x390) |
| LCD Peripheral Present. More... | |
| #define | SYSCTL_PPOWIRE MMIO32(SYSCTL_BASE + 0x398) |
| 1-Wire Peripheral Present More... | |
| #define | SYSCTL_PPEMAC MMIO32(SYSCTL_BASE + 0x39C) |
| Ethernet MAC Peripheral Present. More... | |
| #define | SYSCTL_PPPRB MMIO32(SYSCTL_BASE + 0x3A0) |
| Power Regulator Bus Peripheral Present. More... | |
| #define | SYSCTL_SRWD MMIO32(SYSCTL_BASE + 0x500) |
| Watchdog Timer Software Reset. More... | |
| #define | SYSCTL_SRTIMER MMIO32(SYSCTL_BASE + 0x504) |
| 16/32-Bit General-Purpose Timer Software Reset More... | |
| #define | SYSCTL_SRGPIO MMIO32(SYSCTL_BASE + 0x508) |
| General-Purpose Input/Output Software Reset. More... | |
| #define | SYSCTL_SRDMA MMIO32(SYSCTL_BASE + 0x50C) |
| Micro Direct Memory Access Software Reset. More... | |
| #define | SYSCTL_SREPI MMIO32(SYSCTL_BASE + 0x510) |
| EPI Software Reset. More... | |
| #define | SYSCTL_SRHIB MMIO32(SYSCTL_BASE + 0x514) |
| Hibernation Software Reset. More... | |
| #define | SYSCTL_SRUART MMIO32(SYSCTL_BASE + 0x518) |
| Universal Asynchronous Receiver/Transmitter Software Reset. More... | |
| #define | SYSCTL_SRSSI MMIO32(SYSCTL_BASE + 0x51C) |
| Synchronous Serial Interface Software Reset. More... | |
| #define | SYSCTL_SRI2C MMIO32(SYSCTL_BASE + 0x520) |
| Inter-Integrated Circuit Software Reset. More... | |
| #define | SYSCTL_SRUSB MMIO32(SYSCTL_BASE + 0x528) |
| Universal Serial Bus Software Reset. More... | |
| #define | SYSCTL_SREPHY MMIO32(SYSCTL_BASE + 0x530) |
| Ethernet PHY Software Reset. More... | |
| #define | SYSCTL_SRCAN MMIO32(SYSCTL_BASE + 0x534) |
| Controller Area Network Software Reset. More... | |
| #define | SYSCTL_SRADC MMIO32(SYSCTL_BASE + 0x538) |
| Analog-to-Digital Converter Software Reset. More... | |
| #define | SYSCTL_SRACMP MMIO32(SYSCTL_BASE + 0x53C) |
| Analog Comparator Software Reset. More... | |
| #define | SYSCTL_SRPWM MMIO32(SYSCTL_BASE + 0x540) |
| Pulse Width Modulator Software Reset. More... | |
| #define | SYSCTL_SRQEI MMIO32(SYSCTL_BASE + 0x544) |
| Quadrature Encoder Interface Software Reset. More... | |
| #define | SYSCTL_SREEPROM MMIO32(SYSCTL_BASE + 0x558) |
| EEPROM Software Reset. More... | |
| #define | SYSCTL_SRCCM MMIO32(SYSCTL_BASE + 0x574) |
| CRC and Cryptographic Modules Software Reset. More... | |
| #define | SYSCTL_SRLCD MMIO32(SYSCTL_BASE + 0x590) |
| LCD Controller Software Reset. More... | |
| #define | SYSCTL_SROWIRE MMIO32(SYSCTL_BASE + 0x598) |
| 1-Wire Software Reset More... | |
| #define | SYSCTL_SREMAC MMIO32(SYSCTL_BASE + 0x59C) |
| Ethernet MAC Software Reset. More... | |
| #define | SYSCTL_RCGCWD MMIO32(SYSCTL_BASE + 0x600) |
| Watchdog Timer Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCTIMER MMIO32(SYSCTL_BASE + 0x604) |
| 16/32-BitGeneral-Purpose Timer RunMode Clock Gating Control More... | |
| #define | SYSCTL_RCGCGPIO MMIO32(SYSCTL_BASE + 0x608) |
| General-Purpose Input/Output Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCDMA MMIO32(SYSCTL_BASE + 0x60C) |
| Micro Direct Memory Access Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCEPI MMIO32(SYSCTL_BASE + 0x610) |
| EPI Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCHIB MMIO32(SYSCTL_BASE + 0x614) |
| Hibernation Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCUART MMIO32(SYSCTL_BASE + 0x618) |
| Universal Asynchronous Receiver/Transmitter RunMode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCSSI MMIO32(SYSCTL_BASE + 0x61C) |
| Synchronous Serial Interface Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCI2C MMIO32(SYSCTL_BASE + 0x620) |
| Inter-Integrated Circuit Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCUSB MMIO32(SYSCTL_BASE + 0x628) |
| Universal Serial Bus Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCEPHY MMIO32(SYSCTL_BASE + 0x630) |
| Ethernet PHY Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCCAN MMIO32(SYSCTL_BASE + 0x634) |
| Controller Area Network RunMode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCADC MMIO32(SYSCTL_BASE + 0x638) |
| Analog-to-Digital Converter Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCACMP MMIO32(SYSCTL_BASE + 0x63C) |
| Analog Comparator Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCPWM MMIO32(SYSCTL_BASE + 0x640) |
| Pulse Width Modulator Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCQEI MMIO32(SYSCTL_BASE + 0x644) |
| Quadrature Encoder Interface Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCEEPROM MMIO32(SYSCTL_BASE + 0x658) |
| EEPROM Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCCCM MMIO32(SYSCTL_BASE + 0x674) |
| CRC and CryptographicModules RunMode ClockGating Control. More... | |
| #define | SYSCTL_RCGCLCD MMIO32(SYSCTL_BASE + 0x690) |
| LCD Controller Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_RCGCOWIRE MMIO32(SYSCTL_BASE + 0x698) |
| 1-Wire Run Mode Clock Gating Control More... | |
| #define | SYSCTL_RCGCEMAC MMIO32(SYSCTL_BASE + 0x69C) |
| Ethernet MAC Run Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCWD MMIO32(SYSCTL_BASE + 0x700) |
| Watchdog Timer Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCTIMER MMIO32(SYSCTL_BASE + 0x704) |
| 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control More... | |
| #define | SYSCTL_SCGCGPIO MMIO32(SYSCTL_BASE + 0x708) |
| General-Purpose Input/Output Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCDMA MMIO32(SYSCTL_BASE + 0x70C) |
| Micro Direct Memory Access Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCEPI MMIO32(SYSCTL_BASE + 0x710) |
| EPI Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCHIB MMIO32(SYSCTL_BASE + 0x714) |
| Hibernation Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCUART MMIO32(SYSCTL_BASE + 0x718) |
| Universal Asynchronous Receiver/Transmitter S Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCSSI MMIO32(SYSCTL_BASE + 0x71C) |
| Synchronous Serial Interface Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCI2C MMIO32(SYSCTL_BASE + 0x720) |
| Inter-Integrated Circuit Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCUSB MMIO32(SYSCTL_BASE + 0x728) |
| Universal Serial Bus Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCEPHY MMIO32(SYSCTL_BASE + 0x730) |
| Ethernet PHY Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCCAN MMIO32(SYSCTL_BASE + 0x734) |
| Controller Area Network Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCADC MMIO32(SYSCTL_BASE + 0x738) |
| Analog-to-Digital Converter Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCACMP MMIO32(SYSCTL_BASE + 0x73C) |
| Analog Comparator Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCPWM MMIO32(SYSCTL_BASE + 0x740) |
| PulseWidthModulator Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCQEI MMIO32(SYSCTL_BASE + 0x744) |
| Quadrature Encoder Interface Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCEEPROM MMIO32(SYSCTL_BASE + 0x758) |
| EEPROM Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCCCM MMIO32(SYSCTL_BASE + 0x774) |
| CRC and Cryptographic Modules Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCLCD MMIO32(SYSCTL_BASE + 0x790) |
| LCD Controller Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_SCGCOWIRE MMIO32(SYSCTL_BASE + 0x798) |
| 1-Wire Sleep Mode Clock Gating Control More... | |
| #define | SYSCTL_SCGCEMAC MMIO32(SYSCTL_BASE + 0x79C) |
| Ethernet MAC Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCWD MMIO32(SYSCTL_BASE + 0x800) |
| Watchdog Timer Deep-SleepMode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCTIMER MMIO32(SYSCTL_BASE + 0x804) |
| Clock 16/32-Bit General-Purpose Timer Deep-Sleep Mode Gating Control. More... | |
| #define | SYSCTL_DCGCGPIO MMIO32(SYSCTL_BASE + 0x808) |
| General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCDMA MMIO32(SYSCTL_BASE + 0x80C) |
| Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCEPI MMIO32(SYSCTL_BASE + 0x810) |
| EPI Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCHIB MMIO32(SYSCTL_BASE + 0x814) |
| Hibernation Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCUART MMIO32(SYSCTL_BASE + 0x818) |
| Universal Asynchronous Receiver/Transmitter D-S Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCSSI MMIO32(SYSCTL_BASE + 0x81C) |
| Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCI2C MMIO32(SYSCTL_BASE + 0x820) |
| Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCUSB MMIO32(SYSCTL_BASE + 0x828) |
| Universal Serial Bus Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCEPHY MMIO32(SYSCTL_BASE + 0x830) |
| Ethernet PHY Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCCAN MMIO32(SYSCTL_BASE + 0x834) |
| Controller Area Network Deep-SleepMode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCADC MMIO32(SYSCTL_BASE + 0x838) |
| Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCACMP MMIO32(SYSCTL_BASE + 0x83C) |
| Analog Comparator Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCPWM MMIO32(SYSCTL_BASE + 0x840) |
| Pulse Width Modulator Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCQEI MMIO32(SYSCTL_BASE + 0x844) |
| Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCEEPROM MMIO32(SYSCTL_BASE + 0x858) |
| EEPROM Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCCCM MMIO32(SYSCTL_BASE + 0x874) |
| CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCLCD MMIO32(SYSCTL_BASE + 0x890) |
| LCD Controller Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_DCGCOWIRE MMIO32(SYSCTL_BASE + 0x898) |
| 1-Wire Deep-Sleep Mode Clock Gating Control More... | |
| #define | SYSCTL_DCGCEMAC MMIO32(SYSCTL_BASE + 0x89C) |
| Ethernet MAC Deep-Sleep Mode Clock Gating Control. More... | |
| #define | SYSCTL_PCWD MMIO32(SYSCTL_BASE + 0x900) |
| Watchdog Timer Power Control. More... | |
| #define | SYSCTL_PCTIMER MMIO32(SYSCTL_BASE + 0x904) |
| 16/32-Bit General-Purpose Timer Power Control More... | |
| #define | SYSCTL_PCGPIO MMIO32(SYSCTL_BASE + 0x908) |
| General-Purpose Input/Output Power Control. More... | |
| #define | SYSCTL_PCDMA MMIO32(SYSCTL_BASE + 0x90C) |
| Micro Direct Memory Access Power Control. More... | |
| #define | SYSCTL_PCEPI MMIO32(SYSCTL_BASE + 0x910) |
| External Peripheral Interface Power Control. More... | |
| #define | SYSCTL_PCHIB MMIO32(SYSCTL_BASE + 0x914) |
| Hibernation Power Control. More... | |
| #define | SYSCTL_PCUART MMIO32(SYSCTL_BASE + 0x918) |
| Universal Asynchronous Receiver/Transmitter Power Control. More... | |
| #define | SYSCTL_PCSSI MMIO32(SYSCTL_BASE + 0x91C) |
| Synchronous Serial Interface Power Control. More... | |
| #define | SYSCTL_PCI2C MMIO32(SYSCTL_BASE + 0x920) |
| Inter-Integrated Circuit Power Control. More... | |
| #define | SYSCTL_PCUSB MMIO32(SYSCTL_BASE + 0x928) |
| Universal Serial Bus Power Control. More... | |
| #define | SYSCTL_PCEPHY MMIO32(SYSCTL_BASE + 0x930) |
| Ethernet PHY Power Control. More... | |
| #define | SYSCTL_PCCAN MMIO32(SYSCTL_BASE + 0x934) |
| Controller Area Network Power Control. More... | |
| #define | SYSCTL_PCADC MMIO32(SYSCTL_BASE + 0x938) |
| Analog-to-Digital Converter Power Control. More... | |
| #define | SYSCTL_PCACMP MMIO32(SYSCTL_BASE + 0x93C) |
| Analog Comparator Power Control. More... | |
| #define | SYSCTL_PCPWM MMIO32(SYSCTL_BASE + 0x940) |
| Pulse Width Modulator Power Control. More... | |
| #define | SYSCTL_PCQEI MMIO32(SYSCTL_BASE + 0x944) |
| Quadrature Encoder Interface Power Control. More... | |
| #define | SYSCTL_PCEEPROM MMIO32(SYSCTL_BASE + 0x958) |
| EEPROM Power Control. More... | |
| #define | SYSCTL_PCCCM MMIO32(SYSCTL_BASE + 0x974) |
| CRC and Cryptographic Modules Power Control. More... | |
| #define | SYSCTL_PCLCD MMIO32(SYSCTL_BASE + 0x990) |
| LCD Controller Power Control. More... | |
| #define | SYSCTL_PCOWIRE MMIO32(SYSCTL_BASE + 0x998) |
| 1-Wire Power Control More... | |
| #define | SYSCTL_PCEMAC MMIO32(SYSCTL_BASE + 0x99C) |
| Ethernet MAC Power Control. More... | |
| #define | SYSCTL_PRWD MMIO32(SYSCTL_BASE + 0xA00) |
| Watchdog Timer Peripheral Ready. More... | |
| #define | SYSCTL_PRTIMER MMIO32(SYSCTL_BASE + 0xA04) |
| 16/32-Bit General-Purpose Timer Peripheral Ready More... | |
| #define | SYSCTL_PRGPIO MMIO32(SYSCTL_BASE + 0xA08) |
| General-Purpose Input/Output Peripheral Ready. More... | |
| #define | SYSCTL_PRDMA MMIO32(SYSCTL_BASE + 0xA0C) |
| Micro Direct Memory Access Peripheral Ready. More... | |
| #define | SYSCTL_PREPI MMIO32(SYSCTL_BASE + 0xA10) |
| EPI Peripheral Ready. More... | |
| #define | SYSCTL_PRHIB MMIO32(SYSCTL_BASE + 0xA14) |
| Hibernation Peripheral Ready. More... | |
| #define | SYSCTL_PRUART MMIO32(SYSCTL_BASE + 0xA18) |
| Universal Asynchronous Receiver/Transmitter Peripheral Ready. More... | |
| #define | SYSCTL_PRSSI MMIO32(SYSCTL_BASE + 0xA1C) |
| Synchronous Serial Interface Peripheral Ready. More... | |
| #define | SYSCTL_PRI2C MMIO32(SYSCTL_BASE + 0xA20) |
| Inter-Integrated Circuit Peripheral Ready. More... | |
| #define | SYSCTL_PRUSB MMIO32(SYSCTL_BASE + 0xA28) |
| Universal Serial Bus Peripheral Ready. More... | |
| #define | SYSCTL_PREPHY MMIO32(SYSCTL_BASE + 0xA30) |
| Ethernet PHY Peripheral Ready. More... | |
| #define | SYSCTL_PRCAN MMIO32(SYSCTL_BASE + 0xA34) |
| Controller Area Network Peripheral Ready. More... | |
| #define | SYSCTL_PRADC MMIO32(SYSCTL_BASE + 0xA38) |
| Analog-to-Digital Converter Peripheral Ready. More... | |
| #define | SYSCTL_PRACMP MMIO32(SYSCTL_BASE + 0xA3C) |
| Analog Comparator Peripheral Ready. More... | |
| #define | SYSCTL_PRPWM MMIO32(SYSCTL_BASE + 0xA40) |
| Pulse Width Modulator Peripheral Ready. More... | |
| #define | SYSCTL_PRQEI MMIO32(SYSCTL_BASE + 0xA44) |
| Quadrature Encoder Interface Peripheral Ready. More... | |
| #define | SYSCTL_PREEPROM MMIO32(SYSCTL_BASE + 0xA58) |
| EEPROM Peripheral Ready. More... | |
| #define | SYSCTL_PRCCM MMIO32(SYSCTL_BASE + 0xA74) |
| CRC and Cryptographic Modules Peripheral Ready. More... | |
| #define | SYSCTL_PRLCD MMIO32(SYSCTL_BASE + 0xA90) |
| LCD Controller Peripheral Ready. More... | |
| #define | SYSCTL_PROWIRE MMIO32(SYSCTL_BASE + 0xA98) |
| 1-Wire Peripheral Ready More... | |
| #define | SYSCTL_PREMAC MMIO32(SYSCTL_BASE + 0xA9C) |
| Ethernet MAC Peripheral Ready. More... | |
| #define | SYSCTL_UNIQUEID0 MMIO32(SYSCTL_BASE + 0xF20) |
| Unique ID 0. More... | |
| #define | SYSCTL_UNIQUEID1 MMIO32(SYSCTL_BASE + 0xF24) |
| Unique ID 1. More... | |
| #define | SYSCTL_UNIQUEID2 MMIO32(SYSCTL_BASE + 0xF28) |
| Unique ID 2. More... | |
| #define | SYSCTL_UNIQUEID3 MMIO32(SYSCTL_BASE + 0xF2C) |
| Unique ID 3. More... | |
Detailed Description
System Control Registers.
Macro Definition Documentation
◆ SYSCTL_ALTCLKCFG
| #define SYSCTL_ALTCLKCFG MMIO32(SYSCTL_BASE + 0x138) |
Alternate Clock Configuration.
Definition at line 71 of file systemcontrol.h.
◆ SYSCTL_CAN0MPC
| #define SYSCTL_CAN0MPC MMIO32(SYSCTL_BASE + 0x29C) |
CAN 0 Memory Power Control.
Definition at line 123 of file systemcontrol.h.
◆ SYSCTL_CAN0PDS
| #define SYSCTL_CAN0PDS MMIO32(SYSCTL_BASE + 0x298) |
CAN 0 Power Domain Status.
Definition at line 121 of file systemcontrol.h.
◆ SYSCTL_CAN1MPC
| #define SYSCTL_CAN1MPC MMIO32(SYSCTL_BASE + 0x2A4) |
CAN 1 Memory Power Control.
Definition at line 127 of file systemcontrol.h.
◆ SYSCTL_CAN1PDS
| #define SYSCTL_CAN1PDS MMIO32(SYSCTL_BASE + 0x2A0) |
CAN 1 Power Domain Status.
Definition at line 125 of file systemcontrol.h.
◆ SYSCTL_DCGCACMP
| #define SYSCTL_DCGCACMP MMIO32(SYSCTL_BASE + 0x83C) |
Analog Comparator Deep-Sleep Mode Clock Gating Control.
Definition at line 330 of file systemcontrol.h.
◆ SYSCTL_DCGCADC
| #define SYSCTL_DCGCADC MMIO32(SYSCTL_BASE + 0x838) |
Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control.
Definition at line 328 of file systemcontrol.h.
◆ SYSCTL_DCGCCAN
| #define SYSCTL_DCGCCAN MMIO32(SYSCTL_BASE + 0x834) |
Controller Area Network Deep-SleepMode Clock Gating Control.
Definition at line 326 of file systemcontrol.h.
◆ SYSCTL_DCGCCCM
| #define SYSCTL_DCGCCCM MMIO32(SYSCTL_BASE + 0x874) |
CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control.
Definition at line 338 of file systemcontrol.h.
◆ SYSCTL_DCGCDMA
| #define SYSCTL_DCGCDMA MMIO32(SYSCTL_BASE + 0x80C) |
Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control.
Definition at line 310 of file systemcontrol.h.
◆ SYSCTL_DCGCEEPROM
| #define SYSCTL_DCGCEEPROM MMIO32(SYSCTL_BASE + 0x858) |
EEPROM Deep-Sleep Mode Clock Gating Control.
Definition at line 336 of file systemcontrol.h.
◆ SYSCTL_DCGCEMAC
| #define SYSCTL_DCGCEMAC MMIO32(SYSCTL_BASE + 0x89C) |
Ethernet MAC Deep-Sleep Mode Clock Gating Control.
Definition at line 344 of file systemcontrol.h.
◆ SYSCTL_DCGCEPHY
| #define SYSCTL_DCGCEPHY MMIO32(SYSCTL_BASE + 0x830) |
Ethernet PHY Deep-Sleep Mode Clock Gating Control.
Definition at line 324 of file systemcontrol.h.
◆ SYSCTL_DCGCEPI
| #define SYSCTL_DCGCEPI MMIO32(SYSCTL_BASE + 0x810) |
EPI Deep-Sleep Mode Clock Gating Control.
Definition at line 312 of file systemcontrol.h.
◆ SYSCTL_DCGCGPIO
| #define SYSCTL_DCGCGPIO MMIO32(SYSCTL_BASE + 0x808) |
General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control.
Definition at line 308 of file systemcontrol.h.
◆ SYSCTL_DCGCHIB
| #define SYSCTL_DCGCHIB MMIO32(SYSCTL_BASE + 0x814) |
Hibernation Deep-Sleep Mode Clock Gating Control.
Definition at line 314 of file systemcontrol.h.
◆ SYSCTL_DCGCI2C
| #define SYSCTL_DCGCI2C MMIO32(SYSCTL_BASE + 0x820) |
Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control.
Definition at line 320 of file systemcontrol.h.
◆ SYSCTL_DCGCLCD
| #define SYSCTL_DCGCLCD MMIO32(SYSCTL_BASE + 0x890) |
LCD Controller Deep-Sleep Mode Clock Gating Control.
Definition at line 340 of file systemcontrol.h.
◆ SYSCTL_DCGCOWIRE
| #define SYSCTL_DCGCOWIRE MMIO32(SYSCTL_BASE + 0x898) |
1-Wire Deep-Sleep Mode Clock Gating Control
Definition at line 342 of file systemcontrol.h.
◆ SYSCTL_DCGCPWM
| #define SYSCTL_DCGCPWM MMIO32(SYSCTL_BASE + 0x840) |
Pulse Width Modulator Deep-Sleep Mode Clock Gating Control.
Definition at line 332 of file systemcontrol.h.
◆ SYSCTL_DCGCQEI
| #define SYSCTL_DCGCQEI MMIO32(SYSCTL_BASE + 0x844) |
Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control.
Definition at line 334 of file systemcontrol.h.
◆ SYSCTL_DCGCSSI
| #define SYSCTL_DCGCSSI MMIO32(SYSCTL_BASE + 0x81C) |
Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control.
Definition at line 318 of file systemcontrol.h.
◆ SYSCTL_DCGCTIMER
| #define SYSCTL_DCGCTIMER MMIO32(SYSCTL_BASE + 0x804) |
Clock 16/32-Bit General-Purpose Timer Deep-Sleep Mode Gating Control.
Definition at line 306 of file systemcontrol.h.
◆ SYSCTL_DCGCUART
| #define SYSCTL_DCGCUART MMIO32(SYSCTL_BASE + 0x818) |
Universal Asynchronous Receiver/Transmitter D-S Mode Clock Gating Control.
Definition at line 316 of file systemcontrol.h.
◆ SYSCTL_DCGCUSB
| #define SYSCTL_DCGCUSB MMIO32(SYSCTL_BASE + 0x828) |
Universal Serial Bus Deep-Sleep Mode Clock Gating Control.
Definition at line 322 of file systemcontrol.h.
◆ SYSCTL_DCGCWD
| #define SYSCTL_DCGCWD MMIO32(SYSCTL_BASE + 0x800) |
Watchdog Timer Deep-SleepMode Clock Gating Control.
Definition at line 304 of file systemcontrol.h.
◆ SYSCTL_DID0
| #define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000) |
Device Identification 0.
Definition at line 47 of file systemcontrol.h.
◆ SYSCTL_DID1
| #define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004) |
Device Identification 1.
Definition at line 49 of file systemcontrol.h.
◆ SYSCTL_DIVSCLK
| #define SYSCTL_DIVSCLK MMIO32(SYSCTL_BASE + 0x148) |
Divisor and Source Clock Configuration.
Definition at line 75 of file systemcontrol.h.
◆ SYSCTL_DSCLKCFG
| #define SYSCTL_DSCLKCFG MMIO32(SYSCTL_BASE + 0x144) |
Deep Sleep Clock Configuration Register.
Definition at line 73 of file systemcontrol.h.
◆ SYSCTL_DSLPPWRCFG
| #define SYSCTL_DSLPPWRCFG MMIO32(SYSCTL_BASE + 0x18C) |
Deep-Sleep Power Configuration.
Definition at line 91 of file systemcontrol.h.
◆ SYSCTL_EMACMPC
| #define SYSCTL_EMACMPC MMIO32(SYSCTL_BASE + 0x28C) |
Ethernet MAC Memory Power Control.
Definition at line 115 of file systemcontrol.h.
◆ SYSCTL_EMACPDS
| #define SYSCTL_EMACPDS MMIO32(SYSCTL_BASE + 0x288) |
Ethernet MAC Power Domain Status.
Definition at line 113 of file systemcontrol.h.
◆ SYSCTL_HSSR
| #define SYSCTL_HSSR MMIO32(SYSCTL_BASE + 0x1F4) |
Hardware System Service Request.
Definition at line 107 of file systemcontrol.h.
◆ SYSCTL_IMC
| #define SYSCTL_IMC MMIO32(SYSCTL_BASE + 0x054) |
Interrupt Mask Control.
Definition at line 55 of file systemcontrol.h.
◆ SYSCTL_LCDMPC
| #define SYSCTL_LCDMPC MMIO32(SYSCTL_BASE + 0x294) |
LCD Memory Power Control.
Definition at line 119 of file systemcontrol.h.
◆ SYSCTL_LCDPDS
| #define SYSCTL_LCDPDS MMIO32(SYSCTL_BASE + 0x290) |
LCD Power Domain Status.
Definition at line 117 of file systemcontrol.h.
◆ SYSCTL_LDODPCAL
| #define SYSCTL_LDODPCAL MMIO32(SYSCTL_BASE + 0x1C0) |
LDO Deep-Sleep Power Calibration.
Definition at line 101 of file systemcontrol.h.
◆ SYSCTL_LDODPCTL
| #define SYSCTL_LDODPCTL MMIO32(SYSCTL_BASE + 0x1BC) |
LDO Deep-Sleep Power Control.
Definition at line 99 of file systemcontrol.h.
◆ SYSCTL_LDOSPCAL
| #define SYSCTL_LDOSPCAL MMIO32(SYSCTL_BASE + 0x1B8) |
LDO Sleep Power Calibration.
Definition at line 97 of file systemcontrol.h.
◆ SYSCTL_LDOSPCTL
| #define SYSCTL_LDOSPCTL MMIO32(SYSCTL_BASE + 0x1B4) |
LDO Sleep Power Control.
Definition at line 95 of file systemcontrol.h.
◆ SYSCTL_MEMTIM0
| #define SYSCTL_MEMTIM0 MMIO32(SYSCTL_BASE + 0x0C0) |
Memory Timing Parameter Register 0 for Main Flash and EEPROM.
Definition at line 69 of file systemcontrol.h.
◆ SYSCTL_MISC
| #define SYSCTL_MISC MMIO32(SYSCTL_BASE + 0x058) |
RW1C Masked Interrupt Status and Clear.
Definition at line 57 of file systemcontrol.h.
◆ SYSCTL_MOSCCTL
| #define SYSCTL_MOSCCTL MMIO32(SYSCTL_BASE + 0x07C) |
Main Oscillator Control.
Definition at line 65 of file systemcontrol.h.
◆ SYSCTL_NMIC
| #define SYSCTL_NMIC MMIO32(SYSCTL_BASE + 0x064) |
NMI Cause Register.
Definition at line 63 of file systemcontrol.h.
◆ SYSCTL_NVMSTAT
| #define SYSCTL_NVMSTAT MMIO32(SYSCTL_BASE + 0x1A0) |
Non-Volatile Memory Information.
Definition at line 93 of file systemcontrol.h.
◆ SYSCTL_PCACMP
| #define SYSCTL_PCACMP MMIO32(SYSCTL_BASE + 0x93C) |
Analog Comparator Power Control.
Definition at line 373 of file systemcontrol.h.
◆ SYSCTL_PCADC
| #define SYSCTL_PCADC MMIO32(SYSCTL_BASE + 0x938) |
Analog-to-Digital Converter Power Control.
Definition at line 371 of file systemcontrol.h.
◆ SYSCTL_PCCAN
| #define SYSCTL_PCCAN MMIO32(SYSCTL_BASE + 0x934) |
Controller Area Network Power Control.
Definition at line 369 of file systemcontrol.h.
◆ SYSCTL_PCCCM
| #define SYSCTL_PCCCM MMIO32(SYSCTL_BASE + 0x974) |
CRC and Cryptographic Modules Power Control.
Definition at line 381 of file systemcontrol.h.
◆ SYSCTL_PCDMA
| #define SYSCTL_PCDMA MMIO32(SYSCTL_BASE + 0x90C) |
Micro Direct Memory Access Power Control.
Definition at line 353 of file systemcontrol.h.
◆ SYSCTL_PCEEPROM
| #define SYSCTL_PCEEPROM MMIO32(SYSCTL_BASE + 0x958) |
EEPROM Power Control.
Definition at line 379 of file systemcontrol.h.
◆ SYSCTL_PCEMAC
| #define SYSCTL_PCEMAC MMIO32(SYSCTL_BASE + 0x99C) |
Ethernet MAC Power Control.
Definition at line 387 of file systemcontrol.h.
◆ SYSCTL_PCEPHY
| #define SYSCTL_PCEPHY MMIO32(SYSCTL_BASE + 0x930) |
Ethernet PHY Power Control.
Definition at line 367 of file systemcontrol.h.
◆ SYSCTL_PCEPI
| #define SYSCTL_PCEPI MMIO32(SYSCTL_BASE + 0x910) |
External Peripheral Interface Power Control.
Definition at line 355 of file systemcontrol.h.
◆ SYSCTL_PCGPIO
| #define SYSCTL_PCGPIO MMIO32(SYSCTL_BASE + 0x908) |
General-Purpose Input/Output Power Control.
Definition at line 351 of file systemcontrol.h.
◆ SYSCTL_PCHIB
| #define SYSCTL_PCHIB MMIO32(SYSCTL_BASE + 0x914) |
Hibernation Power Control.
Definition at line 357 of file systemcontrol.h.
◆ SYSCTL_PCI2C
| #define SYSCTL_PCI2C MMIO32(SYSCTL_BASE + 0x920) |
Inter-Integrated Circuit Power Control.
Definition at line 363 of file systemcontrol.h.
◆ SYSCTL_PCLCD
| #define SYSCTL_PCLCD MMIO32(SYSCTL_BASE + 0x990) |
LCD Controller Power Control.
Definition at line 383 of file systemcontrol.h.
◆ SYSCTL_PCOWIRE
| #define SYSCTL_PCOWIRE MMIO32(SYSCTL_BASE + 0x998) |
1-Wire Power Control
Definition at line 385 of file systemcontrol.h.
◆ SYSCTL_PCPWM
| #define SYSCTL_PCPWM MMIO32(SYSCTL_BASE + 0x940) |
Pulse Width Modulator Power Control.
Definition at line 375 of file systemcontrol.h.
◆ SYSCTL_PCQEI
| #define SYSCTL_PCQEI MMIO32(SYSCTL_BASE + 0x944) |
Quadrature Encoder Interface Power Control.
Definition at line 377 of file systemcontrol.h.
◆ SYSCTL_PCSSI
| #define SYSCTL_PCSSI MMIO32(SYSCTL_BASE + 0x91C) |
Synchronous Serial Interface Power Control.
Definition at line 361 of file systemcontrol.h.
◆ SYSCTL_PCTIMER
| #define SYSCTL_PCTIMER MMIO32(SYSCTL_BASE + 0x904) |
16/32-Bit General-Purpose Timer Power Control
Definition at line 349 of file systemcontrol.h.
◆ SYSCTL_PCUART
| #define SYSCTL_PCUART MMIO32(SYSCTL_BASE + 0x918) |
Universal Asynchronous Receiver/Transmitter Power Control.
Definition at line 359 of file systemcontrol.h.
◆ SYSCTL_PCUSB
| #define SYSCTL_PCUSB MMIO32(SYSCTL_BASE + 0x928) |
Universal Serial Bus Power Control.
Definition at line 365 of file systemcontrol.h.
◆ SYSCTL_PCWD
| #define SYSCTL_PCWD MMIO32(SYSCTL_BASE + 0x900) |
Watchdog Timer Power Control.
Definition at line 347 of file systemcontrol.h.
◆ SYSCTL_PIOSCCAL
| #define SYSCTL_PIOSCCAL MMIO32(SYSCTL_BASE + 0x150) |
Precision Internal Oscillator Calibration.
Definition at line 79 of file systemcontrol.h.
◆ SYSCTL_PIOSCSTAT
| #define SYSCTL_PIOSCSTAT MMIO32(SYSCTL_BASE + 0x154) |
Precision Internal Oscillator Statistics.
Definition at line 81 of file systemcontrol.h.
◆ SYSCTL_PLLFREQ0
| #define SYSCTL_PLLFREQ0 MMIO32(SYSCTL_BASE + 0x160) |
PLL Frequency 0.
Definition at line 83 of file systemcontrol.h.
◆ SYSCTL_PLLFREQ1
| #define SYSCTL_PLLFREQ1 MMIO32(SYSCTL_BASE + 0x164) |
PLL Frequency 1.
Definition at line 85 of file systemcontrol.h.
◆ SYSCTL_PLLSTAT
| #define SYSCTL_PLLSTAT MMIO32(SYSCTL_BASE + 0x168) |
PLL Status.
Definition at line 87 of file systemcontrol.h.
◆ SYSCTL_PPACMP
| #define SYSCTL_PPACMP MMIO32(SYSCTL_BASE + 0x33C) |
Analog Comparator Peripheral Present.
Definition at line 156 of file systemcontrol.h.
◆ SYSCTL_PPADC
| #define SYSCTL_PPADC MMIO32(SYSCTL_BASE + 0x338) |
Analog-to-Digital Converter Peripheral Present.
Definition at line 154 of file systemcontrol.h.
◆ SYSCTL_PPCAN
| #define SYSCTL_PPCAN MMIO32(SYSCTL_BASE + 0x334) |
Controller Area Network Peripheral Present.
Definition at line 152 of file systemcontrol.h.
◆ SYSCTL_PPCCM
| #define SYSCTL_PPCCM MMIO32(SYSCTL_BASE + 0x374) |
CRC and Cryptographic Modules Peripheral Present.
Definition at line 164 of file systemcontrol.h.
◆ SYSCTL_PPDMA
| #define SYSCTL_PPDMA MMIO32(SYSCTL_BASE + 0x30C) |
Micro Direct Memory Access Peripheral Present.
Definition at line 136 of file systemcontrol.h.
◆ SYSCTL_PPEEPROM
| #define SYSCTL_PPEEPROM MMIO32(SYSCTL_BASE + 0x358) |
EEPROM Peripheral Present.
Definition at line 162 of file systemcontrol.h.
◆ SYSCTL_PPEMAC
| #define SYSCTL_PPEMAC MMIO32(SYSCTL_BASE + 0x39C) |
Ethernet MAC Peripheral Present.
Definition at line 170 of file systemcontrol.h.
◆ SYSCTL_PPEPHY
| #define SYSCTL_PPEPHY MMIO32(SYSCTL_BASE + 0x330) |
Ethernet PHY Peripheral Present.
Definition at line 150 of file systemcontrol.h.
◆ SYSCTL_PPEPI
| #define SYSCTL_PPEPI MMIO32(SYSCTL_BASE + 0x310) |
EPI Peripheral Present.
Definition at line 138 of file systemcontrol.h.
◆ SYSCTL_PPGPIO
| #define SYSCTL_PPGPIO MMIO32(SYSCTL_BASE + 0x308) |
General-Purpose Input/Output Peripheral Present.
Definition at line 134 of file systemcontrol.h.
◆ SYSCTL_PPHIB
| #define SYSCTL_PPHIB MMIO32(SYSCTL_BASE + 0x314) |
Hibernation Peripheral Present.
Definition at line 140 of file systemcontrol.h.
◆ SYSCTL_PPI2C
| #define SYSCTL_PPI2C MMIO32(SYSCTL_BASE + 0x320) |
Inter-Integrated Circuit Peripheral Present.
Definition at line 146 of file systemcontrol.h.
◆ SYSCTL_PPLCD
| #define SYSCTL_PPLCD MMIO32(SYSCTL_BASE + 0x390) |
LCD Peripheral Present.
Definition at line 166 of file systemcontrol.h.
◆ SYSCTL_PPOWIRE
| #define SYSCTL_PPOWIRE MMIO32(SYSCTL_BASE + 0x398) |
1-Wire Peripheral Present
Definition at line 168 of file systemcontrol.h.
◆ SYSCTL_PPPRB
| #define SYSCTL_PPPRB MMIO32(SYSCTL_BASE + 0x3A0) |
Power Regulator Bus Peripheral Present.
Definition at line 172 of file systemcontrol.h.
◆ SYSCTL_PPPWM
| #define SYSCTL_PPPWM MMIO32(SYSCTL_BASE + 0x340) |
Pulse Width Modulator Peripheral Present.
Definition at line 158 of file systemcontrol.h.
◆ SYSCTL_PPQEI
| #define SYSCTL_PPQEI MMIO32(SYSCTL_BASE + 0x344) |
Quadrature Encoder Interface Peripheral Present.
Definition at line 160 of file systemcontrol.h.
◆ SYSCTL_PPSSI
| #define SYSCTL_PPSSI MMIO32(SYSCTL_BASE + 0x31C) |
Synchronous Serial Interface Peripheral Present.
Definition at line 144 of file systemcontrol.h.
◆ SYSCTL_PPTIMER
| #define SYSCTL_PPTIMER MMIO32(SYSCTL_BASE + 0x304) |
16/32-Bit General-Purpose Timer Peripheral Present
Definition at line 132 of file systemcontrol.h.
◆ SYSCTL_PPUART
| #define SYSCTL_PPUART MMIO32(SYSCTL_BASE + 0x318) |
Universal Asynchronous Receiver/Transmitter Peripheral Present.
Definition at line 142 of file systemcontrol.h.
◆ SYSCTL_PPUSB
| #define SYSCTL_PPUSB MMIO32(SYSCTL_BASE + 0x328) |
Universal Serial Bus Peripheral Present.
Definition at line 148 of file systemcontrol.h.
◆ SYSCTL_PPWD
| #define SYSCTL_PPWD MMIO32(SYSCTL_BASE + 0x300) |
Watchdog Timer Peripheral Present.
Definition at line 130 of file systemcontrol.h.
◆ SYSCTL_PRACMP
| #define SYSCTL_PRACMP MMIO32(SYSCTL_BASE + 0xA3C) |
Analog Comparator Peripheral Ready.
Definition at line 416 of file systemcontrol.h.
◆ SYSCTL_PRADC
| #define SYSCTL_PRADC MMIO32(SYSCTL_BASE + 0xA38) |
Analog-to-Digital Converter Peripheral Ready.
Definition at line 414 of file systemcontrol.h.
◆ SYSCTL_PRCAN
| #define SYSCTL_PRCAN MMIO32(SYSCTL_BASE + 0xA34) |
Controller Area Network Peripheral Ready.
Definition at line 412 of file systemcontrol.h.
◆ SYSCTL_PRCCM
| #define SYSCTL_PRCCM MMIO32(SYSCTL_BASE + 0xA74) |
CRC and Cryptographic Modules Peripheral Ready.
Definition at line 424 of file systemcontrol.h.
◆ SYSCTL_PRDMA
| #define SYSCTL_PRDMA MMIO32(SYSCTL_BASE + 0xA0C) |
Micro Direct Memory Access Peripheral Ready.
Definition at line 396 of file systemcontrol.h.
◆ SYSCTL_PREEPROM
| #define SYSCTL_PREEPROM MMIO32(SYSCTL_BASE + 0xA58) |
EEPROM Peripheral Ready.
Definition at line 422 of file systemcontrol.h.
◆ SYSCTL_PREMAC
| #define SYSCTL_PREMAC MMIO32(SYSCTL_BASE + 0xA9C) |
Ethernet MAC Peripheral Ready.
Definition at line 430 of file systemcontrol.h.
◆ SYSCTL_PREPHY
| #define SYSCTL_PREPHY MMIO32(SYSCTL_BASE + 0xA30) |
Ethernet PHY Peripheral Ready.
Definition at line 410 of file systemcontrol.h.
◆ SYSCTL_PREPI
| #define SYSCTL_PREPI MMIO32(SYSCTL_BASE + 0xA10) |
EPI Peripheral Ready.
Definition at line 398 of file systemcontrol.h.
◆ SYSCTL_PRGPIO
| #define SYSCTL_PRGPIO MMIO32(SYSCTL_BASE + 0xA08) |
General-Purpose Input/Output Peripheral Ready.
Definition at line 394 of file systemcontrol.h.
◆ SYSCTL_PRHIB
| #define SYSCTL_PRHIB MMIO32(SYSCTL_BASE + 0xA14) |
Hibernation Peripheral Ready.
Definition at line 400 of file systemcontrol.h.
◆ SYSCTL_PRI2C
| #define SYSCTL_PRI2C MMIO32(SYSCTL_BASE + 0xA20) |
Inter-Integrated Circuit Peripheral Ready.
Definition at line 406 of file systemcontrol.h.
◆ SYSCTL_PRLCD
| #define SYSCTL_PRLCD MMIO32(SYSCTL_BASE + 0xA90) |
LCD Controller Peripheral Ready.
Definition at line 426 of file systemcontrol.h.
◆ SYSCTL_PROWIRE
| #define SYSCTL_PROWIRE MMIO32(SYSCTL_BASE + 0xA98) |
1-Wire Peripheral Ready
Definition at line 428 of file systemcontrol.h.
◆ SYSCTL_PRPWM
| #define SYSCTL_PRPWM MMIO32(SYSCTL_BASE + 0xA40) |
Pulse Width Modulator Peripheral Ready.
Definition at line 418 of file systemcontrol.h.
◆ SYSCTL_PRQEI
| #define SYSCTL_PRQEI MMIO32(SYSCTL_BASE + 0xA44) |
Quadrature Encoder Interface Peripheral Ready.
Definition at line 420 of file systemcontrol.h.
◆ SYSCTL_PRSSI
| #define SYSCTL_PRSSI MMIO32(SYSCTL_BASE + 0xA1C) |
Synchronous Serial Interface Peripheral Ready.
Definition at line 404 of file systemcontrol.h.
◆ SYSCTL_PRTIMER
| #define SYSCTL_PRTIMER MMIO32(SYSCTL_BASE + 0xA04) |
16/32-Bit General-Purpose Timer Peripheral Ready
Definition at line 392 of file systemcontrol.h.
◆ SYSCTL_PRUART
| #define SYSCTL_PRUART MMIO32(SYSCTL_BASE + 0xA18) |
Universal Asynchronous Receiver/Transmitter Peripheral Ready.
Definition at line 402 of file systemcontrol.h.
◆ SYSCTL_PRUSB
| #define SYSCTL_PRUSB MMIO32(SYSCTL_BASE + 0xA28) |
Universal Serial Bus Peripheral Ready.
Definition at line 408 of file systemcontrol.h.
◆ SYSCTL_PRWD
| #define SYSCTL_PRWD MMIO32(SYSCTL_BASE + 0xA00) |
Watchdog Timer Peripheral Ready.
Definition at line 390 of file systemcontrol.h.
◆ SYSCTL_PTBOCTL
| #define SYSCTL_PTBOCTL MMIO32(SYSCTL_BASE + 0x038) |
Power-Temp Brownout Control.
Definition at line 51 of file systemcontrol.h.
◆ SYSCTL_PWRTC
| #define SYSCTL_PWRTC MMIO32(SYSCTL_BASE + 0x060) |
RW1C Power-Temperature Cause.
Definition at line 61 of file systemcontrol.h.
◆ SYSCTL_RCGCACMP
| #define SYSCTL_RCGCACMP MMIO32(SYSCTL_BASE + 0x63C) |
Analog Comparator Run Mode Clock Gating Control.
Definition at line 244 of file systemcontrol.h.
◆ SYSCTL_RCGCADC
| #define SYSCTL_RCGCADC MMIO32(SYSCTL_BASE + 0x638) |
Analog-to-Digital Converter Run Mode Clock Gating Control.
Definition at line 242 of file systemcontrol.h.
◆ SYSCTL_RCGCCAN
| #define SYSCTL_RCGCCAN MMIO32(SYSCTL_BASE + 0x634) |
Controller Area Network RunMode Clock Gating Control.
Definition at line 240 of file systemcontrol.h.
◆ SYSCTL_RCGCCCM
| #define SYSCTL_RCGCCCM MMIO32(SYSCTL_BASE + 0x674) |
CRC and CryptographicModules RunMode ClockGating Control.
Definition at line 252 of file systemcontrol.h.
◆ SYSCTL_RCGCDMA
| #define SYSCTL_RCGCDMA MMIO32(SYSCTL_BASE + 0x60C) |
Micro Direct Memory Access Run Mode Clock Gating Control.
Definition at line 224 of file systemcontrol.h.
◆ SYSCTL_RCGCEEPROM
| #define SYSCTL_RCGCEEPROM MMIO32(SYSCTL_BASE + 0x658) |
EEPROM Run Mode Clock Gating Control.
Definition at line 250 of file systemcontrol.h.
◆ SYSCTL_RCGCEMAC
| #define SYSCTL_RCGCEMAC MMIO32(SYSCTL_BASE + 0x69C) |
Ethernet MAC Run Mode Clock Gating Control.
Definition at line 258 of file systemcontrol.h.
◆ SYSCTL_RCGCEPHY
| #define SYSCTL_RCGCEPHY MMIO32(SYSCTL_BASE + 0x630) |
Ethernet PHY Run Mode Clock Gating Control.
Definition at line 238 of file systemcontrol.h.
◆ SYSCTL_RCGCEPI
| #define SYSCTL_RCGCEPI MMIO32(SYSCTL_BASE + 0x610) |
EPI Run Mode Clock Gating Control.
Definition at line 226 of file systemcontrol.h.
◆ SYSCTL_RCGCGPIO
| #define SYSCTL_RCGCGPIO MMIO32(SYSCTL_BASE + 0x608) |
General-Purpose Input/Output Run Mode Clock Gating Control.
Definition at line 222 of file systemcontrol.h.
◆ SYSCTL_RCGCHIB
| #define SYSCTL_RCGCHIB MMIO32(SYSCTL_BASE + 0x614) |
Hibernation Run Mode Clock Gating Control.
Definition at line 228 of file systemcontrol.h.
◆ SYSCTL_RCGCI2C
| #define SYSCTL_RCGCI2C MMIO32(SYSCTL_BASE + 0x620) |
Inter-Integrated Circuit Run Mode Clock Gating Control.
Definition at line 234 of file systemcontrol.h.
◆ SYSCTL_RCGCLCD
| #define SYSCTL_RCGCLCD MMIO32(SYSCTL_BASE + 0x690) |
LCD Controller Run Mode Clock Gating Control.
Definition at line 254 of file systemcontrol.h.
◆ SYSCTL_RCGCOWIRE
| #define SYSCTL_RCGCOWIRE MMIO32(SYSCTL_BASE + 0x698) |
1-Wire Run Mode Clock Gating Control
Definition at line 256 of file systemcontrol.h.
◆ SYSCTL_RCGCPWM
| #define SYSCTL_RCGCPWM MMIO32(SYSCTL_BASE + 0x640) |
Pulse Width Modulator Run Mode Clock Gating Control.
Definition at line 246 of file systemcontrol.h.
◆ SYSCTL_RCGCQEI
| #define SYSCTL_RCGCQEI MMIO32(SYSCTL_BASE + 0x644) |
Quadrature Encoder Interface Run Mode Clock Gating Control.
Definition at line 248 of file systemcontrol.h.
◆ SYSCTL_RCGCSSI
| #define SYSCTL_RCGCSSI MMIO32(SYSCTL_BASE + 0x61C) |
Synchronous Serial Interface Run Mode Clock Gating Control.
Definition at line 232 of file systemcontrol.h.
◆ SYSCTL_RCGCTIMER
| #define SYSCTL_RCGCTIMER MMIO32(SYSCTL_BASE + 0x604) |
16/32-BitGeneral-Purpose Timer RunMode Clock Gating Control
Definition at line 220 of file systemcontrol.h.
◆ SYSCTL_RCGCUART
| #define SYSCTL_RCGCUART MMIO32(SYSCTL_BASE + 0x618) |
Universal Asynchronous Receiver/Transmitter RunMode Clock Gating Control.
Definition at line 230 of file systemcontrol.h.
◆ SYSCTL_RCGCUSB
| #define SYSCTL_RCGCUSB MMIO32(SYSCTL_BASE + 0x628) |
Universal Serial Bus Run Mode Clock Gating Control.
Definition at line 236 of file systemcontrol.h.
◆ SYSCTL_RCGCWD
| #define SYSCTL_RCGCWD MMIO32(SYSCTL_BASE + 0x600) |
Watchdog Timer Run Mode Clock Gating Control.
Definition at line 218 of file systemcontrol.h.
◆ SYSCTL_RESBEHAVCTL
| #define SYSCTL_RESBEHAVCTL MMIO32(SYSCTL_BASE + 0x1D8) |
Reset Behavior Control Register.
Definition at line 105 of file systemcontrol.h.
◆ SYSCTL_RESC
| #define SYSCTL_RESC MMIO32(SYSCTL_BASE + 0x05C) |
Reset Cause.
Definition at line 59 of file systemcontrol.h.
◆ SYSCTL_RIS
| #define SYSCTL_RIS MMIO32(SYSCTL_BASE + 0x050) |
Raw Interrupt Status.
Definition at line 53 of file systemcontrol.h.
◆ SYSCTL_RSCLKCFG
| #define SYSCTL_RSCLKCFG MMIO32(SYSCTL_BASE + 0x0B0) |
Run and Sleep Mode Configuration Register.
Definition at line 67 of file systemcontrol.h.
◆ SYSCTL_SCGCACMP
| #define SYSCTL_SCGCACMP MMIO32(SYSCTL_BASE + 0x73C) |
Analog Comparator Sleep Mode Clock Gating Control.
Definition at line 287 of file systemcontrol.h.
◆ SYSCTL_SCGCADC
| #define SYSCTL_SCGCADC MMIO32(SYSCTL_BASE + 0x738) |
Analog-to-Digital Converter Sleep Mode Clock Gating Control.
Definition at line 285 of file systemcontrol.h.
◆ SYSCTL_SCGCCAN
| #define SYSCTL_SCGCCAN MMIO32(SYSCTL_BASE + 0x734) |
Controller Area Network Sleep Mode Clock Gating Control.
Definition at line 283 of file systemcontrol.h.
◆ SYSCTL_SCGCCCM
| #define SYSCTL_SCGCCCM MMIO32(SYSCTL_BASE + 0x774) |
CRC and Cryptographic Modules Sleep Mode Clock Gating Control.
Definition at line 295 of file systemcontrol.h.
◆ SYSCTL_SCGCDMA
| #define SYSCTL_SCGCDMA MMIO32(SYSCTL_BASE + 0x70C) |
Micro Direct Memory Access Sleep Mode Clock Gating Control.
Definition at line 267 of file systemcontrol.h.
◆ SYSCTL_SCGCEEPROM
| #define SYSCTL_SCGCEEPROM MMIO32(SYSCTL_BASE + 0x758) |
EEPROM Sleep Mode Clock Gating Control.
Definition at line 293 of file systemcontrol.h.
◆ SYSCTL_SCGCEMAC
| #define SYSCTL_SCGCEMAC MMIO32(SYSCTL_BASE + 0x79C) |
Ethernet MAC Sleep Mode Clock Gating Control.
Definition at line 301 of file systemcontrol.h.
◆ SYSCTL_SCGCEPHY
| #define SYSCTL_SCGCEPHY MMIO32(SYSCTL_BASE + 0x730) |
Ethernet PHY Sleep Mode Clock Gating Control.
Definition at line 281 of file systemcontrol.h.
◆ SYSCTL_SCGCEPI
| #define SYSCTL_SCGCEPI MMIO32(SYSCTL_BASE + 0x710) |
EPI Sleep Mode Clock Gating Control.
Definition at line 269 of file systemcontrol.h.
◆ SYSCTL_SCGCGPIO
| #define SYSCTL_SCGCGPIO MMIO32(SYSCTL_BASE + 0x708) |
General-Purpose Input/Output Sleep Mode Clock Gating Control.
Definition at line 265 of file systemcontrol.h.
◆ SYSCTL_SCGCHIB
| #define SYSCTL_SCGCHIB MMIO32(SYSCTL_BASE + 0x714) |
Hibernation Sleep Mode Clock Gating Control.
Definition at line 271 of file systemcontrol.h.
◆ SYSCTL_SCGCI2C
| #define SYSCTL_SCGCI2C MMIO32(SYSCTL_BASE + 0x720) |
Inter-Integrated Circuit Sleep Mode Clock Gating Control.
Definition at line 277 of file systemcontrol.h.
◆ SYSCTL_SCGCLCD
| #define SYSCTL_SCGCLCD MMIO32(SYSCTL_BASE + 0x790) |
LCD Controller Sleep Mode Clock Gating Control.
Definition at line 297 of file systemcontrol.h.
◆ SYSCTL_SCGCOWIRE
| #define SYSCTL_SCGCOWIRE MMIO32(SYSCTL_BASE + 0x798) |
1-Wire Sleep Mode Clock Gating Control
Definition at line 299 of file systemcontrol.h.
◆ SYSCTL_SCGCPWM
| #define SYSCTL_SCGCPWM MMIO32(SYSCTL_BASE + 0x740) |
PulseWidthModulator Sleep Mode Clock Gating Control.
Definition at line 289 of file systemcontrol.h.
◆ SYSCTL_SCGCQEI
| #define SYSCTL_SCGCQEI MMIO32(SYSCTL_BASE + 0x744) |
Quadrature Encoder Interface Sleep Mode Clock Gating Control.
Definition at line 291 of file systemcontrol.h.
◆ SYSCTL_SCGCSSI
| #define SYSCTL_SCGCSSI MMIO32(SYSCTL_BASE + 0x71C) |
Synchronous Serial Interface Sleep Mode Clock Gating Control.
Definition at line 275 of file systemcontrol.h.
◆ SYSCTL_SCGCTIMER
| #define SYSCTL_SCGCTIMER MMIO32(SYSCTL_BASE + 0x704) |
16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control
Definition at line 263 of file systemcontrol.h.
◆ SYSCTL_SCGCUART
| #define SYSCTL_SCGCUART MMIO32(SYSCTL_BASE + 0x718) |
Universal Asynchronous Receiver/Transmitter S Mode Clock Gating Control.
Definition at line 273 of file systemcontrol.h.
◆ SYSCTL_SCGCUSB
| #define SYSCTL_SCGCUSB MMIO32(SYSCTL_BASE + 0x728) |
Universal Serial Bus Sleep Mode Clock Gating Control.
Definition at line 279 of file systemcontrol.h.
◆ SYSCTL_SCGCWD
| #define SYSCTL_SCGCWD MMIO32(SYSCTL_BASE + 0x700) |
Watchdog Timer Sleep Mode Clock Gating Control.
Definition at line 261 of file systemcontrol.h.
◆ SYSCTL_SDPMST
| #define SYSCTL_SDPMST MMIO32(SYSCTL_BASE + 0x1CC) |
Sleep / Deep-Sleep Power Mode Status.
Definition at line 103 of file systemcontrol.h.
◆ SYSCTL_SLPPWRCFG
| #define SYSCTL_SLPPWRCFG MMIO32(SYSCTL_BASE + 0x188) |
Sleep Power Configuration.
Definition at line 89 of file systemcontrol.h.
◆ SYSCTL_SRACMP
| #define SYSCTL_SRACMP MMIO32(SYSCTL_BASE + 0x53C) |
Analog Comparator Software Reset.
Definition at line 201 of file systemcontrol.h.
◆ SYSCTL_SRADC
| #define SYSCTL_SRADC MMIO32(SYSCTL_BASE + 0x538) |
Analog-to-Digital Converter Software Reset.
Definition at line 199 of file systemcontrol.h.
◆ SYSCTL_SRCAN
| #define SYSCTL_SRCAN MMIO32(SYSCTL_BASE + 0x534) |
Controller Area Network Software Reset.
Definition at line 197 of file systemcontrol.h.
◆ SYSCTL_SRCCM
| #define SYSCTL_SRCCM MMIO32(SYSCTL_BASE + 0x574) |
CRC and Cryptographic Modules Software Reset.
Definition at line 209 of file systemcontrol.h.
◆ SYSCTL_SRDMA
| #define SYSCTL_SRDMA MMIO32(SYSCTL_BASE + 0x50C) |
Micro Direct Memory Access Software Reset.
Definition at line 181 of file systemcontrol.h.
◆ SYSCTL_SREEPROM
| #define SYSCTL_SREEPROM MMIO32(SYSCTL_BASE + 0x558) |
EEPROM Software Reset.
Definition at line 207 of file systemcontrol.h.
◆ SYSCTL_SREMAC
| #define SYSCTL_SREMAC MMIO32(SYSCTL_BASE + 0x59C) |
Ethernet MAC Software Reset.
Definition at line 215 of file systemcontrol.h.
◆ SYSCTL_SREPHY
| #define SYSCTL_SREPHY MMIO32(SYSCTL_BASE + 0x530) |
Ethernet PHY Software Reset.
Definition at line 195 of file systemcontrol.h.
◆ SYSCTL_SREPI
| #define SYSCTL_SREPI MMIO32(SYSCTL_BASE + 0x510) |
EPI Software Reset.
Definition at line 183 of file systemcontrol.h.
◆ SYSCTL_SRGPIO
| #define SYSCTL_SRGPIO MMIO32(SYSCTL_BASE + 0x508) |
General-Purpose Input/Output Software Reset.
Definition at line 179 of file systemcontrol.h.
◆ SYSCTL_SRHIB
| #define SYSCTL_SRHIB MMIO32(SYSCTL_BASE + 0x514) |
Hibernation Software Reset.
Definition at line 185 of file systemcontrol.h.
◆ SYSCTL_SRI2C
| #define SYSCTL_SRI2C MMIO32(SYSCTL_BASE + 0x520) |
Inter-Integrated Circuit Software Reset.
Definition at line 191 of file systemcontrol.h.
◆ SYSCTL_SRLCD
| #define SYSCTL_SRLCD MMIO32(SYSCTL_BASE + 0x590) |
LCD Controller Software Reset.
Definition at line 211 of file systemcontrol.h.
◆ SYSCTL_SROWIRE
| #define SYSCTL_SROWIRE MMIO32(SYSCTL_BASE + 0x598) |
1-Wire Software Reset
Definition at line 213 of file systemcontrol.h.
◆ SYSCTL_SRPWM
| #define SYSCTL_SRPWM MMIO32(SYSCTL_BASE + 0x540) |
Pulse Width Modulator Software Reset.
Definition at line 203 of file systemcontrol.h.
◆ SYSCTL_SRQEI
| #define SYSCTL_SRQEI MMIO32(SYSCTL_BASE + 0x544) |
Quadrature Encoder Interface Software Reset.
Definition at line 205 of file systemcontrol.h.
◆ SYSCTL_SRSSI
| #define SYSCTL_SRSSI MMIO32(SYSCTL_BASE + 0x51C) |
Synchronous Serial Interface Software Reset.
Definition at line 189 of file systemcontrol.h.
◆ SYSCTL_SRTIMER
| #define SYSCTL_SRTIMER MMIO32(SYSCTL_BASE + 0x504) |
16/32-Bit General-Purpose Timer Software Reset
Definition at line 177 of file systemcontrol.h.
◆ SYSCTL_SRUART
| #define SYSCTL_SRUART MMIO32(SYSCTL_BASE + 0x518) |
Universal Asynchronous Receiver/Transmitter Software Reset.
Definition at line 187 of file systemcontrol.h.
◆ SYSCTL_SRUSB
| #define SYSCTL_SRUSB MMIO32(SYSCTL_BASE + 0x528) |
Universal Serial Bus Software Reset.
Definition at line 193 of file systemcontrol.h.
◆ SYSCTL_SRWD
| #define SYSCTL_SRWD MMIO32(SYSCTL_BASE + 0x500) |
Watchdog Timer Software Reset.
Definition at line 175 of file systemcontrol.h.
◆ SYSCTL_SYSPROP
| #define SYSCTL_SYSPROP MMIO32(SYSCTL_BASE + 0x14C) |
System Properties.
Definition at line 77 of file systemcontrol.h.
◆ SYSCTL_UNIQUEID0
| #define SYSCTL_UNIQUEID0 MMIO32(SYSCTL_BASE + 0xF20) |
Unique ID 0.
Definition at line 433 of file systemcontrol.h.
◆ SYSCTL_UNIQUEID1
| #define SYSCTL_UNIQUEID1 MMIO32(SYSCTL_BASE + 0xF24) |
Unique ID 1.
Definition at line 435 of file systemcontrol.h.
◆ SYSCTL_UNIQUEID2
| #define SYSCTL_UNIQUEID2 MMIO32(SYSCTL_BASE + 0xF28) |
Unique ID 2.
Definition at line 437 of file systemcontrol.h.
◆ SYSCTL_UNIQUEID3
| #define SYSCTL_UNIQUEID3 MMIO32(SYSCTL_BASE + 0xF2C) |
Unique ID 3.
Definition at line 439 of file systemcontrol.h.
◆ SYSCTL_USBMPC
| #define SYSCTL_USBMPC MMIO32(SYSCTL_BASE + 0x284) |
USB Memory Power Control.
Definition at line 111 of file systemcontrol.h.
◆ SYSCTL_USBPDS
| #define SYSCTL_USBPDS MMIO32(SYSCTL_BASE + 0x280) |
USB Power Domain Status.
Definition at line 109 of file systemcontrol.h.
