libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
systemcontrol.h
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1/** @defgroup systemcontrol_defines System Control Defines
2 *
3 * @ingroup MSP432E4xx_defines
4 *
5 * @brief Defined Constants and Types for the MSP432E4xx System Control
6 *
7 * @version 1.0.0
8 *
9 * @date 22 July 2018
10 *
11 * LGPL License Terms @ref lgpl_license
12 */
13
14/*
15 * This file is part of the libopencm3 project.
16 *
17 * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
18 * Copyright (C) 2018 Dmitry Rezvanov <dmitry.rezvanov@yandex.ru>
19 *
20 * This library is free software: you can redistribute it and/or modify
21 * it under the terms of the GNU Lesser General Public License as published by
22 * the Free Software Foundation, either version 3 of the License, or
23 * (at your option) any later version.
24 *
25 * This library is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU Lesser General Public License for more details.
29 *
30 * You should have received a copy of the GNU Lesser General Public License
31 * along with this library. If not, see <http://www.gnu.org/licenses/>.
32 */
33
34#ifndef MSP432E4_SYSTEMCONTROL_H
35#define MSP432E4_SYSTEMCONTROL_H
36
37/**@{*/
38
39#include <libopencm3/cm3/common.h>
40#include <libopencm3/msp432/e4/memorymap.h>
41#include <stdbool.h>
42
43/** @defgroup sysctl_registers SYSCTL Registers
44 * @brief System Control Registers
45@{*/
46/** Device Identification 0 */
47#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000)
48/** Device Identification 1 */
49#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004)
50/** Power-Temp Brownout Control */
51#define SYSCTL_PTBOCTL MMIO32(SYSCTL_BASE + 0x038)
52/** Raw Interrupt Status */
53#define SYSCTL_RIS MMIO32(SYSCTL_BASE + 0x050)
54/** Interrupt Mask Control */
55#define SYSCTL_IMC MMIO32(SYSCTL_BASE + 0x054)
56/** RW1C Masked Interrupt Status and Clear */
57#define SYSCTL_MISC MMIO32(SYSCTL_BASE + 0x058)
58/** Reset Cause */
59#define SYSCTL_RESC MMIO32(SYSCTL_BASE + 0x05C)
60/** RW1C Power-Temperature Cause */
61#define SYSCTL_PWRTC MMIO32(SYSCTL_BASE + 0x060)
62/** NMI Cause Register */
63#define SYSCTL_NMIC MMIO32(SYSCTL_BASE + 0x064)
64/** Main Oscillator Control */
65#define SYSCTL_MOSCCTL MMIO32(SYSCTL_BASE + 0x07C)
66/** Run and Sleep Mode Configuration Register */
67#define SYSCTL_RSCLKCFG MMIO32(SYSCTL_BASE + 0x0B0)
68/** Memory Timing Parameter Register 0 for Main Flash and EEPROM */
69#define SYSCTL_MEMTIM0 MMIO32(SYSCTL_BASE + 0x0C0)
70/** Alternate Clock Configuration */
71#define SYSCTL_ALTCLKCFG MMIO32(SYSCTL_BASE + 0x138)
72/** Deep Sleep Clock Configuration Register */
73#define SYSCTL_DSCLKCFG MMIO32(SYSCTL_BASE + 0x144)
74/** Divisor and Source Clock Configuration */
75#define SYSCTL_DIVSCLK MMIO32(SYSCTL_BASE + 0x148)
76/** System Properties */
77#define SYSCTL_SYSPROP MMIO32(SYSCTL_BASE + 0x14C)
78/** Precision Internal Oscillator Calibration */
79#define SYSCTL_PIOSCCAL MMIO32(SYSCTL_BASE + 0x150)
80/** Precision Internal Oscillator Statistics */
81#define SYSCTL_PIOSCSTAT MMIO32(SYSCTL_BASE + 0x154)
82/** PLL Frequency 0 */
83#define SYSCTL_PLLFREQ0 MMIO32(SYSCTL_BASE + 0x160)
84/** PLL Frequency 1 */
85#define SYSCTL_PLLFREQ1 MMIO32(SYSCTL_BASE + 0x164)
86/** PLL Status */
87#define SYSCTL_PLLSTAT MMIO32(SYSCTL_BASE + 0x168)
88/** Sleep Power Configuration */
89#define SYSCTL_SLPPWRCFG MMIO32(SYSCTL_BASE + 0x188)
90/** Deep-Sleep Power Configuration */
91#define SYSCTL_DSLPPWRCFG MMIO32(SYSCTL_BASE + 0x18C)
92/** Non-Volatile Memory Information */
93#define SYSCTL_NVMSTAT MMIO32(SYSCTL_BASE + 0x1A0)
94/** LDO Sleep Power Control */
95#define SYSCTL_LDOSPCTL MMIO32(SYSCTL_BASE + 0x1B4)
96/** LDO Sleep Power Calibration */
97#define SYSCTL_LDOSPCAL MMIO32(SYSCTL_BASE + 0x1B8)
98/** LDO Deep-Sleep Power Control */
99#define SYSCTL_LDODPCTL MMIO32(SYSCTL_BASE + 0x1BC)
100/** LDO Deep-Sleep Power Calibration */
101#define SYSCTL_LDODPCAL MMIO32(SYSCTL_BASE + 0x1C0)
102/** Sleep / Deep-Sleep Power Mode Status */
103#define SYSCTL_SDPMST MMIO32(SYSCTL_BASE + 0x1CC)
104/** Reset Behavior Control Register */
105#define SYSCTL_RESBEHAVCTL MMIO32(SYSCTL_BASE + 0x1D8)
106/** Hardware System Service Request */
107#define SYSCTL_HSSR MMIO32(SYSCTL_BASE + 0x1F4)
108/** USB Power Domain Status */
109#define SYSCTL_USBPDS MMIO32(SYSCTL_BASE + 0x280)
110/** USB Memory Power Control */
111#define SYSCTL_USBMPC MMIO32(SYSCTL_BASE + 0x284)
112/** Ethernet MAC Power Domain Status */
113#define SYSCTL_EMACPDS MMIO32(SYSCTL_BASE + 0x288)
114/** Ethernet MAC Memory Power Control */
115#define SYSCTL_EMACMPC MMIO32(SYSCTL_BASE + 0x28C)
116/** LCD Power Domain Status */
117#define SYSCTL_LCDPDS MMIO32(SYSCTL_BASE + 0x290)
118/** LCD Memory Power Control */
119#define SYSCTL_LCDMPC MMIO32(SYSCTL_BASE + 0x294)
120/** CAN 0 Power Domain Status */
121#define SYSCTL_CAN0PDS MMIO32(SYSCTL_BASE + 0x298)
122/** CAN 0 Memory Power Control */
123#define SYSCTL_CAN0MPC MMIO32(SYSCTL_BASE + 0x29C)
124/** CAN 1 Power Domain Status */
125#define SYSCTL_CAN1PDS MMIO32(SYSCTL_BASE + 0x2A0)
126/** CAN 1 Memory Power Control */
127#define SYSCTL_CAN1MPC MMIO32(SYSCTL_BASE + 0x2A4)
128
129/** Watchdog Timer Peripheral Present */
130#define SYSCTL_PPWD MMIO32(SYSCTL_BASE + 0x300)
131/** 16/32-Bit General-Purpose Timer Peripheral Present */
132#define SYSCTL_PPTIMER MMIO32(SYSCTL_BASE + 0x304)
133/** General-Purpose Input/Output Peripheral Present */
134#define SYSCTL_PPGPIO MMIO32(SYSCTL_BASE + 0x308)
135/** Micro Direct Memory Access Peripheral Present */
136#define SYSCTL_PPDMA MMIO32(SYSCTL_BASE + 0x30C)
137/** EPI Peripheral Present */
138#define SYSCTL_PPEPI MMIO32(SYSCTL_BASE + 0x310)
139/** Hibernation Peripheral Present */
140#define SYSCTL_PPHIB MMIO32(SYSCTL_BASE + 0x314)
141/** Universal Asynchronous Receiver/Transmitter Peripheral Present */
142#define SYSCTL_PPUART MMIO32(SYSCTL_BASE + 0x318)
143/** Synchronous Serial Interface Peripheral Present */
144#define SYSCTL_PPSSI MMIO32(SYSCTL_BASE + 0x31C)
145/** Inter-Integrated Circuit Peripheral Present */
146#define SYSCTL_PPI2C MMIO32(SYSCTL_BASE + 0x320)
147/** Universal Serial Bus Peripheral Present */
148#define SYSCTL_PPUSB MMIO32(SYSCTL_BASE + 0x328)
149/** Ethernet PHY Peripheral Present */
150#define SYSCTL_PPEPHY MMIO32(SYSCTL_BASE + 0x330)
151/** Controller Area Network Peripheral Present */
152#define SYSCTL_PPCAN MMIO32(SYSCTL_BASE + 0x334)
153/** Analog-to-Digital Converter Peripheral Present */
154#define SYSCTL_PPADC MMIO32(SYSCTL_BASE + 0x338)
155/** Analog Comparator Peripheral Present */
156#define SYSCTL_PPACMP MMIO32(SYSCTL_BASE + 0x33C)
157/** Pulse Width Modulator Peripheral Present */
158#define SYSCTL_PPPWM MMIO32(SYSCTL_BASE + 0x340)
159/** Quadrature Encoder Interface Peripheral Present */
160#define SYSCTL_PPQEI MMIO32(SYSCTL_BASE + 0x344)
161/** EEPROM Peripheral Present */
162#define SYSCTL_PPEEPROM MMIO32(SYSCTL_BASE + 0x358)
163/** CRC and Cryptographic Modules Peripheral Present */
164#define SYSCTL_PPCCM MMIO32(SYSCTL_BASE + 0x374)
165/** LCD Peripheral Present */
166#define SYSCTL_PPLCD MMIO32(SYSCTL_BASE + 0x390)
167/** 1-Wire Peripheral Present */
168#define SYSCTL_PPOWIRE MMIO32(SYSCTL_BASE + 0x398)
169/** Ethernet MAC Peripheral Present */
170#define SYSCTL_PPEMAC MMIO32(SYSCTL_BASE + 0x39C)
171/** Power Regulator Bus Peripheral Present */
172#define SYSCTL_PPPRB MMIO32(SYSCTL_BASE + 0x3A0)
173
174/** Watchdog Timer Software Reset */
175#define SYSCTL_SRWD MMIO32(SYSCTL_BASE + 0x500)
176/** 16/32-Bit General-Purpose Timer Software Reset */
177#define SYSCTL_SRTIMER MMIO32(SYSCTL_BASE + 0x504)
178/** General-Purpose Input/Output Software Reset */
179#define SYSCTL_SRGPIO MMIO32(SYSCTL_BASE + 0x508)
180/** Micro Direct Memory Access Software Reset */
181#define SYSCTL_SRDMA MMIO32(SYSCTL_BASE + 0x50C)
182/** EPI Software Reset */
183#define SYSCTL_SREPI MMIO32(SYSCTL_BASE + 0x510)
184/** Hibernation Software Reset */
185#define SYSCTL_SRHIB MMIO32(SYSCTL_BASE + 0x514)
186/** Universal Asynchronous Receiver/Transmitter Software Reset */
187#define SYSCTL_SRUART MMIO32(SYSCTL_BASE + 0x518)
188/** Synchronous Serial Interface Software Reset */
189#define SYSCTL_SRSSI MMIO32(SYSCTL_BASE + 0x51C)
190/** Inter-Integrated Circuit Software Reset */
191#define SYSCTL_SRI2C MMIO32(SYSCTL_BASE + 0x520)
192/** Universal Serial Bus Software Reset */
193#define SYSCTL_SRUSB MMIO32(SYSCTL_BASE + 0x528)
194/** Ethernet PHY Software Reset */
195#define SYSCTL_SREPHY MMIO32(SYSCTL_BASE + 0x530)
196/** Controller Area Network Software Reset */
197#define SYSCTL_SRCAN MMIO32(SYSCTL_BASE + 0x534)
198/** Analog-to-Digital Converter Software Reset */
199#define SYSCTL_SRADC MMIO32(SYSCTL_BASE + 0x538)
200/** Analog Comparator Software Reset */
201#define SYSCTL_SRACMP MMIO32(SYSCTL_BASE + 0x53C)
202/** Pulse Width Modulator Software Reset */
203#define SYSCTL_SRPWM MMIO32(SYSCTL_BASE + 0x540)
204/** Quadrature Encoder Interface Software Reset */
205#define SYSCTL_SRQEI MMIO32(SYSCTL_BASE + 0x544)
206/** EEPROM Software Reset */
207#define SYSCTL_SREEPROM MMIO32(SYSCTL_BASE + 0x558)
208/** CRC and Cryptographic Modules Software Reset */
209#define SYSCTL_SRCCM MMIO32(SYSCTL_BASE + 0x574)
210/** LCD Controller Software Reset */
211#define SYSCTL_SRLCD MMIO32(SYSCTL_BASE + 0x590)
212/** 1-Wire Software Reset */
213#define SYSCTL_SROWIRE MMIO32(SYSCTL_BASE + 0x598)
214/** Ethernet MAC Software Reset */
215#define SYSCTL_SREMAC MMIO32(SYSCTL_BASE + 0x59C)
216
217/** Watchdog Timer Run Mode Clock Gating Control */
218#define SYSCTL_RCGCWD MMIO32(SYSCTL_BASE + 0x600)
219/** 16/32-BitGeneral-Purpose Timer RunMode Clock Gating Control */
220#define SYSCTL_RCGCTIMER MMIO32(SYSCTL_BASE + 0x604)
221/** General-Purpose Input/Output Run Mode Clock Gating Control */
222#define SYSCTL_RCGCGPIO MMIO32(SYSCTL_BASE + 0x608)
223/** Micro Direct Memory Access Run Mode Clock Gating Control */
224#define SYSCTL_RCGCDMA MMIO32(SYSCTL_BASE + 0x60C)
225/** EPI Run Mode Clock Gating Control */
226#define SYSCTL_RCGCEPI MMIO32(SYSCTL_BASE + 0x610)
227/** Hibernation Run Mode Clock Gating Control */
228#define SYSCTL_RCGCHIB MMIO32(SYSCTL_BASE + 0x614)
229/** Universal Asynchronous Receiver/Transmitter RunMode Clock Gating Control */
230#define SYSCTL_RCGCUART MMIO32(SYSCTL_BASE + 0x618)
231/** Synchronous Serial Interface Run Mode Clock Gating Control */
232#define SYSCTL_RCGCSSI MMIO32(SYSCTL_BASE + 0x61C)
233/** Inter-Integrated Circuit Run Mode Clock Gating Control */
234#define SYSCTL_RCGCI2C MMIO32(SYSCTL_BASE + 0x620)
235/** Universal Serial Bus Run Mode Clock Gating Control */
236#define SYSCTL_RCGCUSB MMIO32(SYSCTL_BASE + 0x628)
237/** Ethernet PHY Run Mode Clock Gating Control */
238#define SYSCTL_RCGCEPHY MMIO32(SYSCTL_BASE + 0x630)
239/** Controller Area Network RunMode Clock Gating Control */
240#define SYSCTL_RCGCCAN MMIO32(SYSCTL_BASE + 0x634)
241/** Analog-to-Digital Converter Run Mode Clock Gating Control */
242#define SYSCTL_RCGCADC MMIO32(SYSCTL_BASE + 0x638)
243/** Analog Comparator Run Mode Clock Gating Control */
244#define SYSCTL_RCGCACMP MMIO32(SYSCTL_BASE + 0x63C)
245/** Pulse Width Modulator Run Mode Clock Gating Control */
246#define SYSCTL_RCGCPWM MMIO32(SYSCTL_BASE + 0x640)
247/** Quadrature Encoder Interface Run Mode Clock Gating Control */
248#define SYSCTL_RCGCQEI MMIO32(SYSCTL_BASE + 0x644)
249/** EEPROM Run Mode Clock Gating Control */
250#define SYSCTL_RCGCEEPROM MMIO32(SYSCTL_BASE + 0x658)
251/** CRC and CryptographicModules RunMode ClockGating Control */
252#define SYSCTL_RCGCCCM MMIO32(SYSCTL_BASE + 0x674)
253/** LCD Controller Run Mode Clock Gating Control */
254#define SYSCTL_RCGCLCD MMIO32(SYSCTL_BASE + 0x690)
255/** 1-Wire Run Mode Clock Gating Control */
256#define SYSCTL_RCGCOWIRE MMIO32(SYSCTL_BASE + 0x698)
257/** Ethernet MAC Run Mode Clock Gating Control */
258#define SYSCTL_RCGCEMAC MMIO32(SYSCTL_BASE + 0x69C)
259
260/** Watchdog Timer Sleep Mode Clock Gating Control */
261#define SYSCTL_SCGCWD MMIO32(SYSCTL_BASE + 0x700)
262/** 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control */
263#define SYSCTL_SCGCTIMER MMIO32(SYSCTL_BASE + 0x704)
264/** General-Purpose Input/Output Sleep Mode Clock Gating Control */
265#define SYSCTL_SCGCGPIO MMIO32(SYSCTL_BASE + 0x708)
266/** Micro Direct Memory Access Sleep Mode Clock Gating Control */
267#define SYSCTL_SCGCDMA MMIO32(SYSCTL_BASE + 0x70C)
268/** EPI Sleep Mode Clock Gating Control */
269#define SYSCTL_SCGCEPI MMIO32(SYSCTL_BASE + 0x710)
270/** Hibernation Sleep Mode Clock Gating Control */
271#define SYSCTL_SCGCHIB MMIO32(SYSCTL_BASE + 0x714)
272/** Universal Asynchronous Receiver/Transmitter S Mode Clock Gating Control */
273#define SYSCTL_SCGCUART MMIO32(SYSCTL_BASE + 0x718)
274/** Synchronous Serial Interface Sleep Mode Clock Gating Control */
275#define SYSCTL_SCGCSSI MMIO32(SYSCTL_BASE + 0x71C)
276/** Inter-Integrated Circuit Sleep Mode Clock Gating Control */
277#define SYSCTL_SCGCI2C MMIO32(SYSCTL_BASE + 0x720)
278/** Universal Serial Bus Sleep Mode Clock Gating Control */
279#define SYSCTL_SCGCUSB MMIO32(SYSCTL_BASE + 0x728)
280/** Ethernet PHY Sleep Mode Clock Gating Control */
281#define SYSCTL_SCGCEPHY MMIO32(SYSCTL_BASE + 0x730)
282/** Controller Area Network Sleep Mode Clock Gating Control */
283#define SYSCTL_SCGCCAN MMIO32(SYSCTL_BASE + 0x734)
284/** Analog-to-Digital Converter Sleep Mode Clock Gating Control */
285#define SYSCTL_SCGCADC MMIO32(SYSCTL_BASE + 0x738)
286/** Analog Comparator Sleep Mode Clock Gating Control */
287#define SYSCTL_SCGCACMP MMIO32(SYSCTL_BASE + 0x73C)
288/** PulseWidthModulator Sleep Mode Clock Gating Control */
289#define SYSCTL_SCGCPWM MMIO32(SYSCTL_BASE + 0x740)
290/** Quadrature Encoder Interface Sleep Mode Clock Gating Control */
291#define SYSCTL_SCGCQEI MMIO32(SYSCTL_BASE + 0x744)
292/** EEPROM Sleep Mode Clock Gating Control */
293#define SYSCTL_SCGCEEPROM MMIO32(SYSCTL_BASE + 0x758)
294/** CRC and Cryptographic Modules Sleep Mode Clock Gating Control */
295#define SYSCTL_SCGCCCM MMIO32(SYSCTL_BASE + 0x774)
296/** LCD Controller Sleep Mode Clock Gating Control */
297#define SYSCTL_SCGCLCD MMIO32(SYSCTL_BASE + 0x790)
298/** 1-Wire Sleep Mode Clock Gating Control */
299#define SYSCTL_SCGCOWIRE MMIO32(SYSCTL_BASE + 0x798)
300/** Ethernet MAC Sleep Mode Clock Gating Control */
301#define SYSCTL_SCGCEMAC MMIO32(SYSCTL_BASE + 0x79C)
302
303/** Watchdog Timer Deep-SleepMode Clock Gating Control */
304#define SYSCTL_DCGCWD MMIO32(SYSCTL_BASE + 0x800)
305/** Clock 16/32-Bit General-Purpose Timer Deep-Sleep Mode Gating Control */
306#define SYSCTL_DCGCTIMER MMIO32(SYSCTL_BASE + 0x804)
307/** General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control */
308#define SYSCTL_DCGCGPIO MMIO32(SYSCTL_BASE + 0x808)
309/** Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control */
310#define SYSCTL_DCGCDMA MMIO32(SYSCTL_BASE + 0x80C)
311/** EPI Deep-Sleep Mode Clock Gating Control */
312#define SYSCTL_DCGCEPI MMIO32(SYSCTL_BASE + 0x810)
313/** Hibernation Deep-Sleep Mode Clock Gating Control */
314#define SYSCTL_DCGCHIB MMIO32(SYSCTL_BASE + 0x814)
315/** Universal Asynchronous Receiver/Transmitter D-S Mode Clock Gating Control*/
316#define SYSCTL_DCGCUART MMIO32(SYSCTL_BASE + 0x818)
317/** Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control */
318#define SYSCTL_DCGCSSI MMIO32(SYSCTL_BASE + 0x81C)
319/** Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control */
320#define SYSCTL_DCGCI2C MMIO32(SYSCTL_BASE + 0x820)
321/** Universal Serial Bus Deep-Sleep Mode Clock Gating Control */
322#define SYSCTL_DCGCUSB MMIO32(SYSCTL_BASE + 0x828)
323/** Ethernet PHY Deep-Sleep Mode Clock Gating Control */
324#define SYSCTL_DCGCEPHY MMIO32(SYSCTL_BASE + 0x830)
325/** Controller Area Network Deep-SleepMode Clock Gating Control */
326#define SYSCTL_DCGCCAN MMIO32(SYSCTL_BASE + 0x834)
327/** Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control */
328#define SYSCTL_DCGCADC MMIO32(SYSCTL_BASE + 0x838)
329/** Analog Comparator Deep-Sleep Mode Clock Gating Control */
330#define SYSCTL_DCGCACMP MMIO32(SYSCTL_BASE + 0x83C)
331/** Pulse Width Modulator Deep-Sleep Mode Clock Gating Control */
332#define SYSCTL_DCGCPWM MMIO32(SYSCTL_BASE + 0x840)
333/** Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control */
334#define SYSCTL_DCGCQEI MMIO32(SYSCTL_BASE + 0x844)
335/** EEPROM Deep-Sleep Mode Clock Gating Control */
336#define SYSCTL_DCGCEEPROM MMIO32(SYSCTL_BASE + 0x858)
337/** CRC and Cryptographic Modules Deep-Sleep Mode Clock Gating Control */
338#define SYSCTL_DCGCCCM MMIO32(SYSCTL_BASE + 0x874)
339/** LCD Controller Deep-Sleep Mode Clock Gating Control */
340#define SYSCTL_DCGCLCD MMIO32(SYSCTL_BASE + 0x890)
341/** 1-Wire Deep-Sleep Mode Clock Gating Control */
342#define SYSCTL_DCGCOWIRE MMIO32(SYSCTL_BASE + 0x898)
343/** Ethernet MAC Deep-Sleep Mode Clock Gating Control */
344#define SYSCTL_DCGCEMAC MMIO32(SYSCTL_BASE + 0x89C)
345
346/** Watchdog Timer Power Control */
347#define SYSCTL_PCWD MMIO32(SYSCTL_BASE + 0x900)
348/** 16/32-Bit General-Purpose Timer Power Control */
349#define SYSCTL_PCTIMER MMIO32(SYSCTL_BASE + 0x904)
350/** General-Purpose Input/Output Power Control */
351#define SYSCTL_PCGPIO MMIO32(SYSCTL_BASE + 0x908)
352/** Micro Direct Memory Access Power Control */
353#define SYSCTL_PCDMA MMIO32(SYSCTL_BASE + 0x90C)
354/** External Peripheral Interface Power Control */
355#define SYSCTL_PCEPI MMIO32(SYSCTL_BASE + 0x910)
356/** Hibernation Power Control */
357#define SYSCTL_PCHIB MMIO32(SYSCTL_BASE + 0x914)
358/** Universal Asynchronous Receiver/Transmitter Power Control */
359#define SYSCTL_PCUART MMIO32(SYSCTL_BASE + 0x918)
360/** Synchronous Serial Interface Power Control */
361#define SYSCTL_PCSSI MMIO32(SYSCTL_BASE + 0x91C)
362/** Inter-Integrated Circuit Power Control */
363#define SYSCTL_PCI2C MMIO32(SYSCTL_BASE + 0x920)
364/** Universal Serial Bus Power Control */
365#define SYSCTL_PCUSB MMIO32(SYSCTL_BASE + 0x928)
366/** Ethernet PHY Power Control */
367#define SYSCTL_PCEPHY MMIO32(SYSCTL_BASE + 0x930)
368/** Controller Area Network Power Control */
369#define SYSCTL_PCCAN MMIO32(SYSCTL_BASE + 0x934)
370/** Analog-to-Digital Converter Power Control */
371#define SYSCTL_PCADC MMIO32(SYSCTL_BASE + 0x938)
372/** Analog Comparator Power Control */
373#define SYSCTL_PCACMP MMIO32(SYSCTL_BASE + 0x93C)
374/** Pulse Width Modulator Power Control */
375#define SYSCTL_PCPWM MMIO32(SYSCTL_BASE + 0x940)
376/** Quadrature Encoder Interface Power Control */
377#define SYSCTL_PCQEI MMIO32(SYSCTL_BASE + 0x944)
378/** EEPROM Power Control */
379#define SYSCTL_PCEEPROM MMIO32(SYSCTL_BASE + 0x958)
380/** CRC and Cryptographic Modules Power Control */
381#define SYSCTL_PCCCM MMIO32(SYSCTL_BASE + 0x974)
382/** LCD Controller Power Control */
383#define SYSCTL_PCLCD MMIO32(SYSCTL_BASE + 0x990)
384/** 1-Wire Power Control */
385#define SYSCTL_PCOWIRE MMIO32(SYSCTL_BASE + 0x998)
386/** Ethernet MAC Power Control */
387#define SYSCTL_PCEMAC MMIO32(SYSCTL_BASE + 0x99C)
388
389/** Watchdog Timer Peripheral Ready */
390#define SYSCTL_PRWD MMIO32(SYSCTL_BASE + 0xA00)
391/** 16/32-Bit General-Purpose Timer Peripheral Ready */
392#define SYSCTL_PRTIMER MMIO32(SYSCTL_BASE + 0xA04)
393/** General-Purpose Input/Output Peripheral Ready */
394#define SYSCTL_PRGPIO MMIO32(SYSCTL_BASE + 0xA08)
395/** Micro Direct Memory Access Peripheral Ready */
396#define SYSCTL_PRDMA MMIO32(SYSCTL_BASE + 0xA0C)
397/** EPI Peripheral Ready */
398#define SYSCTL_PREPI MMIO32(SYSCTL_BASE + 0xA10)
399/** Hibernation Peripheral Ready */
400#define SYSCTL_PRHIB MMIO32(SYSCTL_BASE + 0xA14)
401/** Universal Asynchronous Receiver/Transmitter Peripheral Ready */
402#define SYSCTL_PRUART MMIO32(SYSCTL_BASE + 0xA18)
403/** Synchronous Serial Interface Peripheral Ready */
404#define SYSCTL_PRSSI MMIO32(SYSCTL_BASE + 0xA1C)
405/** Inter-Integrated Circuit Peripheral Ready */
406#define SYSCTL_PRI2C MMIO32(SYSCTL_BASE + 0xA20)
407/** Universal Serial Bus Peripheral Ready */
408#define SYSCTL_PRUSB MMIO32(SYSCTL_BASE + 0xA28)
409/** Ethernet PHY Peripheral Ready */
410#define SYSCTL_PREPHY MMIO32(SYSCTL_BASE + 0xA30)
411/** Controller Area Network Peripheral Ready */
412#define SYSCTL_PRCAN MMIO32(SYSCTL_BASE + 0xA34)
413/** Analog-to-Digital Converter Peripheral Ready */
414#define SYSCTL_PRADC MMIO32(SYSCTL_BASE + 0xA38)
415/** Analog Comparator Peripheral Ready */
416#define SYSCTL_PRACMP MMIO32(SYSCTL_BASE + 0xA3C)
417/** Pulse Width Modulator Peripheral Ready */
418#define SYSCTL_PRPWM MMIO32(SYSCTL_BASE + 0xA40)
419/** Quadrature Encoder Interface Peripheral Ready */
420#define SYSCTL_PRQEI MMIO32(SYSCTL_BASE + 0xA44)
421/** EEPROM Peripheral Ready */
422#define SYSCTL_PREEPROM MMIO32(SYSCTL_BASE + 0xA58)
423/** CRC and Cryptographic Modules Peripheral Ready */
424#define SYSCTL_PRCCM MMIO32(SYSCTL_BASE + 0xA74)
425/** LCD Controller Peripheral Ready */
426#define SYSCTL_PRLCD MMIO32(SYSCTL_BASE + 0xA90)
427/** 1-Wire Peripheral Ready */
428#define SYSCTL_PROWIRE MMIO32(SYSCTL_BASE + 0xA98)
429/** Ethernet MAC Peripheral Ready */
430#define SYSCTL_PREMAC MMIO32(SYSCTL_BASE + 0xA9C)
431
432/** Unique ID 0 */
433#define SYSCTL_UNIQUEID0 MMIO32(SYSCTL_BASE + 0xF20)
434/** Unique ID 1 */
435#define SYSCTL_UNIQUEID1 MMIO32(SYSCTL_BASE + 0xF24)
436/** Unique ID 2 */
437#define SYSCTL_UNIQUEID2 MMIO32(SYSCTL_BASE + 0xF28)
438/** Unique ID 3 */
439#define SYSCTL_UNIQUEID3 MMIO32(SYSCTL_BASE + 0xF2C)
440/**@}*/
441
442/** @defgroup sysctl_did0_values SYSCTL_DID0 Values
443 * @brief System Control Device Identification 0 Register Values
444@{*/
445/** DID0 Version Shift */
446#define SYSCTL_DID0_VER_SHIFT (28)
447/** DID0 Version Mask */
448#define SYSCTL_DID0_VER_MASK (0x7)
449/** Device Class Shift */
450#define SYSCTL_DID0_CLASS_SHIFT (16)
451/** Device Class Mask */
452#define SYSCTL_DID0_CLASS_MASK (0xFF)
453/** Major Revision Shift */
454#define SYSCTL_DID0_MAJOR_SHIFT (8)
455/** Major Revision Mask */
456#define SYSCTL_DID0_MAJOR_MASK (0xFF)
457/** Minor Revision Shift */
458#define SYSCTL_DID0_MINOR_SHIFT (0)
459/** Minor Revision Mask */
460#define SYSCTL_DID0_MINOR_MASK (0xFF)
461/**@}*/
462
463/** @defgroup sysctl_did1_values SYSCTL_DID1 Values
464 * @brief System Control Device Identification 1 Register Values
465@{*/
466/** DID1 Version Shift */
467#define SYSCTL_DID1_VER_SHIFT (28)
468/** DID1 Version Mask */
469#define SYSCTL_DID1_VER_MASK (0xF)
470/** Family Shift */
471#define SYSCTL_DID1_FAM_SHIFT (24)
472/** Family Mask */
473#define SYSCTL_DID1_FAM_MASK (0xF)
474/** Part Number Shift */
475#define SYSCTL_DID1_PARTNO_SHIFT (16)
476/** Part Number Mask */
477#define SYSCTL_DID1_PARTNO_MASK (0xFF)
478/** Package Pin Count Shift */
479#define SYSCTL_DID1_PINCOUNT_SHIFT (13)
480/** Package Pin Count Mask */
481#define SYSCTL_DID1_PINCOUNT_MASK (0x7)
482/** 128-pin package */
483#define SYSCTL_DID1_PINCOUNT_128P (0x6)
484/** 212-pin package */
485#define SYSCTL_DID1_PINCOUNT_212P (0x7)
486/** Temperature Range Shift */
487#define SYSCTL_DID1_TEMP_SHIFT (5)
488/** Temperature Range Mask */
489#define SYSCTL_DID1_TEMP_MASK (0x7)
490/** 0°C to +70°C */
491#define SYSCTL_DID1_TEMP_COMMERCIAL (0x0)
492/** -40°C to +85°C */
493#define SYSCTL_DID1_TEMP_INDUSTRIAL (0x1)
494/** -40°C to +105°C */
495#define SYSCTL_DID1_TEMP_EXTENDED (0x2)
496/** Package Type Shift */
497#define SYSCTL_DID1_PKG_SHIFT (3)
498/** Package Type Mask */
499#define SYSCTL_DID1_PKG_MASK (0x3)
500/** QFP package */
501#define SYSCTL_DID1_PKG_QFP (0x1)
502/** BGA package */
503#define SYSCTL_DID1_PKG_BGA (0x2)
504/** RoHS-compliance */
505#define SYSCTL_DID1_ROHS (1 << 2)
506/** Qualification Status Shift */
507#define SYSCTL_DID1_QUAL_SHIFT (0)
508/** Qualification Status Mask */
509#define SYSCTL_DID1_QUAL_MASK (0x3)
510/** Engineering Sample */
511#define SYSCTL_DID1_QUAL_SAMPLE (0x0)
512/** Pilot Production */
513#define SYSCTL_DID1_QUAL_PILOT (0x1)
514/** Fully Qualified */
515#define SYSCTL_DID1_QUAL_QUALIFIED (0x2)
516/**@}*/
517
518/** @defgroup sysctl_ptboctl_values SYSCTL_PTBOCTL0 Values
519 * @brief System Control Power-Temp Brownout Control Register Values
520@{*/
521/** VDDA Under BOR Event Action Shift */
522#define SYSCTL_PTBOCTL_VDDA_UBOR_SHIFT (8)
523/** VDDA Under BOR Event Action Mask */
524#define SYSCTL_PTBOCTL_VDDA_UBOR_MASK (0x3)
525/** VDDA Under BOR Event Action - No action */
526#define SYSCTL_PTBOCTL_VDDA_UBOR_NO (0x0)
527/** VDDA Under BOR Event Action - System Control Interrupt */
528#define SYSCTL_PTBOCTL_VDDA_UBOR_INT (0x1)
529/** VDDA Under BOR Event Action - Non-maskable interrupt */
530#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI (0x2)
531/** VDDA Under BOR Event Action - Reset */
532#define SYSCTL_PTBOCTL_VDDA_UBOR_RESET (0x3)
533/** VDD Under BOR Event Action Shift */
534#define SYSCTL_PTBOCTL_VDD_UBOR_SHIFT (1)
535/** VDD Under BOR Event Action Mask */
536#define SYSCTL_PTBOCTL_VDD_UBOR_MASK (0x3)
537/** VDD Under BOR Event Action - No action */
538#define SYSCTL_PTBOCTL_VDD_UBOR_NO (0x0)
539/** VDD Under BOR Event Action - System Control Interrupt */
540#define SYSCTL_PTBOCTL_VDD_UBOR_INT (0x1)
541/** VDD Under BOR Event Action - Non-maskable interrupt */
542#define SYSCTL_PTBOCTL_VDD_UBOR_NMI (0x2)
543/** VDD Under BOR Event Action - Reset */
544#define SYSCTL_PTBOCTL_VDD_UBOR_RESET (0x3)
545/**@}*/
546
547/** @defgroup sysctl_ric_values SYSCTL_RIS Values
548 * @brief System Control Raw Interrupt Status Register Values
549@{*/
550/** MOSC Power Up Raw Interrupt Status */
551#define SYSCTL_RIS_MOSCPUPRIS (1 << 8)
552/** PLL Lock Raw Interrupt Status */
553#define SYSCTL_RIS_PLLLRIS (1 << 6)
554/** Main Oscillator Failure Raw Interrupt Status */
555#define SYSCTL_RIS_MOFRIS (1 << 3)
556/** Brown-Out Reset Raw Interrupt Status */
557#define SYSCTL_RIS_BORRIS (1 << 1)
558/**@}*/
559
560/** @defgroup sysctl_imc_values SYSCTL_IMC Values
561 * @brief System Control Interrupt Mask Control Register Values
562@{*/
563/** MOSC Power Up Raw Interrupt Mask */
564#define SYSCTL_IMC_MOSCPUPIM (1 << 8)
565/** PLL Lock Raw Interrupt Mask */
566#define SYSCTL_IMC_PLLLIM (1 << 6)
567/** Main Oscillator Failure Raw Interrupt Mask */
568#define SYSCTL_IMC_MOFIM (1 << 3)
569/** Brown-Out Reset Raw Interrupt Mask */
570#define SYSCTL_IMC_BORIM (1 << 1)
571/**@}*/
572
573/** @defgroup sysctl_misc_values SYSCTL_MISC Values
574 * @brief System Control Masked Interrupt Status and Clear Register Values
575@{*/
576/** MOSC Power Up Raw Interrupt Status*/
577#define SYSCTL_MISC_MOSCPUPMIS (1 << 8)
578/** PLL Lock Raw Interrupt Status */
579#define SYSCTL_MISC_PLLLMIS (1 << 6)
580/** Main Oscillator Failure Raw Interrupt Status */
581#define SYSCTL_MISC_MOFMIS (1 << 3)
582/** Brown-Out Reset Raw Interrupt Status */
583#define SYSCTL_MISC_BORMIS (1 << 1)
584/**@}*/
585
586/** @defgroup sysctl_resc_values SYSCTL_RESC Values
587 * @brief System Control Reset Cause Register Values
588@{*/
589/** MOSC Failure Reset */
590#define SYSCTL_RESC_MOSCFAIL (1 << 16)
591/** HSSR Reset */
592#define SYSCTL_RESC_HSSR (1 << 12)
593/** Watchdog Timer 1 Reset */
594#define SYSCTL_RESC_WDT1 (1 << 5)
595/** Software Reset */
596#define SYSCTL_RESC_SW (1 << 4)
597/** Watchdog Timer 0 Reset */
598#define SYSCTL_RESC_WDT0 (1 << 3)
599/** Brown-Out Reset */
600#define SYSCTL_RESC_BOR (1 << 2)
601/** Power-On Reset */
602#define SYSCTL_RESC_POR (1 << 1)
603/** External Reset */
604#define SYSCTL_RESC_EXT (1 << 0)
605/**@}*/
606
607/** @defgroup sysctl_pwrtc_values SYSCTL_PWRTC Values
608 * @brief System Control Power-Temperature Cause Register Values
609@{*/
610/** VDDA Under BOR Status */
611#define SYSCTL_PWRTC_VDDA_UBOR (1 << 4)
612/** VDD Under BOR Status */
613#define SYSCTL_PWRTC_VDD_UBOR (1 << 0)
614/**@}*/
615
616/** @defgroup sysctl_nmic_values SYSCTL_NMIC Values
617 * @brief System Control NMI Cause Register Values
618@{*/
619/** MOSC Failure NMI */
620#define SYSCTL_NMIC_MOSCFAIL (1 << 16)
621/** Tamper Event NMI */
622#define SYSCTL_NMIC_TAMPER (1 << 9)
623/** WDT1 NMI */
624#define SYSCTL_NMIC_WDT1 (1 << 5)
625/** WDT0 NMI */
626#define SYSCTL_NMIC_WDT0 (1 << 3)
627/** Power/Brownout Event NMI */
628#define SYSCTL_NMIC_POWER (1 << 2)
629/** External Pin NMI */
630#define SYSCTL_NMIC_EXTERNAL (1 << 0)
631/**@}*/
632
633/** @defgroup sysctl_moscctl_values SYSCTL_MOSCCTL Values
634 * @brief System Control Main Oscillator Control Register Values
635@{*/
636/** Oscillator Range */
637#define SYSCTL_MOSCCTL_OSCRNG (1 << 4)
638/** Power Down */
639#define SYSCTL_MOSCCTL_PWRDN (1 << 3)
640/** No MOSC or Crystal Connected */
641#define SYSCTL_MOSCCTL_NOXTAL (1 << 2)
642/** MOSC Failure Action */
643#define SYSCTL_MOSCCTL_MOSCIM (1 << 1)
644/** Clock Validation for MOSC */
645#define SYSCTL_MOSCCTL_CVAL (1 << 0)
646/**@}*/
647
648/** @defgroup sysctl_rsclkcfg_values SYSCTL_RSCLKCFG Values
649 * @brief System Control Run and Sleep Mode Configuration Register Values
650@{*/
651/** Memory Timing Register Update */
652#define SYSCTL_RSCLKCFG_MEMTIMU (1 << 31)
653/** New PLLFREQ Accept */
654#define SYSCTL_RSCLKCFG_NEWFREQ (1 << 30)
655/** Auto Clock Gating */
656#define SYSCTL_RSCLKCFG_ACG (1 << 29)
657/** Use PLL */
658#define SYSCTL_RSCLKCFG_USEPLL (1 << 28)
659/** PLL Source Shift */
660#define SYSCTL_RSCLKCFG_PLLSRC_SHIFT (24)
661/** PLL Source Mask */
662#define SYSCTL_RSCLKCFG_PLLSRC_MASK (0xF)
663/** PLL Source - MOSC */
664#define SYSCTL_RSCLKCFG_PLLSRC_MOSC (0x3)
665/** Oscillator Source Shift */
666#define SYSCTL_RSCLKCFG_OSCSRC_SHIFT (20)
667/** Oscillator Source Mask */
668#define SYSCTL_RSCLKCFG_OSCSRC_MASK (0xF)
669/** Oscillator Source - LFIOSC */
670#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC (0x2)
671/** Oscillator Source - MOSC */
672#define SYSCTL_RSCLKCFG_OSCSRC_MOSC (0x3)
673/** Oscillator Source - RTCOSC */
674#define SYSCTL_RSCLKCFG_OSCSRC_RTCOSC (0x4)
675/** Oscillator System Clock Divisor Shift */
676#define SYSCTL_RSCLKCFG_OSYSDIV_SHIFT (10)
677/** Oscillator System Clock Divisor Mask */
678#define SYSCTL_RSCLKCFG_OSYSDIV_MASK (0x3FF)
679/** PLL System Clock Divisor Shift */
680#define SYSCTL_RSCLKCFG_PSYSDIV_SHIFT (0)
681/** PLL System Clock Divisor Mask */
682#define SYSCTL_RSCLKCFG_PSYSDIV_MASK (0x3FF)
683/**@}*/
684
685/** @defgroup sysctl_memtim0_values SYSCTL_MEMTIM0 Values
686 * @brief System Control Memory Timing Parameter Register 0 for Main Flash
687 * and EEPROM Register Values
688 *
689 * CPU Frequency Range (f) in MHZ |FBCHT and EBCHT|FBCE and EBCE| FWS and EWS|
690 * -------------------------------| ------------- | ----------- | ---------- |
691 * 16 | 0x0 (1/2) | 0x1 | 0x0 |
692 * 16 < f <= 40 | 0x2 (1.5) | 0x0 | 0x1 |
693 * 40 < f <= 60 | 0x3 (2) | 0x0 | 0x2 |
694 * 60 < f <= 80 | 0x4 (2.5) | 0x0 | 0x3 |
695 * 80 < f <= 100 | 0x5 (3) | 0x0 | 0x4 |
696 * 100 < f <= 120 | 0x6 (3.5) | 0x0 | 0x5 |
697 *
698@{*/
699/** EEPROM Clock High Time Shift */
700#define SYSCTL_MEMTIM0_EBCHT_SHIFT (22)
701/** EEPROM Clock High Time Mask */
702#define SYSCTL_MEMTIM0_EBCHT_MASK (0xF)
703/** EBCHT - 0.5 sys clock period */
704#define SYSCTL_MEMTIM0_EBCHT_0_POINT_5 (0x0)
705/** EBCHT - 1 sys clock period */
706#define SYSCTL_MEMTIM0_EBCHT_1 (0x1)
707/** EBCHT - 1.5 sys clock period */
708#define SYSCTL_MEMTIM0_EBCHT_1_POINT_5 (0x2)
709/** EBCHT - 2 sys clock period */
710#define SYSCTL_MEMTIM0_EBCHT_2 (0x3)
711/** EBCHT - 2.5 sys clock period */
712#define SYSCTL_MEMTIM0_EBCHT_2_POINT_5 (0x4)
713/** EBCHT - 3 sys clock period */
714#define SYSCTL_MEMTIM0_EBCHT_3 (0x5)
715/** EBCHT - 3.5 sys clock period */
716#define SYSCTL_MEMTIM0_EBCHT_3_POINT_5 (0x6)
717/** EBCHT - 4 sys clock period */
718#define SYSCTL_MEMTIM0_EBCHT_4 (0x7)
719/** EBCHT - 4.5 sys clock period */
720#define SYSCTL_MEMTIM0_EBCHT_4_POINT_5 (0x8)
721/** EEPROM Bank Clock Edge */
722#define SYSCTL_MEMTIM0_EBCE (1 << 21)
723/** EEPROM Wait States Shift */
724#define SYSCTL_MEMTIM0_EWS_SHIFT (16)
725/** EEPROM Wait States Mask */
726#define SYSCTL_MEMTIM0_EWS_MASK (0xF)
727/** EWS - 1 wait state */
728#define SYSCTL_MEMTIM0_EWS_1 (0x1)
729/** EWS - 2 wait state */
730#define SYSCTL_MEMTIM0_EWS_2 (0x2)
731/** EWS - 3 wait state */
732#define SYSCTL_MEMTIM0_EWS_3 (0x3)
733/** EWS - 4 wait state */
734#define SYSCTL_MEMTIM0_EWS_4 (0x4)
735/** EWS - 5 wait state */
736#define SYSCTL_MEMTIM0_EWS_5 (0x5)
737/** EWS - 6 wait state */
738#define SYSCTL_MEMTIM0_EWS_6 (0x6)
739/** EWS - 7 wait state */
740#define SYSCTL_MEMTIM0_EWS_7 (0x7)
741/** Flash Clock High Time Shift */
742#define SYSCTL_MEMTIM0_FBCHT_SHIFT (6)
743/** Flash Clock High Time Mask */
744#define SYSCTL_MEMTIM0_FBCHT_MASK (0xF)
745/** FBCHT - 0.5 sys clock period */
746#define SYSCTL_MEMTIM0_FBCHT_0_POINT_5 (0x0)
747/** FBCHT - 1 sys clock period */
748#define SYSCTL_MEMTIM0_FBCHT_1 (0x1)
749/** FBCHT - 1.5 sys clock period */
750#define SYSCTL_MEMTIM0_FBCHT_1_POINT_5 (0x2)
751/** FBCHT - 2 sys clock period */
752#define SYSCTL_MEMTIM0_FBCHT_2 (0x3)
753/** FBCHT - 2.5 sys clock period */
754#define SYSCTL_MEMTIM0_FBCHT_2_POINT_5 (0x4)
755/** FBCHT - 3 sys clock period */
756#define SYSCTL_MEMTIM0_FBCHT_3 (0x5)
757/** FBCHT - 3.5 sys clock period */
758#define SYSCTL_MEMTIM0_FBCHT_3_POINT_5 (0x6)
759/** FBCHT - 4 sys clock period */
760#define SYSCTL_MEMTIM0_FBCHT_4 (0x7)
761/** FBCHT - 4.5 sys clock period */
762#define SYSCTL_MEMTIM0_FBCHT_4_POINT_5 (0x8)
763/** Flash Bank Clock Edge */
764#define SYSCTL_MEMTIM0_FBCE (1 << 5)
765/** Flash Wait States Shift */
766#define SYSCTL_MEMTIM0_FWS_SHIFT (0)
767/** Flash Wait States Mask */
768#define SYSCTL_MEMTIM0_FWS_MASK (0xF)
769/** FWS - 1 wait state */
770#define SYSCTL_MEMTIM0_FWS_1 (0x1)
771/** FWS - 2 wait state */
772#define SYSCTL_MEMTIM0_FWS_2 (0x2)
773/** FWS - 3 wait state */
774#define SYSCTL_MEMTIM0_FWS_3 (0x3)
775/** FWS - 4 wait state */
776#define SYSCTL_MEMTIM0_FWS_4 (0x4)
777/** FWS - 5 wait state */
778#define SYSCTL_MEMTIM0_FWS_5 (0x5)
779/** FWS - 6 wait state */
780#define SYSCTL_MEMTIM0_FWS_6 (0x6)
781/** FWS - 7 wait state */
782#define SYSCTL_MEMTIM0_FWS_7 (0x7)
783/**@}*/
784
785/** @defgroup sysctl_altclkcfg_values SYSCTL_ALTCLKCFG Values
786 * @brief System Control Alternate Clock Configuration Register Values
787@{*/
788/** Alternate Clock Source Shift */
789#define SYSCTL_ALTCLKCFG_ALTCLK_SHIFT (0)
790/** Alternate Clock Source Mask */
791#define SYSCTL_ALTCLKCFG_ALTCLK_MASK (0xF)
792/** Alternate Clock Source - RTCOSC */
793#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC (0x3)
794/** Alternate Clock Source - LFIOSC */
795#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC (0x4)
796/**@}*/
797
798/** @defgroup sysctl_dsclkcfg_values SYSCTL_DSCLKCFG Values
799 * @brief System Control Deep Sleep Clock Configuration Register Values
800@{*/
801/** PIOSC Power Down */
802#define SYSCTL_DSCLKCFG_PIOSCPD (1 << 31)
803/** MOSC Disable Power Down */
804#define SYSCTL_DSCLKCFG_MOSCDPD (1 << 30)
805/** Deep Sleep Oscillator Source Shift */
806#define SYSCTL_DSCLKCFG_DSOSCSRC_SHIFT (20)
807/** Deep Sleep Oscillator Source Mask */
808#define SYSCTL_DSCLKCFG_DSOSCSRC_MASK (0xF)
809/** Deep Sleep Oscillator Source - LFIOSC */
810#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC (0x2)
811/** Deep Sleep Oscillator Source - MOSC */
812#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC (0x3)
813/** Deep Sleep Oscillator Source - RTCOSC */
814#define SYSCTL_DSCLKCFG_DSOSCSRC_RTCOSC (0x4)
815/** Deep Sleep Clock Divisor Shift */
816#define SYSCTL_DSCLKCFG_DSSYSDIV_SHIFT (0)
817/** Deep Sleep Clock Divisor Mask */
818#define SYSCTL_DSCLKCFG_DSSYSDIV_MASK (0x3FF)
819/**@}*/
820
821/** @defgroup sysctl_divsclk_values SYSCTL_DIVSCLK Values
822 * @brief System Control Divisor and Source Clock Configuration Register Values
823@{*/
824/** DIVSCLK Enable */
825#define SYSCTL_DIVSCLK_EN (1 << 31)
826/** Clock Source Shift */
827#define SYSCTL_DIVSCLK_SRC_SHIFT (16)
828/** Clock Source Mask */
829#define SYSCTL_DIVSCLK_SRC_MASK (0x3)
830/** Clock Source - PIOSCK */
831#define SYSCTL_DIVSCLK_SRC_PIOSC (0x1)
832/** Clock Source - MOSC */
833#define SYSCTL_DIVSCLK_SRC_MOSC (0x2)
834/** Divisor Value Shift */
835#define SYSCTL_DIVSCLK_DIV_SHIFT (0)
836/** Divisor Value Mask */
837#define SYSCTL_DIVSCLK_DIV_MASK (0xF)
838/** Divisor Value - 1 */
839#define SYSCTL_DIVSCLK_DIV_1 (0x0)
840/** Divisor Value - 2 */
841#define SYSCTL_DIVSCLK_DIV_2 (0x1)
842/**@}*/
843
844/** @defgroup sysctl_sysprop_values SYSCTL_SYSPROP Values
845 * @brief System Control System Properties Register Values
846@{*/
847/** LDO Sleep Mode Enable */
848#define SYSCTL_SYSPROP_LDOSME (1 << 17)
849/** Temp Sense Power Down Enable */
850#define SYSCTL_SYSPROP_TSPDE (1 << 16)
851/** PIOSC Power Down Present */
852#define SYSCTL_SYSPROP_PIOSCPDE (1 << 12)
853/** SRAM Sleep/Deep-Sleep Standby Mode Present */
854#define SYSCTL_SYSPROP_SRAMSM (1 << 11)
855/** SRAM Sleep/Deep-Sleep Low Power Mode Present */
856#define SYSCTL_SYSPROP_SRAMLPM (1 << 10)
857/** Flash Memory Sleep/Deep-Sleep Low Power Mode Present */
858#define SYSCTL_SYSPROP_FLASHLPM (1 << 8)
859/** Automatic LDO Sequence Control Present */
860#define SYSCTL_SYSPROP_LDOSEQ (1 << 5)
861/** FPU Present */
862#define SYSCTL_SYSPROP_FPU (1 << 0)
863/**@}*/
864
865/** @defgroup sysctl_piosccal_values SYSCTL_PIOSCCAL Values
866 * @brief System Control Precision Internal Oscillator
867 * Calibration Register Values
868@{*/
869/** Use User Trim Value */
870#define SYSCTL_PIOSCCAL_UTEN (1 << 31)
871/** Start Calibration */
872#define SYSCTL_PIOSCCAL_CAL (1 << 9)
873/** Update Trim */
874#define SYSCTL_PIOSCCAL_UPDATE (1 << 8)
875/** User Trim Value Shift */
876#define SYSCTL_PIOSCCAL_UT_SHIFT (0)
877/** User Trim Value Mask */
878#define SYSCTL_PIOSCCAL_UT_MASK (0x7F)
879/**@}*/
880
881/** @defgroup sysctl_pioscstat_values SYSCTL_PIOSCSTAT Values
882 * @brief System Control Precision Internal Oscillator
883 * Statistics Register Values
884@{*/
885/** Default Trim Value Shift */
886#define SYSCTL_PIOSCSTAT_DT_SHIFT (16)
887/** Default Trim Value Mask */
888#define SYSCTL_PIOSCSTAT_DT_MASK (0x7F)
889/** Calibration Result Shift */
890#define SYSCTL_PIOSCSTAT_RESULT_SHIFT (8)
891/** Calibration Result Mask */
892#define SYSCTL_PIOSCSTAT_RESULT_MASK (0x3)
893/** Calibration Not Attempted */
894#define SYSCTL_PIOSCSTAT_RESULT_NOT_ATTEMPT (0x0)
895/** Calibration Completed */
896#define SYSCTL_PIOSCSTAT_RESULT_COMPLETE (0x1)
897/** Calibration Failed */
898#define SYSCTL_PIOSCSTAT_RESULT_FAIL (0x2)
899/** Calibration Value Shift */
900#define SYSCTL_PIOSCSTAT_CT_SHIFT (0)
901/** Calibration Value Mask */
902#define SYSCTL_PIOSCSTAT_CT_MASK (0x7F)
903/**@}*/
904
905/** @defgroup sysctl_pllfreq0_values SYSCTL_PLLFREQ0 Values
906 * @brief System Control PLL Frequency 0 Register Values
907@{*/
908/** PLL Power */
909#define SYSCTL_PLLFREQ0_PLLPWR (1 << 23)
910/** PLL M Fractional Value Shift */
911#define SYSCTL_PLLFREQ0_MFRAC_SHIFT (10)
912/** PLL M Fractional Value Mask */
913#define SYSCTL_PLLFREQ0_MFRAC_MASK (0x3FF)
914/** PLL M Integer Value Shift */
915#define SYSCTL_PLLFREQ0_MINT_SHIFT (0)
916/** PLL M Integer Value Mask */
917#define SYSCTL_PLLFREQ0_MINT_MASK (0x3FF)
918/**@}*/
919
920/** @defgroup sysctl_pllfreq1_values SYSCTL_PLLFREQ1 Values
921 * @brief System Control PLL Frequency 1 Register Values
922@{*/
923/** PLL Q Value Shift */
924#define SYSCTL_PLLFREQ1_Q_SHIFT (8)
925/** PLL Q Value Mask */
926#define SYSCTL_PLLFREQ1_Q_MASK (0x1F)
927/** PLL N Value Shift */
928#define SYSCTL_PLLFREQ1_N_SHIFT (0)
929/** PLL N Value Mask */
930#define SYSCTL_PLLFREQ1_N_MASK (0x1F)
931/**@}*/
932
933/** @defgroup sysctl_pllstat_values SYSCTL_PLLSTAT Values
934 * @brief System Control PLL Status Register Values
935@{*/
936/** PLL Lock */
937#define SYSCTL_PLLSTAT_LOCK (1 << 0)
938/**@}*/
939
940/** @defgroup sysctl_slppwrcfg_values SYSCTL_SLPPWRCFG Values
941 * @brief System Control Sleep Power Configuration Register Values
942@{*/
943/** Flash Power Modes Shift */
944#define SYSCTL_SLPPWRCFG_FLASHPM_SHIFT (4)
945/** Flash Power Modes Mask */
946#define SYSCTL_SLPPWRCFG_FLASHPM_MASK (0x3)
947/** Flash Power Mode - Active mode */
948#define SYSCTL_SLPPWRCFG_FLASHPM_ACTIVE (0x0)
949/** Flash Power Mode - Low-Power Mode */
950#define SYSCTL_SLPPWRCFG_FLASHPM_LP (0x2)
951/** SRAM Power Modes Shift */
952#define SYSCTL_SLPPWRCFG_SRAMPM_SHIFT (0)
953/** SRAM Power Modes Mask */
954#define SYSCTL_SLPPWRCFG_SRAMPM_MASK (0x3)
955/** SRAM Power Mode - Active mode */
956#define SYSCTL_SLPPWRCFG_SRAMPM_ACTIVE (0x0)
957/** SRAM Power Mode - Standby mode */
958#define SYSCTL_SLPPWRCFG_SRAMPM_STANDBY (0x1)
959/** SRAM Power Mode - Low-Power Mode */
960#define SYSCTL_SLPPWRCFG_SRAMPM_LP (0x3)
961/**@}*/
962
963/** @defgroup sysctl_dslppwrcfg_values SYSCTL_DSLPPWRCFG Values
964 * @brief System Control Deep-Sleep Power Configuration Register Values
965@{*/
966/** LDO Sleep Mode */
967#define SYSCTL_DSLPPWRCFG_LDOSM (1 << 9)
968/** Temp Sense Power Down */
969#define SYSCTL_DSLPPWRCFG_TSPD (1 << 8)
970/** Flash Power Modes Shift */
971#define SYSCTL_DSLPPWRCFG_FLASHPM_SHIFT (4)
972/** Flash Power Modes Mask */
973#define SYSCTL_DSLPPWRCFG_FLASHPM_MASK (0x3)
974/** Flash Power Mode - Active mode */
975#define SYSCTL_DSLPPWRCFG_FLASHPM_ACTIVE (0x0)
976/** Flash Power Mode - Low-Power Mode */
977#define SYSCTL_DSLPPWRCFG_FLASHPM_LP (0x2)
978/** SRAM Power Modes Shift */
979#define SYSCTL_DSLPPWRCFG_SRAMPM_SHIFT (0)
980/** SRAM Power Modes Mask */
981#define SYSCTL_DSLPPWRCFG_SRAMPM_MASK (0x3)
982/** SRAM Power Mode - Active mode */
983#define SYSCTL_DSLPPWRCFG_SRAMPM_ACTIVE (0x0)
984/** SRAM Power Mode - Standby mode */
985#define SYSCTL_DSLPPWRCFG_SRAMPM_STANDBY (0x1)
986/** SRAM Power Mode - Low-Power Mode */
987#define SYSCTL_DSLPPWRCFG_SRAMPM_LP (0x3)
988/**@}*/
989
990/** @defgroup sysctl_nvmstat_values SYSCTL_NVMSTAT Values
991 * @brief System Control Non-Volatile Memory Information Register Values
992@{*/
993/** 32 Word Flash Write Buffer Available */
994#define SYSCTL_NVMSTAT_FWB (1 << 0)
995/**@}*/
996
997/** @defgroup sysctl_ldospctl_values SYSCTL_LDOSPCTL Values
998 * @brief System Control LDO Sleep Power Control Register Values
999@{*/
1000/** Voltage Adjust Enable */
1001#define SYSCTL_LDOSPCTL_VADJEN (1 << 31)
1002/** LDO Out Voltage Shift */
1003#define SYSCTL_LDOSPCTL_VLDO_SHIFT (0)
1004/** LDO Out Voltage Mask */
1005#define SYSCTL_LDOSPCTL_VLDO_MASK (0xFF)
1006/** LDO Out Voltage - 0.90V */
1007#define SYSCTL_LDOSPCTL_VLDO_0_POINT_90 (0x12)
1008/** LDO Out Voltage - 0.95V */
1009#define SYSCTL_LDOSPCTL_VLDO_0_POINT_95 (0x13)
1010/** LDO Out Voltage - 1.00V */
1011#define SYSCTL_LDOSPCTL_VLDO_1_POINT_00 (0x14)
1012/** LDO Out Voltage - 1.05V */
1013#define SYSCTL_LDOSPCTL_VLDO_1_POINT_05 (0x15)
1014/** LDO Out Voltage - 1.10V */
1015#define SYSCTL_LDOSPCTL_VLDO_1_POINT_10 (0x16)
1016/** LDO Out Voltage - 1.15V */
1017#define SYSCTL_LDOSPCTL_VLDO_1_POINT_15 (0x17)
1018/** LDO Out Voltage - 1.20V */
1019#define SYSCTL_LDOSPCTL_VLDO_1_POINT_20 (0x18)
1020/**@}*/
1021
1022/** @defgroup sysctl_ldospcal_values SYSCTL_LDOSPCAL Values
1023 * @brief System Control LDO Sleep Power Calibration Register Values
1024@{*/
1025/** Sleep With PLL Shift */
1026#define SYSCTL_LDOSPCAL_WITHPLL_SHIFT (8)
1027/** Sleep With PLL Mask */
1028#define SYSCTL_LDOSPCAL_WITHPLL_MASK (0xFF)
1029/** Sleep Without PLL Shift */
1030#define SYSCTL_LDOSPCAL_NOPLL_SHIFT (0)
1031/** Sleep Without PLL Mask */
1032#define SYSCTL_LDOSPCAL_NOPLL_MASK (0xFF)
1033/**@}*/
1034
1035/** @defgroup sysctl_ldodpctl_values SYSCTL_LDODPCTL Values
1036 * @brief System Control LDO Deep-Sleep Power Control Register Values
1037@{*/
1038/** Voltage Adjust Enable */
1039#define SYSCTL_LDODPCTL_VADJEN (1 << 31)
1040/** LDO Out Voltage Shift */
1041#define SYSCTL_LDODPCTL_VLDO_SHIFT (0)
1042/** LDO Out Voltage Mask */
1043#define SYSCTL_LDODPCTL_VLDO_MASK (0xFF)
1044/** LDO Out Voltage - 0.90V */
1045#define SYSCTL_LDODPCTL_VLDO_0_POINT_90 (0x12)
1046/** LDO Out Voltage - 0.95V */
1047#define SYSCTL_LDODPCTL_VLDO_0_POINT_95 (0x13)
1048/** LDO Out Voltage - 1.00V */
1049#define SYSCTL_LDODPCTL_VLDO_1_POINT_00 (0x14)
1050/** LDO Out Voltage - 1.05V */
1051#define SYSCTL_LDODPCTL_VLDO_1_POINT_05 (0x15)
1052/** LDO Out Voltage - 1.10V */
1053#define SYSCTL_LDODPCTL_VLDO_1_POINT_10 (0x16)
1054/** LDO Out Voltage - 1.15V */
1055#define SYSCTL_LDODPCTL_VLDO_1_POINT_15 (0x17)
1056/** LDO Out Voltage - 1.20V */
1057#define SYSCTL_LDODPCTL_VLDO_1_POINT_20 (0x18)
1058/**@}*/
1059
1060/** @defgroup sysctl_ldodpcal_values SYSCTL_LDODPCAL Values
1061 * @brief System Control LDO Deep-Sleep Power Calibration Register Values
1062@{*/
1063/** Deep-Sleep Without PLL Shift */
1064#define SYSCTL_LDODPCAL_NOPLL_SHIFT (8)
1065/** Deep-Sleep Without PLL Mask */
1066#define SYSCTL_LDODPCAL_NOPLL_MASK (0xFF)
1067/** Deep-Sleep With IOSC Shift */
1068#define SYSCTL_LDODPCAL_30KHZ_SHIFT (0)
1069/** Deep-Sleep With IOSC Mask */
1070#define SYSCTL_LDODPCAL_30KHZ_MASK (0xFF)
1071/**@}*/
1072
1073/** @defgroup sysctl_sdpmst_values SYSCTL_SDPMST Values
1074 * @brief System Control Sleep/Deep-Sleep Power Mode Status Register Values
1075@{*/
1076/** LDO Update Active */
1077#define SYSCTL_SDPMST_LDOUA (1 << 19)
1078/** Flash Memory in Low Power State */
1079#define SYSCTL_SDPMST_FLASHLP (1 << 18)
1080/** Sleep or Deep-Sleep Mode */
1081#define SYSCTL_SDPMST_LOWPWR (1 << 17)
1082/** Sleep or Deep-Sleep Power Request Active */
1083#define SYSCTL_SDPMST_PRACT (1 << 16)
1084/** PIOSC Power Down Request Warning */
1085#define SYSCTL_SDPMST_PPDW (1 << 7)
1086/** VLDO Value Above Max Error */
1087#define SYSCTL_SDPMST_LMAXERR (1 << 6)
1088/** VLDO Value Below Minimum Error in Sleep Mode */
1089#define SYSCTL_SDPMST_LSMINERR (1 << 4)
1090/** VLDO Value Below Minimum Error in Deep-Sleep Mode */
1091#define SYSCTL_SDPMST_LDMINERR (1 << 3)
1092/** PIOSC Power Down Request Error */
1093#define SYSCTL_SDPMST_PPDERR (1 << 2)
1094/** Flash Memory Power Down Request Error */
1095#define SYSCTL_SDPMST_FPDERR (1 << 1)
1096/** SRAM Power Down Request Error */
1097#define SYSCTL_SDPMST_SPDERR (1 << 0)
1098/**@}*/
1099
1100/** @defgroup sysctl_resbehavctl_values SYSCTL_RESBEHAVCTL Values
1101 * @brief System Control Reset Behavior Control Register Values
1102@{*/
1103/** Reset Operation - System Reset */
1104#define SYSCTL_RESBEHAVCTL_SYSRES (0x2)
1105/** Reset Operation - Power-On-Reset */
1106#define SYSCTL_RESBEHAVCTL_POR (0x3)
1107/** Watchdog 1 Reset Operation Shift */
1108#define SYSCTL_RESBEHAVCTL_WDOG1_SHIFT (6)
1109/** Watchdog 1 Reset Operation Mask */
1110#define SYSCTL_RESBEHAVCTL_WDOG1_MASK (0x3)
1111/** Watchdog 0 Reset Operation Shift */
1112#define SYSCTL_RESBEHAVCTL_WDOG0_SHIFT (4)
1113/** Watchdog 0 Reset Operation Mask */
1114#define SYSCTL_RESBEHAVCTL_WDOG0_MASK (0x3)
1115/** BOR Reset Operation Shift */
1116#define SYSCTL_RESBEHAVCTL_BOR_SHIFT (2)
1117/** BOR Reset Operation Shift */
1118#define SYSCTL_RESBEHAVCTL_BOR_MASK (0x3)
1119/** EXT Reset Operation Shift */
1120#define SYSCTL_RESBEHAVCTL_EXTRES_SHIFT (2)
1121/** EXT Reset Operation Mask */
1122#define SYSCTL_RESBEHAVCTL_EXTRES_MASK (0x3)
1123/**@}*/
1124
1125/** @defgroup sysctl_hssr_values SYSCTL_HSSR Values
1126 * @brief System Control Hardware System Service Request Register Values
1127@{*/
1128/** Write Key Shift */
1129#define SYSCTL_HSSR_KEY_SHIFT (24)
1130/** Write Key Mask */
1131#define SYSCTL_HSSR_KEY_MASK (0xFF)
1132/** Key Value for initiate request */
1133#define SYSCTL_HSSR_KEY_VALUE (0xCA)
1134/** Command Descriptor Pointer Shift */
1135#define SYSCTL_HSSR_CDOFF_SHIFT (0)
1136/** Command Descriptor Pointer Mask */
1137#define SYSCTL_HSSR_CDOFF_MASK (0xFFFFFF)
1138/** Command Descriptor - No Request */
1139#define SYSCTL_HSSR_CDOFF_NO_REQUEST (0x000000)
1140/** Command Descriptor - Error Or Incomplete Request */
1141#define SYSCTL_HSSR_CDOFF_ERROR (0xFFFFFF)
1142/**@}*/
1143
1144/** @defgroup sysctl_usbpds_values SYSCTL_USBPDS Values
1145 * @brief System Control USB Power Domain Status Register Values
1146@{*/
1147/** Memory Array Power Status Shift */
1148#define SYSCTL_USBPDS_MEMSTAT_SHIFT (2)
1149/** Memory Array Power Status Mask */
1150#define SYSCTL_USBPDS_MEMSTAT_MASK (0x3)
1151/** Memory Array Power Status - Off */
1152#define SYSCTL_USBPDS_MEMSTAT_ARR_OFF (0x0)
1153/** Memory Array Power Status - SRAM Retention */
1154#define SYSCTL_USBPDS_MEMSTAT_SRAM_RET (0x1)
1155/** Memory Array Power Status - On */
1156#define SYSCTL_USBPDS_MEMSTAT_ARR_ON (0x3)
1157/** Power Domain Status Shift */
1158#define SYSCTL_USBPDS_PWRSTAT_SHIFT (0)
1159/** Power Domain Status Mask */
1160#define SYSCTL_USBPDS_PWRSTAT_MASK (0x3)
1161/** Power Domain Status - Off */
1162#define SYSCTL_USBPDS_PWRSTAT_OFF (0x0)
1163/** Power Domain Status - On */
1164#define SYSCTL_USBPDS_PWRSTAT_ON (0x3)
1165/**@}*/
1166
1167/** @defgroup sysctl_usbmpc_values SYSCTL_USBMPC Values
1168 * @brief System Control USB Memory Power Control Register Values
1169@{*/
1170/** Memory Array Power Control Shift */
1171#define SYSCTL_USBMPC_PWRCTL_SHIFT (0)
1172/** Memory Array Power Control Mask */
1173#define SYSCTL_USBMPC_PWRCTL_MASK (0x3)
1174/** Memory Array Power Control - Off */
1175#define SYSCTL_USBMPC_PWRCTL_ARR_OFF (0x0)
1176/** Memory Array Power Control - SRAM Retention */
1177#define SYSCTL_USBMPC_PWRCTL_SRAM_RET (0x1)
1178/** Memory Array Power Control - On */
1179#define SYSCTL_USBMPC_PWRCTL_ARR_ON (0x3)
1180/**@}*/
1181
1182/** @defgroup sysctl_emacpds_values SYSCTL_EMACPDS Values
1183 * @brief System Control Ethernet MAC Power Domain Status Register Values
1184@{*/
1185/** Memory Array Power Status Shift */
1186#define SYSCTL_EMACPDS_MEMSTAT_SHIFT (2)
1187/** Memory Array Power Status Mask */
1188#define SYSCTL_EMACPDS_MEMSTAT_MASK (0x3)
1189/** Memory Array Power Status - Off */
1190#define SYSCTL_EMACPDS_MEMSTAT_ARR_OFF (0x0)
1191/** Memory Array Power Status - On */
1192#define SYSCTL_EMACPDS_MEMSTAT_ARR_ON (0x3)
1193/** Power Domain Status Shift*/
1194#define SYSCTL_EMACPDS_PWRSTAT_SHIFT (0)
1195/** Power Domain Status Mask */
1196#define SYSCTL_EMACPDS_PWRSTAT_MASK (0x3)
1197/** Power Domain Status - Off */
1198#define SYSCTL_EMACPDS_PWRSTAT_OFF (0x0)
1199/** Power Domain Status - On */
1200#define SYSCTL_EMACPDS_PWRSTAT_ON (0x3)
1201/**@}*/
1202
1203/** @defgroup sysctl_emacmpc_values SYSCTL_EMACMPC Values
1204 * @brief System Control Ethernet MAC Memory Power Control Register Values
1205@{*/
1206/** Memory Array Power Control Shift */
1207#define SYSCTL_EMACMPC_PWRCTL_SHIFT (0)
1208/** Memory Array Power Control Mask */
1209#define SYSCTL_EMACMPC_PWRCTL_MASK (0x3)
1210/** Memory Array Power Control - Off */
1211#define SYSCTL_EMACMPC_PWRCTL_ARR_OFF (0x0)
1212/** Memory Array Power Control - On */
1213#define SYSCTL_EMACMPC_PWRCTL_ARR_ON (0x3)
1214/**@}*/
1215
1216/** @defgroup sysctl_lcdpds_values SYSCTL_LCDPDS Values
1217 * @brief System Control LCD Power Domain Status Register Values
1218@{*/
1219/** Memory Array Power Status Shift */
1220#define SYSCTL_LCDPDS_MEMSTAT_SHIFT (2)
1221/** Memory Array Power Status Mask */
1222#define SYSCTL_LCDPDS_MEMSTAT_MASK (0x3)
1223/** Memory Array Power Status - Off */
1224#define SYSCTL_LCDPDS_MEMSTAT_ARR_OFF (0x0)
1225/** Memory Array Power Status - On */
1226#define SYSCTL_LCDPDS_MEMSTAT_ARR_ON (0x3)
1227/** Power Domain Status Shift*/
1228#define SYSCTL_LCDPDS_PWRSTAT_SHIFT (0)
1229/** Power Domain Status Mask */
1230#define SYSCTL_LCDPDS_PWRSTAT_MASK (0x3)
1231/** Power Domain Status - Off */
1232#define SYSCTL_LCDPDS_PWRSTAT_OFF (0x0)
1233/** Power Domain Status - On */
1234#define SYSCTL_LCDPDS_PWRSTAT_ON (0x3)
1235/**@}*/
1236
1237/** @defgroup sysctl_lcdmpc_values SYSCTL_LCDMPC Values
1238 * @brief System Control LCD Memory Power Control Register Values
1239@{*/
1240/** Memory Array Power Control Shift */
1241#define SYSCTL_LCDMPC_PWRCTL_SHIFT (0)
1242/** Memory Array Power Control Mask */
1243#define SYSCTL_LCDMPC_PWRCTL_MASK (0x3)
1244/** Memory Array Power Control - Off */
1245#define SYSCTL_LCDMPC_PWRCTL_ARR_OFF (0x0)
1246/** Memory Array Power Control - On */
1247#define SYSCTL_LCDMPC_PWRCTL_ARR_ON (0x3)
1248/**@}*/
1249
1250/** @defgroup sysctl_can0pds_values SYSCTL_CAN0PDS Values
1251 * @brief System Control CAN 0 Power Domain Status Register Values
1252@{*/
1253/** Memory Array Power Status Shift */
1254#define SYSCTL_CAN0PDS_MEMSTAT_SHIFT (2)
1255/** Memory Array Power Status Mask */
1256#define SYSCTL_CAN0PDS_MEMSTAT_MASK (0x3)
1257/** Memory Array Power Status - Off */
1258#define SYSCTL_CAN0PDS_MEMSTAT_ARR_OFF (0x0)
1259/** Memory Array Power Status - On */
1260#define SYSCTL_CAN0PDS_MEMSTAT_ARR_ON (0x3)
1261/** Power Domain Status Shift*/
1262#define SYSCTL_CAN0PDS_PWRSTAT_SHIFT (0)
1263/** Power Domain Status Mask */
1264#define SYSCTL_CAN0PDS_PWRSTAT_MASK (0x3)
1265/** Power Domain Status - Off */
1266#define SYSCTL_CAN0PDS_PWRSTAT_OFF (0x0)
1267/** Power Domain Status - On */
1268#define SYSCTL_CAN0PDS_PWRSTAT_ON (0x3)
1269/**@}*/
1270
1271/** @defgroup sysctl_can0mpc_values SYSCTL_CAN0MPC Values
1272 * @brief System Control CAN 0 Memory Power Control Register Values
1273@{*/
1274/** Memory Array Power Control Shift */
1275#define SYSCTL_CAN0MPC_PWRCTL_SHIFT (0)
1276/** Memory Array Power Control Mask */
1277#define SYSCTL_CAN0MPC_PWRCTL_MASK (0x3)
1278/** Memory Array Power Control - Off */
1279#define SYSCTL_CAN0MPC_PWRCTL_ARR_OFF (0x0)
1280/** Memory Array Power Control - On */
1281#define SYSCTL_CAN0MPC_PWRCTL_ARR_ON (0x3)
1282/**@}*/
1283
1284/** @defgroup sysctl_can1pds_values SYSCTL_CAN1PDS Values
1285 * @brief System Control CAN 1 Power Domain Status Register Values
1286@{*/
1287/** Memory Array Power Status Shift */
1288#define SYSCTL_CAN1PDS_MEMSTAT_SHIFT (2)
1289/** Memory Array Power Status Mask */
1290#define SYSCTL_CAN1PDS_MEMSTAT_MASK (0x3)
1291/** Memory Array Power Status - Off */
1292#define SYSCTL_CAN1PDS_MEMSTAT_ARR_OFF (0x0)
1293/** Memory Array Power Status - On */
1294#define SYSCTL_CAN1PDS_MEMSTAT_ARR_ON (0x3)
1295/** Power Domain Status Shift*/
1296#define SYSCTL_CAN1PDS_PWRSTAT_SHIFT (0)
1297/** Power Domain Status Mask */
1298#define SYSCTL_CAN1PDS_PWRSTAT_MASK (0x3)
1299/** Power Domain Status - Off */
1300#define SYSCTL_CAN1PDS_PWRSTAT_OFF (0x0)
1301/** Power Domain Status - On */
1302#define SYSCTL_CAN1PDS_PWRSTAT_ON (0x3)
1303/**@}*/
1304
1305/** @defgroup sysctl_can1mpc_values SYSCTL_CAN1MPC Values
1306 * @brief System Control CAN 1 Memory Power Control Register Values
1307@{*/
1308/** Memory Array Power Control Shift */
1309#define SYSCTL_CAN1MPC_PWRCTL_SHIFT (0)
1310/** Memory Array Power Control Mask */
1311#define SYSCTL_CAN1MPC_PWRCTL_MASK (0x3)
1312/** Memory Array Power Control - Off */
1313#define SYSCTL_CAN1MPC_PWRCTL_ARR_OFF (0x0)
1314/** Memory Array Power Control - On */
1315#define SYSCTL_CAN1MPC_PWRCTL_ARR_ON (0x3)
1316/**@}*/
1317
1318/**
1319 * @brief Clock mode definitions
1320 * The definitions are specified in the form offset from
1321 * SYSCTL_BASE
1322 * @li CLOCK_RUN - Run mode
1323 * @li CLOCK_SLEEP - Sleep mode
1324 * @li CLOCK_DEEP_SLEEP - Deep-Sleep Mode
1325 */
1326enum msp432_clock_mode {
1327 CLOCK_RUN = 0x600,
1328 CLOCK_SLEEP = 0x700,
1329 CLOCK_DEEP_SLEEP = 0x800
1330};
1331
1332/**
1333 * @brief Power mode definitions
1334 *
1335 * @li POWER_DISABLE - Module is not powered and does not receive a clock
1336 * @li POWER_ENABLE - Module is powered but does not receive a clock
1337 *
1338 * @note If the module is in run, sleep or deep-sleep mode - the module
1339 * is powered and receives a clock regardless of the value of power mode.
1340 */
1341enum msp432_power_mode {
1342 POWER_DISABLE = false,
1343 POWER_ENABLE = true
1344};
1345
1346#define _REG_BIT(base, bit) (((base) << 5) + (bit))
1347
1348/**
1349 * @brief Peripheral list definitions
1350 * The definitions are specified in the form
1351 * 31:5 register offset from first register for SR, PP, RCGC,
1352 * SCGC, DCGC, PC, PR
1353 * 4:0 bit offset for the given peripheral
1354 */
1355enum msp432_periph {
1356
1357 PERIPH_WD0 = _REG_BIT(0x00, 0),
1358 PERIPH_WD1,
1359
1360 PERIPH_TIMER0 = _REG_BIT(0x04, 0),
1361 PERIPH_TIMER1,
1362 PERIPH_TIMER2,
1363 PERIPH_TIMER3,
1364 PERIPH_TIMER4,
1365 PERIPH_TIMER5,
1366 PERIPH_TIMER6,
1367 PERIPH_TIMER7,
1368
1369 PERIPH_GPIOA = _REG_BIT(0x08, 0),
1370 PERIPH_GPIOB,
1371 PERIPH_GPIOC,
1372 PERIPH_GPIOD,
1373 PERIPH_GPIOE,
1374 PERIPH_GPIOF,
1375 PERIPH_GPIOG,
1376 PERIPH_GPIOH,
1377 PERIPH_GPIOJ,
1378 PERIPH_GPIOK,
1379 PERIPH_GPIOL,
1380 PERIPH_GPIOM,
1381 PERIPH_GPION,
1382 PERIPH_GPIOP,
1383 PERIPH_GPIOQ,
1384 PERIPH_GPIOR,
1385 PERIPH_GPIOS,
1386 PERIPH_GPIOT,
1387
1388 PERIPH_DMA = _REG_BIT(0x0C, 0),
1389
1390 PERIPH_EPI = _REG_BIT(0x10, 0),
1391
1392 PERIPH_HIB = _REG_BIT(0x14, 0),
1393
1394 PERIPH_UART0 = _REG_BIT(0x18, 0),
1395 PERIPH_UART1,
1396 PERIPH_UART2,
1397 PERIPH_UART3,
1398 PERIPH_UART4,
1399 PERIPH_UART5,
1400 PERIPH_UART6,
1401 PERIPH_UART7,
1402
1403 PERIPH_SSI0 = _REG_BIT(0x1C, 0),
1404 PERIPH_SSI1,
1405 PERIPH_SSI2,
1406 PERIPH_SSI3,
1407
1408 PERIPH_I2C0 = _REG_BIT(0x20, 0),
1409 PERIPH_I2C1,
1410 PERIPH_I2C2,
1411 PERIPH_I2C3,
1412 PERIPH_I2C4,
1413 PERIPH_I2C5,
1414 PERIPH_I2C6,
1415 PERIPH_I2C7,
1416 PERIPH_I2C8,
1417 PERIPH_I2C9,
1418
1419 PERIPH_USB0 = _REG_BIT(0x28, 0),
1420
1421 PERIPH_EPHY = _REG_BIT(0x30, 0),
1422
1423 PERIPH_CAN0 = _REG_BIT(0x34, 0),
1424 PERIPH_CAN1,
1425
1426 PERIPH_ADC0 = _REG_BIT(0x38, 0),
1427 PERIPH_ADC1,
1428
1429 PERIPH_ACMP = _REG_BIT(0x3C, 0),
1430
1431 PERIPH_PWM = _REG_BIT(0x40, 0),
1432
1433 PERIPH_QEI = _REG_BIT(0x44, 0),
1434
1435 PERIPH_EEPROM = _REG_BIT(0x58, 0),
1436
1437 PERIPH_CCM = _REG_BIT(0x74, 0),
1438
1439 PERIPH_LCD = _REG_BIT(0x90, 0),
1440
1441 PERIPH_OWIRE = _REG_BIT(0x98, 0),
1442
1443 PERIPH_EMAC = _REG_BIT(0x9C, 0),
1444
1445 PERIPH_PRB = _REG_BIT(0xA0, 0)
1446};
1447
1448#undef _REG_BIT
1449
1450/* Function prototypes ------------------------------------------------------ */
1451
1452BEGIN_DECLS
1453
1454void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode,
1455 enum msp432_periph periph);
1456void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode,
1457 enum msp432_periph periph);
1458
1459void sysctl_periph_reset(enum msp432_periph periph);
1460void sysctl_periph_clear_reset(enum msp432_periph periph);
1461
1462bool sysctl_periph_is_present(enum msp432_periph periph);
1463bool sysctl_periph_is_ready(enum msp432_periph periph);
1464void sysctl_periph_set_power_state(enum msp432_power_mode power_mode,
1465 enum msp432_periph periph);
1466
1467END_DECLS
1468
1469/**@}*/
1470
1471#endif /* MSP432E4_SYSTEMCONTROL_H */
END_DECLS
#define END_DECLS
Definition: common.h:34
BEGIN_DECLS
#define BEGIN_DECLS
Definition: common.h:33
sysctl_periph_set_power_state
void sysctl_periph_set_power_state(enum msp432_power_mode power_mode, enum msp432_periph periph)
System Control Peripheral Set Power State.
Definition: systemcontrol.c:119
sysctl_periph_is_ready
bool sysctl_periph_is_ready(enum msp432_periph periph)
System Control Peripheral Is Ready.
Definition: systemcontrol.c:102
msp432_power_mode
msp432_power_mode
Power mode definitions.
Definition: systemcontrol.h:1341
sysctl_periph_clock_disable
void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode, enum msp432_periph periph)
System Control Disable Peripheral Clock.
Definition: systemcontrol.c:58
sysctl_periph_clock_enable
void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode, enum msp432_periph periph)
System Control Enable Peripheral Clock.
Definition: systemcontrol.c:46
sysctl_periph_reset
void sysctl_periph_reset(enum msp432_periph periph)
System Control Peripheral Software Reset.
Definition: systemcontrol.c:69
_REG_BIT
#define _REG_BIT(base, bit)
Definition: systemcontrol.h:1346
msp432_clock_mode
msp432_clock_mode
Clock mode definitions The definitions are specified in the form offset from SYSCTL_BASE.
Definition: systemcontrol.h:1326
msp432_periph
msp432_periph
Peripheral list definitions The definitions are specified in the form 31:5 register offset from first...
Definition: systemcontrol.h:1355
sysctl_periph_clear_reset
void sysctl_periph_clear_reset(enum msp432_periph periph)
System Control Peripheral Clear Software Reset.
Definition: systemcontrol.c:79
sysctl_periph_is_present
bool sysctl_periph_is_present(enum msp432_periph periph)
System Control Peripheral Is Present.
Definition: systemcontrol.c:89
POWER_ENABLE
@ POWER_ENABLE
Definition: systemcontrol.h:1343
POWER_DISABLE
@ POWER_DISABLE
Definition: systemcontrol.h:1342
CLOCK_RUN
@ CLOCK_RUN
Definition: systemcontrol.h:1327
CLOCK_DEEP_SLEEP
@ CLOCK_DEEP_SLEEP
Definition: systemcontrol.h:1329
CLOCK_SLEEP
@ CLOCK_SLEEP
Definition: systemcontrol.h:1328
PERIPH_I2C1
@ PERIPH_I2C1
Definition: systemcontrol.h:1409
PERIPH_UART3
@ PERIPH_UART3
Definition: systemcontrol.h:1397
PERIPH_UART2
@ PERIPH_UART2
Definition: systemcontrol.h:1396
PERIPH_EPI
@ PERIPH_EPI
Definition: systemcontrol.h:1390
PERIPH_GPIOC
@ PERIPH_GPIOC
Definition: systemcontrol.h:1371
PERIPH_QEI
@ PERIPH_QEI
Definition: systemcontrol.h:1433
PERIPH_UART0
@ PERIPH_UART0
Definition: systemcontrol.h:1394
PERIPH_CCM
@ PERIPH_CCM
Definition: systemcontrol.h:1437
PERIPH_GPIOS
@ PERIPH_GPIOS
Definition: systemcontrol.h:1385
PERIPH_USB0
@ PERIPH_USB0
Definition: systemcontrol.h:1419
PERIPH_GPIOA
@ PERIPH_GPIOA
Definition: systemcontrol.h:1369
PERIPH_PRB
@ PERIPH_PRB
Definition: systemcontrol.h:1445
PERIPH_DMA
@ PERIPH_DMA
Definition: systemcontrol.h:1388
PERIPH_GPIOT
@ PERIPH_GPIOT
Definition: systemcontrol.h:1386
PERIPH_CAN0
@ PERIPH_CAN0
Definition: systemcontrol.h:1423
PERIPH_UART7
@ PERIPH_UART7
Definition: systemcontrol.h:1401
PERIPH_UART6
@ PERIPH_UART6
Definition: systemcontrol.h:1400
PERIPH_I2C2
@ PERIPH_I2C2
Definition: systemcontrol.h:1410
PERIPH_TIMER4
@ PERIPH_TIMER4
Definition: systemcontrol.h:1364
PERIPH_I2C5
@ PERIPH_I2C5
Definition: systemcontrol.h:1413
PERIPH_UART1
@ PERIPH_UART1
Definition: systemcontrol.h:1395
PERIPH_I2C8
@ PERIPH_I2C8
Definition: systemcontrol.h:1416
PERIPH_GPIOH
@ PERIPH_GPIOH
Definition: systemcontrol.h:1376
PERIPH_TIMER2
@ PERIPH_TIMER2
Definition: systemcontrol.h:1362
PERIPH_TIMER5
@ PERIPH_TIMER5
Definition: systemcontrol.h:1365
PERIPH_GPIOP
@ PERIPH_GPIOP
Definition: systemcontrol.h:1382
PERIPH_TIMER6
@ PERIPH_TIMER6
Definition: systemcontrol.h:1366
PERIPH_GPION
@ PERIPH_GPION
Definition: systemcontrol.h:1381
PERIPH_I2C4
@ PERIPH_I2C4
Definition: systemcontrol.h:1412
PERIPH_GPIOD
@ PERIPH_GPIOD
Definition: systemcontrol.h:1372
PERIPH_GPIOB
@ PERIPH_GPIOB
Definition: systemcontrol.h:1370
PERIPH_GPIOR
@ PERIPH_GPIOR
Definition: systemcontrol.h:1384
PERIPH_TIMER3
@ PERIPH_TIMER3
Definition: systemcontrol.h:1363
PERIPH_ACMP
@ PERIPH_ACMP
Definition: systemcontrol.h:1429
PERIPH_GPIOE
@ PERIPH_GPIOE
Definition: systemcontrol.h:1373
PERIPH_CAN1
@ PERIPH_CAN1
Definition: systemcontrol.h:1424
PERIPH_LCD
@ PERIPH_LCD
Definition: systemcontrol.h:1439
PERIPH_WD1
@ PERIPH_WD1
Definition: systemcontrol.h:1358
PERIPH_GPIOK
@ PERIPH_GPIOK
Definition: systemcontrol.h:1378
PERIPH_GPIOG
@ PERIPH_GPIOG
Definition: systemcontrol.h:1375
PERIPH_I2C9
@ PERIPH_I2C9
Definition: systemcontrol.h:1417
PERIPH_I2C7
@ PERIPH_I2C7
Definition: systemcontrol.h:1415
PERIPH_ADC1
@ PERIPH_ADC1
Definition: systemcontrol.h:1427
PERIPH_ADC0
@ PERIPH_ADC0
Definition: systemcontrol.h:1426
PERIPH_UART5
@ PERIPH_UART5
Definition: systemcontrol.h:1399
PERIPH_SSI1
@ PERIPH_SSI1
Definition: systemcontrol.h:1404
PERIPH_GPIOJ
@ PERIPH_GPIOJ
Definition: systemcontrol.h:1377
PERIPH_HIB
@ PERIPH_HIB
Definition: systemcontrol.h:1392
PERIPH_SSI0
@ PERIPH_SSI0
Definition: systemcontrol.h:1403
PERIPH_GPIOQ
@ PERIPH_GPIOQ
Definition: systemcontrol.h:1383
PERIPH_EEPROM
@ PERIPH_EEPROM
Definition: systemcontrol.h:1435
PERIPH_PWM
@ PERIPH_PWM
Definition: systemcontrol.h:1431
PERIPH_SSI2
@ PERIPH_SSI2
Definition: systemcontrol.h:1405
PERIPH_UART4
@ PERIPH_UART4
Definition: systemcontrol.h:1398
PERIPH_SSI3
@ PERIPH_SSI3
Definition: systemcontrol.h:1406
PERIPH_I2C3
@ PERIPH_I2C3
Definition: systemcontrol.h:1411
PERIPH_GPIOL
@ PERIPH_GPIOL
Definition: systemcontrol.h:1379
PERIPH_GPIOM
@ PERIPH_GPIOM
Definition: systemcontrol.h:1380
PERIPH_I2C6
@ PERIPH_I2C6
Definition: systemcontrol.h:1414
PERIPH_EPHY
@ PERIPH_EPHY
Definition: systemcontrol.h:1421
PERIPH_TIMER7
@ PERIPH_TIMER7
Definition: systemcontrol.h:1367
PERIPH_EMAC
@ PERIPH_EMAC
Definition: systemcontrol.h:1443
PERIPH_WD0
@ PERIPH_WD0
Definition: systemcontrol.h:1357
PERIPH_TIMER1
@ PERIPH_TIMER1
Definition: systemcontrol.h:1361
PERIPH_GPIOF
@ PERIPH_GPIOF
Definition: systemcontrol.h:1374
PERIPH_OWIRE
@ PERIPH_OWIRE
Definition: systemcontrol.h:1441
PERIPH_I2C0
@ PERIPH_I2C0
Definition: systemcontrol.h:1408
PERIPH_TIMER0
@ PERIPH_TIMER0
Definition: systemcontrol.h:1360