System Control Divisor and Source Clock Configuration Register Values.
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System Control Divisor and Source Clock Configuration Register Values.
◆ SYSCTL_DIVSCLK_DIV_1
#define SYSCTL_DIVSCLK_DIV_1 (0x0) |
◆ SYSCTL_DIVSCLK_DIV_2
#define SYSCTL_DIVSCLK_DIV_2 (0x1) |
◆ SYSCTL_DIVSCLK_DIV_MASK
#define SYSCTL_DIVSCLK_DIV_MASK (0xF) |
◆ SYSCTL_DIVSCLK_DIV_SHIFT
#define SYSCTL_DIVSCLK_DIV_SHIFT (0) |
◆ SYSCTL_DIVSCLK_EN
#define SYSCTL_DIVSCLK_EN (1 << 31) |
◆ SYSCTL_DIVSCLK_SRC_MASK
#define SYSCTL_DIVSCLK_SRC_MASK (0x3) |
◆ SYSCTL_DIVSCLK_SRC_MOSC
#define SYSCTL_DIVSCLK_SRC_MOSC (0x2) |
◆ SYSCTL_DIVSCLK_SRC_PIOSC
#define SYSCTL_DIVSCLK_SRC_PIOSC (0x1) |
◆ SYSCTL_DIVSCLK_SRC_SHIFT
#define SYSCTL_DIVSCLK_SRC_SHIFT (16) |