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libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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Macros | |
| #define | SCB_CPUID MMIO32(SCB_BASE + 0x00) |
| CPUID: CPUID base register. More... | |
| #define | SCB_ICSR MMIO32(SCB_BASE + 0x04) |
| ICSR: Interrupt Control State Register. More... | |
| #define | SCB_VTOR MMIO32(SCB_BASE + 0x08) |
| VTOR: Vector Table Offset Register. More... | |
| #define | SCB_AIRCR MMIO32(SCB_BASE + 0x0C) |
| AIRCR: Application Interrupt and Reset Control Register. More... | |
| #define | SCB_SCR MMIO32(SCB_BASE + 0x10) |
| SCR: System Control Register. More... | |
| #define | SCB_CCR MMIO32(SCB_BASE + 0x14) |
| CCR: Configuration Control Register. More... | |
| #define | SCB_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id)) |
| System Handler Priority 8 bits Registers, SHPR1/2/3. More... | |
| #define | SCB_SHCSR MMIO32(SCB_BASE + 0x24) |
| SHCSR: System Handler Control and State Register. More... | |
| #define | SCB_DFSR MMIO32(SCB_BASE + 0x30) |
| DFSR: Debug Fault Status Register. More... | |
| #define | SCB_CFSR MMIO32(SCB_BASE + 0x28) |
| CFSR: Configurable Fault Status Registers. More... | |
| #define | SCB_HFSR MMIO32(SCB_BASE + 0x2C) |
| HFSR: Hard Fault Status Register. More... | |
| #define | SCB_MMFAR MMIO32(SCB_BASE + 0x34) |
| MMFAR: Memory Manage Fault Address Register. More... | |
| #define | SCB_BFAR MMIO32(SCB_BASE + 0x38) |
| BFAR: Bus Fault Address Register. More... | |
| #define | SCB_AFSR MMIO32(SCB_BASE + 0x3C) |
| AFSR: Auxiliary Fault Status Register. More... | |
| #define | SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) |
| ID_PFR0: Processor Feature Register 0. More... | |
| #define | SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) |
| ID_PFR1: Processor Feature Register 1. More... | |
| #define | SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) |
| ID_DFR0: Debug Features Register 0. More... | |
| #define | SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) |
| ID_AFR0: Auxiliary Features Register 0. More... | |
| #define | SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) |
| ID_MMFR0: Memory Model Feature Register 0. More... | |
| #define | SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) |
| ID_MMFR1: Memory Model Feature Register 1. More... | |
| #define | SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) |
| ID_MMFR2: Memory Model Feature Register 2. More... | |
| #define | SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) |
| ID_MMFR3: Memory Model Feature Register 3. More... | |
| #define | SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) |
| ID_ISAR0: Instruction Set Attributes Register 0. More... | |
| #define | SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) |
| ID_ISAR1: Instruction Set Attributes Register 1. More... | |
| #define | SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) |
| ID_ISAR2: Instruction Set Attributes Register 2. More... | |
| #define | SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) |
| ID_ISAR3: Instruction Set Attributes Register 3. More... | |
| #define | SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) |
| ID_ISAR4: Instruction Set Attributes Register 4. More... | |
| #define | SCB_CPACR MMIO32(SCB_BASE + 0x88) |
| CPACR: Coprocessor Access Control Register. More... | |
| #define | SCB_FPCCR MMIO32(SCB_BASE + 0x234) |
| FPCCR: Floating-Point Context Control Register. More... | |
| #define | SCB_FPCAR MMIO32(SCB_BASE + 0x238) |
| FPCAR: Floating-Point Context Address Register. More... | |
| #define | SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) |
| FPDSCR: Floating-Point Default Status Control Register. More... | |
| #define | SCB_MVFR0 MMIO32(SCB_BASE + 0x240) |
| MVFR0: Media and Floating-Point Feature Register 0. More... | |
| #define | SCB_MVFR1 MMIO32(SCB_BASE + 0x244) |
| MVFR1: Media and Floating-Point Feature Register 1. More... | |
1.9.4