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libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control. More...
Modules | |
| SCS Registers | |
Macros | |
| #define | SCS_DHCSR_DBGKEY 0xA05F0000 |
| #define | SCS_DHCSR_C_DEBUGEN 0x00000001 |
| #define | SCS_DHCSR_C_HALT 0x00000002 |
| #define | SCS_DHCSR_C_STEP 0x00000004 |
| #define | SCS_DHCSR_C_MASKINTS 0x00000008 |
| #define | SCS_DHCSR_C_SNAPSTALL 0x00000020 |
| #define | SCS_DHCSR_S_REGRDY 0x00010000 |
| #define | SCS_DHCSR_S_HALT 0x00020000 |
| #define | SCS_DHCSR_S_SLEEP 0x00040000 |
| #define | SCS_DHCSR_S_LOCKUP 0x00080000 |
| #define | SCS_DHCSR_S_RETIRE_ST 0x01000000 |
| #define | SCS_DHCSR_S_RESET_ST 0x02000000 |
| #define | SCS_DCRSR_REGSEL_MASK 0x0000001F |
| #define | SCS_DCRSR_REGSEL_XPSR 0x00000010 |
| #define | SCS_DCRSR_REGSEL_MSP 0x00000011 |
| #define | SCS_DCRSR_REGSEL_PSP 0x00000012 |
| #define | SCS_DEMCR_TRCENA (1 << 24) |
| #define | SCS_DEMCR_MON_REQ (1 << 19) |
| #define | SCS_DEMCR_MON_STEP (1 << 18) |
| #define | SCS_DEMCR_VC_MON_PEND (1 << 17) |
| #define | SCS_DEMCR_VC_MON_EN (1 << 16) |
| #define | SCS_DEMCR_VC_HARDERR (1 << 10) |
| #define | SCS_DEMCR_VC_INTERR (1 << 9) |
| #define | SCS_DEMCR_VC_BUSERR (1 << 8) |
| #define | SCS_DEMCR_VC_STATERR (1 << 7) |
| #define | SCS_DEMCR_VC_CHKERR (1 << 6) |
| #define | SCS_DEMCR_VC_NOCPERR (1 << 5) |
| #define | SCS_DEMCR_VC_MMERR (1 << 4) |
| #define | SCS_DEMCR_VC_CORERESET (1 << 0) |
| #define | SCS_DWT_LSR MMIO32(SCS_DWT_BASE + 0xFB4) |
| #define | SCS_DWT_LAR MMIO32(SCS_DWT_BASE + 0xFB0) |
The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control.
The SCS registers divide into the following groups:
Most portions of the SCS are covered by their own header files, eg systick.h, dwt.h, scb.h, itm.h, fpb.h
1.9.4