libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
lptimer_common_all.h
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1/** @addtogroup lptimer_defines
2 *
3 * @author @htmlonly &copy; @endhtmlonly 2009 Piotr Esden-Tempski <piotr@esden.net>
4 * @author @htmlonly &copy; @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
5 *
6 */
7/*
8 * This file is part of the libopencm3 project.
9 *
10 * Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net>
11 * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com>
12 *
13 * This library is free software: you can redistribute it and/or modify
14 * it under the terms of the GNU Lesser General Public License as published by
15 * the Free Software Foundation, either version 3 of the License, or
16 * (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public License
24 * along with this library. If not, see <http://www.gnu.org/licenses/>.
25 */
26
27/**@{*/
28
29/** @cond */
30#if defined(LIBOPENCM3_LPTIMER_H)
31/** @endcond */
32#ifndef LIBOPENCM3_LPTIMER_COMMON_H
33#define LIBOPENCM3_LPTIMER_COMMON_H
34
35/* --- LPTIM (low power timer) ------------------------------------------- */
36
37#define LPTIM_ISR(tim_base) MMIO32((tim_base) + 0x00)
38#define LPTIM_ICR(tim_base) MMIO32((tim_base) + 0x04)
39#define LPTIM_IER(tim_base) MMIO32((tim_base) + 0x08)
40#define LPTIM_CFGR(tim_base) MMIO32((tim_base) + 0x0C)
41#define LPTIM_CR(tim_base) MMIO32((tim_base) + 0x10)
42#define LPTIM_CMP(tim_base) MMIO32((tim_base) + 0x14)
43#define LPTIM_ARR(tim_base) MMIO32((tim_base) + 0x18)
44#define LPTIM_CNT(tim_base) MMIO32((tim_base) + 0x1C)
45
46#define LPTIM1_ISR LPTIM_ISR(LPTIM1_BASE)
47#define LPTIM1_ICR LPTIM_ICR(LPTIM1_BASE)
48#define LPTIM1_IER LPTIM_IER(LPTIM1_BASE)
49#define LPTIM1_CFGR LPTIM_CFGR(LPTIM1_BASE)
50#define LPTIM1_CR LPTIM_CR(LPTIM1_BASE)
51#define LPTIM1_CMP LPTIM_CMP(LPTIM1_BASE)
52#define LPTIM1_ARR LPTIM_ARR(LPTIM1_BASE)
53#define LPTIM1_CNT LPTIM_CNT(LPTIM1_BASE)
54
55#if defined(LPTIM2_BASE)
56#define LPTIM2_ISR LPTIM_ISR(LPTIM2_BASE)
57#define LPTIM2_ICR LPTIM_ICR(LPTIM2_BASE)
58#define LPTIM2_IER LPTIM_IER(LPTIM2_BASE)
59#define LPTIM2_CFGR LPTIM_CFGR(LPTIM2_BASE)
60#define LPTIM2_CR LPTIM_CR(LPTIM2_BASE)
61#define LPTIM2_CMP LPTIM_CMP(LPTIM2_BASE)
62#define LPTIM2_ARR LPTIM_ARR(LPTIM2_BASE)
63#define LPTIM2_CNT LPTIM_CNT(LPTIM2_BASE)
64#endif
65
66/** @defgroup lptim_isr LPTIM_ISR Interrupt and Status Register
67@{*/
68
69/** LPTIM_ISR_CMPM Compare match */
70#define LPTIM_ISR_CMPM (1 << 0)
71
72/** LPTIM_ISR_ARRM Autoreload match */
73#define LPTIM_ISR_ARRM (1 << 1)
74
75/** LPTIM_ISR_EXTTRIG External trigger edge event */
76#define LPTIM_ISR_EXTTRIG (1 << 2)
77
78/** LPTIM_ISR_CMPOK Compare register update OK */
79#define LPTIM_ISR_CMPOK (1 << 3)
80
81/** LPTIM_ISR_ARROK Autoreload register update OK */
82#define LPTIM_ISR_ARROK (1 << 4)
83
84/** LPTIM_ISR_UP Counter direction change down to up */
85#define LPTIM_ISR_UP (1 << 5)
86
87/** LPTIM_ISR_DOWN Counter direction change up to down */
88#define LPTIM_ISR_DOWN (1 << 6)
89
90/**@}*/
91
92/** @defgroup lptim_icr LPTIM_ICR Interrupt Clear Register
93@{*/
94
95/** LPTIM_ICR_CMPMCF compare match Clear Flag */
96#define LPTIM_ICR_CMPMCF (1 << 0)
97
98/** LPTIM_ICR_ARRMCF Autoreload match Clear Flag */
99#define LPTIM_ICR_ARRMCF (1 << 1)
100
101/** LPTIM_ICR_EXTTRIGCF External trigger valid edge Clear Flag */
102#define LPTIM_ICR_EXTTRIGCF (1 << 2)
103
104/** LPTIM_ICR_CMPOKCF Compare register update OK Clear Flag */
105#define LPTIM_ICR_CMPOKCF (1 << 3)
106
107/** LPTIM_ICR_ARROKCF Autoreload register update OK Clear Flag */
108#define LPTIM_ICR_ARROKCF (1 << 4)
109
110/** LPTIM_ICR_UPCF Direction change to UP Clear Flag */
111#define LPTIM_ICR_UPCF (1 << 5)
112
113/** LPTIM_ICR_DOWNCF Direction change to down Clear Flag */
114#define LPTIM_ICR_DOWNCF (1 << 6)
115
116/**@}*/
117
118/** @defgroup lptim_ier LPTIM_IER Interrupt Enable Register
119@{*/
120
121/** LPTIM_IER_CMPMIE Compare match Interrupt Enable */
122#define LPTIM_IER_CMPMIE (1 << 0)
123
124/** LPTIM_IER_ARRMIE Autoreload match Interrupt Enable */
125#define LPTIM_IER_ARRMIE (1 << 1)
126
127/** LPTIM_IER_EXTTRIGIE External trigger valid edge Interrupt Enable */
128#define LPTIM_IER_EXTTRIGIE (1 << 2)
129
130/** LPTIM_IER_CMPOKIE Compare register update OK Interrupt Enable */
131#define LPTIM_IER_CMPOKIE (1 << 3)
132
133/** LPTIM_IER_ARROKIE Autoreload register update OK Interrupt Enable */
134#define LPTIM_IER_ARROKIE (1 << 4)
135
136/** LPTIM_IER_UPIE Direction change to UP Interrupt Enable */
137#define LPTIM_IER_UPIE (1 << 5)
138
139/** LPTIM_IER_DOWNIE Direction change to down Interrupt Enable */
140#define LPTIM_IER_DOWNIE (1 << 6)
141
142/**@}*/
143
144/** @defgroup lptim_cfgr LPTIM_CFGR Configuration Register
145@{*/
146
147/** CKSEL: Select internal (0) or external clock source (1) */
148#define LPTIM_CFGR_CKSEL (1 << 0)
149
150#define LPTIM_CFGR_CKPOL_SHIFT 1
151#define LPTIM_CFGR_CKPOL_MASK 0x03
152#define LPTIM_CFGR_CKPOL (3 << LPTIM_CFGR_CKPOL_SHIFT)
153/** @defgroup lptim_cfgr_ckpol LPTIM_CFGR CKPOL Clock Polarity
154@{*/
155#define LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT)
156#define LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT)
157#define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT)
158#define LPTIM_CFGR_CKPOL_ENC_1 (0 << LPTIM_CFGR_CKPOL_SHIFT)
159#define LPTIM_CFGR_CKPOL_ENC_2 (1 << LPTIM_CFGR_CKPOL_SHIFT)
160#define LPTIM_CFGR_CKPOL_ENC_3 (2 << LPTIM_CFGR_CKPOL_SHIFT)
161/**@}*/
162
163#define LPTIM_CFGR_CKFLT_SHIFT 3
164#define LPTIM_CFGR_CKFLT_MASK 0x03
165#define LPTIM_CFGR_CKFLT (3 << LPTIM_CFGR_CKFLT_SHIFT)
166/** @defgroup lptim_cfgr_ckflt LPTIM_CFGR CKFLT Configurable digital filter for external clock
167@{*/
168#define LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT)
169#define LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT)
170#define LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT)
171/**@}*/
172
173#define LPTIM_CFGR_TRGFLT_SHIFT 6
174#define LPTIM_CFGR_TRGFLT_MASK 0x03
175#define LPTIM_CFGR_TRGFLT (3 << LPTIM_CFGR_TRGFLT_SHIFT)
176/** @defgroup lptim_cfgr_trgflt LPTIM_CFGR TRGFLT Configurable digital filter for trigger
177@{*/
178#define LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT)
179#define LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT)
180#define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT)
181/**@}*/
182
183#define LPTIM_CFGR_PRESC_SHIFT 9
184#define LPTIM_CFGR_PRESC_MASK 0x07
185#define LPTIM_CFGR_PRESC (7 << LPTIM_CFGR_PRESC_SHIFT)
186/** @defgroup lptim_cfgr_presc LPTIM_CFGR PRESC Clock prescaler
187@{*/
188#define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT)
189#define LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT)
190#define LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT)
191#define LPTIM_CFGR_PRESC_8 (3 << LPTIM_CFGR_PRESC_SHIFT)
192#define LPTIM_CFGR_PRESC_16 (4 << LPTIM_CFGR_PRESC_SHIFT)
193#define LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT)
194#define LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT)
195#define LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT)
196/**@}*/
197
198#define LPTIM_CFGR_TRIGSEL_SHIFT 13
199#define LPTIM_CFGR_TRIGSEL_MASK 0x07
200#define LPTIM_CFGR_TRIGSEL (7 << LPTIM_CFGR_TRIGSEL_SHIFT)
201/** @defgroup lptim_cfgr_trigsel LPTIM_CFGR TRIGSEL Trigger selector
202@{*/
203#define LPTIM_CFGR_TRIGSEL_EXT_TRIG0 (0 << LPTIM_CFGR_TRIGSEL_SHIFT)
204#define LPTIM_CFGR_TRIGSEL_EXT_TRIG1 (1 << LPTIM_CFGR_TRIGSEL_SHIFT)
205#define LPTIM_CFGR_TRIGSEL_EXT_TRIG2 (2 << LPTIM_CFGR_TRIGSEL_SHIFT)
206#define LPTIM_CFGR_TRIGSEL_EXT_TRIG3 (3 << LPTIM_CFGR_TRIGSEL_SHIFT)
207#define LPTIM_CFGR_TRIGSEL_EXT_TRIG4 (4 << LPTIM_CFGR_TRIGSEL_SHIFT)
208/* 5 is reserved */
209#define LPTIM_CFGR_TRIGSEL_EXT_TRIG6 (6 << LPTIM_CFGR_TRIGSEL_SHIFT)
210#define LPTIM_CFGR_TRIGSEL_EXT_TRIG7 (7 << LPTIM_CFGR_TRIGSEL_SHIFT)
211/**@}*/
212
213#define LPTIM_CFGR_TRIGEN_SHIFT 17
214#define LPTIM_CFGR_TRIGEN_MASK 0x07
215#define LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT)
216/** @defgroup LPTIM_CFGR_TRIGEN LPTIM_CFGR TRIGEN Trigger enable and polarity
217@{*/
218#define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT)
219#define LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT)
220#define LPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT)
221#define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT)
222/**@}*/
223
224/** TIMOUT: Timeout enable */
225#define LPTIM_CFGR_TIMOUT (1 << 19)
226
227/** WAVE: Waveform shape */
228#define LPTIM_CFGR_WAVE (1 << 20)
229
230/** WAVPOL: Waveform shape polarity */
231#define LPTIM_CFGR_WAVPOL (1 << 21)
232
233/** PRELOAD: Register update mode */
234#define LPTIM_CFGR_PRELOAD (1 << 22)
235
236/** COUNTMODE: Counter mode enable */
237#define LPTIM_CFGR_COUNTMODE (1 << 23)
238
239/** ENC: Encoder mode enable */
240#define LPTIM_CFGR_ENC (1 << 24)
241
242/**@}*/
243
244/** @defgroup lptim_cr LPTIM_CR Control Register
245@{*/
246
247/** ENABLE: LPTIM Enable */
248#define LPTIM_CR_ENABLE (1 << 0)
249
250/** SNGSTRT: Start in Single Mode */
251#define LPTIM_CR_SNGSTRT (1 << 1)
252
253/** CNGSTRT: Start in Continuous Mode */
254#define LPTIM_CR_CNTSTRT (1 << 2)
255
256/**@}*/
257
258/* --- LPTIM function prototypes --------------------------------------------- */
259
261
262void lptimer_enable(uint32_t timer_peripheral);
263void lptimer_disable(uint32_t timer_peripheral);
264
265void lptimer_start_counter(uint32_t timer_peripheral, uint32_t mode);
266void lptimer_set_counter(uint32_t timer_peripheral, uint16_t count);
267uint16_t lptimer_get_counter(uint32_t timer_peripheral);
268void lptimer_set_compare(uint32_t timer_peripheral, uint16_t compare_value);
269void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value);
270void lptimer_enable_preload(uint32_t lptimer_peripheral);
271void lptimer_disable_preload(uint32_t lptimer_peripheral);
272void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral);
273void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral);
274
275void lptimer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler);
276void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen);
277void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source);
278void lptimer_set_internal_clock_source(uint32_t timer_peripheral);
279void lptimer_set_external_clock_source(uint32_t timer_peripheral);
280
281void lptimer_clear_flag(uint32_t timer_peripheral, uint32_t flag);
282bool lptimer_get_flag(uint32_t timer_peripheral, uint32_t flag);
283void lptimer_enable_irq(uint32_t timer_peripheral, uint32_t irq);
284void lptimer_disable_irq(uint32_t timer_peripheral, uint32_t irq);
285
286
288
289#endif
290/** @cond */
291#else
292#warning "lptimer_common_all.h should not be included directly, only via lptimer.h"
293#endif
294/** @endcond */
295
296/**@}*/
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral)
Set lptimer Waveform Output Polarity High.
void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral)
Set lptimer Waveform Output Polarity Low.
uint16_t lptimer_get_counter(uint32_t timer_peripheral)
Read lptimer Counter.
void lptimer_enable_preload(uint32_t lptimer_peripheral)
Enable lptimer Preload mode.
void lptimer_disable_irq(uint32_t timer_peripheral, uint32_t irq)
Disable lptimer Interrupts.
void lptimer_start_counter(uint32_t timer_peripheral, uint32_t mode)
Start lptimer in a given mode.
void lptimer_enable_irq(uint32_t timer_peripheral, uint32_t irq)
Enable lptimer interrupts.
void lptimer_set_internal_clock_source(uint32_t timer_peripheral)
Set lptimer Internal Clock source.
void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen)
Enable lptimer External Trigger.
void lptimer_disable(uint32_t timer_peripheral)
Disable lptimer.
void lptimer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler)
Set lptimer clock prescaler.
void lptimer_disable_preload(uint32_t lptimer_peripheral)
Disable lptimer Preload mode.
bool lptimer_get_flag(uint32_t timer_peripheral, uint32_t flag)
Read lptimer Status Flag.
void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value)
Set lptimer period.
void lptimer_set_compare(uint32_t timer_peripheral, uint16_t compare_value)
Set lptimer counter Compare Value.
void lptimer_set_external_clock_source(uint32_t timer_peripheral)
Set lptimer External Clock source.
void lptimer_set_counter(uint32_t timer_peripheral, uint16_t count)
Set lptimer Counter.
void lptimer_clear_flag(uint32_t timer_peripheral, uint32_t flag)
Clear lptimer Status Flag.
void lptimer_enable(uint32_t timer_peripheral)
Enable lptimer.
void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source)
Select lptimer Trigger Source.