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Macros | |
| #define | LPTIM_ISR(tim_base) MMIO32((tim_base) + 0x00) |
| #define | LPTIM_ICR(tim_base) MMIO32((tim_base) + 0x04) |
| #define | LPTIM_IER(tim_base) MMIO32((tim_base) + 0x08) |
| #define | LPTIM_CFGR(tim_base) MMIO32((tim_base) + 0x0C) |
| #define | LPTIM_CR(tim_base) MMIO32((tim_base) + 0x10) |
| #define | LPTIM_CMP(tim_base) MMIO32((tim_base) + 0x14) |
| #define | LPTIM_ARR(tim_base) MMIO32((tim_base) + 0x18) |
| #define | LPTIM_CNT(tim_base) MMIO32((tim_base) + 0x1C) |
| #define | LPTIM1_ISR LPTIM_ISR(LPTIM1_BASE) |
| #define | LPTIM1_ICR LPTIM_ICR(LPTIM1_BASE) |
| #define | LPTIM1_IER LPTIM_IER(LPTIM1_BASE) |
| #define | LPTIM1_CFGR LPTIM_CFGR(LPTIM1_BASE) |
| #define | LPTIM1_CR LPTIM_CR(LPTIM1_BASE) |
| #define | LPTIM1_CMP LPTIM_CMP(LPTIM1_BASE) |
| #define | LPTIM1_ARR LPTIM_ARR(LPTIM1_BASE) |
| #define | LPTIM1_CNT LPTIM_CNT(LPTIM1_BASE) |
| #define | LPTIM_ISR_CMPM (1 << 0) |
| LPTIM_ISR_CMPM Compare match. More... | |
| #define | LPTIM_ISR_ARRM (1 << 1) |
| LPTIM_ISR_ARRM Autoreload match. More... | |
| #define | LPTIM_ISR_EXTTRIG (1 << 2) |
| LPTIM_ISR_EXTTRIG External trigger edge event. More... | |
| #define | LPTIM_ISR_CMPOK (1 << 3) |
| LPTIM_ISR_CMPOK Compare register update OK. More... | |
| #define | LPTIM_ISR_ARROK (1 << 4) |
| LPTIM_ISR_ARROK Autoreload register update OK. More... | |
| #define | LPTIM_ISR_UP (1 << 5) |
| LPTIM_ISR_UP Counter direction change down to up. More... | |
| #define | LPTIM_ISR_DOWN (1 << 6) |
| LPTIM_ISR_DOWN Counter direction change up to down. More... | |
| #define | LPTIM_ICR_CMPMCF (1 << 0) |
| LPTIM_ICR_CMPMCF compare match Clear Flag. More... | |
| #define | LPTIM_ICR_ARRMCF (1 << 1) |
| LPTIM_ICR_ARRMCF Autoreload match Clear Flag. More... | |
| #define | LPTIM_ICR_EXTTRIGCF (1 << 2) |
| LPTIM_ICR_EXTTRIGCF External trigger valid edge Clear Flag. More... | |
| #define | LPTIM_ICR_CMPOKCF (1 << 3) |
| LPTIM_ICR_CMPOKCF Compare register update OK Clear Flag. More... | |
| #define | LPTIM_ICR_ARROKCF (1 << 4) |
| LPTIM_ICR_ARROKCF Autoreload register update OK Clear Flag. More... | |
| #define | LPTIM_ICR_UPCF (1 << 5) |
| LPTIM_ICR_UPCF Direction change to UP Clear Flag. More... | |
| #define | LPTIM_ICR_DOWNCF (1 << 6) |
| LPTIM_ICR_DOWNCF Direction change to down Clear Flag. More... | |
| #define | LPTIM_IER_CMPMIE (1 << 0) |
| LPTIM_IER_CMPMIE Compare match Interrupt Enable. More... | |
| #define | LPTIM_IER_ARRMIE (1 << 1) |
| LPTIM_IER_ARRMIE Autoreload match Interrupt Enable. More... | |
| #define | LPTIM_IER_EXTTRIGIE (1 << 2) |
| LPTIM_IER_EXTTRIGIE External trigger valid edge Interrupt Enable. More... | |
| #define | LPTIM_IER_CMPOKIE (1 << 3) |
| LPTIM_IER_CMPOKIE Compare register update OK Interrupt Enable. More... | |
| #define | LPTIM_IER_ARROKIE (1 << 4) |
| LPTIM_IER_ARROKIE Autoreload register update OK Interrupt Enable. More... | |
| #define | LPTIM_IER_UPIE (1 << 5) |
| LPTIM_IER_UPIE Direction change to UP Interrupt Enable. More... | |
| #define | LPTIM_IER_DOWNIE (1 << 6) |
| LPTIM_IER_DOWNIE Direction change to down Interrupt Enable. More... | |
| #define | LPTIM_CFGR_CKSEL (1 << 0) |
| CKSEL: Select internal (0) or external clock source (1) More... | |
| #define | LPTIM_CFGR_CKPOL_SHIFT 1 |
| #define | LPTIM_CFGR_CKPOL_MASK 0x03 |
| #define | LPTIM_CFGR_CKPOL (3 << LPTIM_CFGR_CKPOL_SHIFT) |
| #define | LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT) |
| #define | LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT) |
| #define | LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) |
| #define | LPTIM_CFGR_CKPOL_ENC_1 (0 << LPTIM_CFGR_CKPOL_SHIFT) |
| #define | LPTIM_CFGR_CKPOL_ENC_2 (1 << LPTIM_CFGR_CKPOL_SHIFT) |
| #define | LPTIM_CFGR_CKPOL_ENC_3 (2 << LPTIM_CFGR_CKPOL_SHIFT) |
| #define | LPTIM_CFGR_CKFLT_SHIFT 3 |
| #define | LPTIM_CFGR_CKFLT_MASK 0x03 |
| #define | LPTIM_CFGR_CKFLT (3 << LPTIM_CFGR_CKFLT_SHIFT) |
| #define | LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT) |
| #define | LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT) |
| #define | LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT) |
| #define | LPTIM_CFGR_TRGFLT_SHIFT 6 |
| #define | LPTIM_CFGR_TRGFLT_MASK 0x03 |
| #define | LPTIM_CFGR_TRGFLT (3 << LPTIM_CFGR_TRGFLT_SHIFT) |
| #define | LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT) |
| #define | LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT) |
| #define | LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT) |
| #define | LPTIM_CFGR_PRESC_SHIFT 9 |
| #define | LPTIM_CFGR_PRESC_MASK 0x07 |
| #define | LPTIM_CFGR_PRESC (7 << LPTIM_CFGR_PRESC_SHIFT) |
| #define | LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT) |
| #define | LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT) |
| #define | LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT) |
| #define | LPTIM_CFGR_PRESC_8 (3 << LPTIM_CFGR_PRESC_SHIFT) |
| #define | LPTIM_CFGR_PRESC_16 (4 << LPTIM_CFGR_PRESC_SHIFT) |
| #define | LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT) |
| #define | LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT) |
| #define | LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT) |
| #define | LPTIM_CFGR_TRIGSEL_SHIFT 13 |
| #define | LPTIM_CFGR_TRIGSEL_MASK 0x07 |
| #define | LPTIM_CFGR_TRIGSEL (7 << LPTIM_CFGR_TRIGSEL_SHIFT) |
| #define | LPTIM_CFGR_TRIGSEL_EXT_TRIG0 (0 << LPTIM_CFGR_TRIGSEL_SHIFT) |
| #define | LPTIM_CFGR_TRIGSEL_EXT_TRIG1 (1 << LPTIM_CFGR_TRIGSEL_SHIFT) |
| #define | LPTIM_CFGR_TRIGSEL_EXT_TRIG2 (2 << LPTIM_CFGR_TRIGSEL_SHIFT) |
| #define | LPTIM_CFGR_TRIGSEL_EXT_TRIG3 (3 << LPTIM_CFGR_TRIGSEL_SHIFT) |
| #define | LPTIM_CFGR_TRIGSEL_EXT_TRIG4 (4 << LPTIM_CFGR_TRIGSEL_SHIFT) |
| #define | LPTIM_CFGR_TRIGSEL_EXT_TRIG6 (6 << LPTIM_CFGR_TRIGSEL_SHIFT) |
| #define | LPTIM_CFGR_TRIGSEL_EXT_TRIG7 (7 << LPTIM_CFGR_TRIGSEL_SHIFT) |
| #define | LPTIM_CFGR_TRIGEN_SHIFT 17 |
| #define | LPTIM_CFGR_TRIGEN_MASK 0x07 |
| #define | LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT) |
| #define | LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) |
| #define | LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT) |
| #define | LPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT) |
| #define | LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT) |
| #define | LPTIM_CFGR_TIMOUT (1 << 19) |
| TIMOUT: Timeout enable. More... | |
| #define | LPTIM_CFGR_WAVE (1 << 20) |
| WAVE: Waveform shape. More... | |
| #define | LPTIM_CFGR_WAVPOL (1 << 21) |
| WAVPOL: Waveform shape polarity. More... | |
| #define | LPTIM_CFGR_PRELOAD (1 << 22) |
| PRELOAD: Register update mode. More... | |
| #define | LPTIM_CFGR_COUNTMODE (1 << 23) |
| COUNTMODE: Counter mode enable. More... | |
| #define | LPTIM_CFGR_ENC (1 << 24) |
| ENC: Encoder mode enable. More... | |
| #define | LPTIM_CR_ENABLE (1 << 0) |
| ENABLE: LPTIM Enable. More... | |
| #define | LPTIM_CR_SNGSTRT (1 << 1) |
| SNGSTRT: Start in Single Mode. More... | |
| #define | LPTIM_CR_CNTSTRT (1 << 2) |
| CNGSTRT: Start in Continuous Mode. More... | |
Functions | |
| void | lptimer_enable (uint32_t timer_peripheral) |
| Enable lptimer. More... | |
| void | lptimer_disable (uint32_t timer_peripheral) |
| Disable lptimer. More... | |
| void | lptimer_start_counter (uint32_t timer_peripheral, uint32_t mode) |
| Start lptimer in a given mode. More... | |
| void | lptimer_set_counter (uint32_t timer_peripheral, uint16_t count) |
| Set lptimer Counter. More... | |
| uint16_t | lptimer_get_counter (uint32_t timer_peripheral) |
| Read lptimer Counter. More... | |
| void | lptimer_set_compare (uint32_t timer_peripheral, uint16_t compare_value) |
| Set lptimer counter Compare Value. More... | |
| void | lptimer_set_period (uint32_t lptimer_peripheral, uint16_t period_value) |
| Set lptimer period. More... | |
| void | lptimer_enable_preload (uint32_t lptimer_peripheral) |
| Enable lptimer Preload mode. More... | |
| void | lptimer_disable_preload (uint32_t lptimer_peripheral) |
| Disable lptimer Preload mode. More... | |
| void | lptimer_set_waveform_polarity_high (uint32_t lptimer_peripheral) |
| Set lptimer Waveform Output Polarity High. More... | |
| void | lptimer_set_waveform_polarity_low (uint32_t lptimer_peripheral) |
| Set lptimer Waveform Output Polarity Low. More... | |
| void | lptimer_set_prescaler (uint32_t timer_peripheral, uint32_t prescaler) |
| Set lptimer clock prescaler. More... | |
| void | lptimer_enable_trigger (uint32_t lptimer_peripheral, uint32_t trigen) |
| Enable lptimer External Trigger. More... | |
| void | lptimer_select_trigger_source (uint32_t lptimer_peripheral, uint32_t trigger_source) |
| Select lptimer Trigger Source. More... | |
| void | lptimer_set_internal_clock_source (uint32_t timer_peripheral) |
| Set lptimer Internal Clock source. More... | |
| void | lptimer_set_external_clock_source (uint32_t timer_peripheral) |
| Set lptimer External Clock source. More... | |
| void | lptimer_clear_flag (uint32_t timer_peripheral, uint32_t flag) |
| Clear lptimer Status Flag. More... | |
| bool | lptimer_get_flag (uint32_t timer_peripheral, uint32_t flag) |
| Read lptimer Status Flag. More... | |
| void | lptimer_enable_irq (uint32_t timer_peripheral, uint32_t irq) |
| Enable lptimer interrupts. More... | |
| void | lptimer_disable_irq (uint32_t timer_peripheral, uint32_t irq) |
| Disable lptimer Interrupts. More... | |
