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#define | LIBOPENCM3_STM32_COMMON_LTDC_COMMON_F47_H_ |
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#define | LTDC_SSCR (MMIO32(LTDC_BASE + 0x08)) |
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#define | LTDC_BPCR (MMIO32(LTDC_BASE + 0x0C)) |
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#define | LTDC_AWCR (MMIO32(LTDC_BASE + 0x10)) |
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#define | LTDC_TWCR (MMIO32(LTDC_BASE + 0x14)) |
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#define | LTDC_GCR (MMIO32(LTDC_BASE + 0x18)) |
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#define | LTDC_SRCR (MMIO32(LTDC_BASE + 0x24)) |
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#define | LTDC_BCCR (MMIO32(LTDC_BASE + 0x2C)) |
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#define | LTDC_IER (MMIO32(LTDC_BASE + 0x34)) |
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#define | LTDC_ISR (MMIO32(LTDC_BASE + 0x38)) |
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#define | LTDC_ICR (MMIO32(LTDC_BASE + 0x3C)) |
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#define | LTDC_LIPCR (MMIO32(LTDC_BASE + 0x40)) |
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#define | LTDC_CPSR (MMIO32(LTDC_BASE + 0x44)) |
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#define | LTDC_CDSR (MMIO32(LTDC_BASE + 0x48)) |
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#define | LTDC_LxCR(x) (MMIO32(LTDC_BASE + 0x84 + 0x80 * ((x) - 1))) |
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#define | LTDC_L1CR LTDC_LxCR(LTDC_LAYER_1) |
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#define | LTDC_L2CR LTDC_LxCR(LTDC_LAYER_2) |
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#define | LTDC_LxWHPCR(x) (MMIO32(LTDC_BASE + 0x88 + 0x80 * ((x) - 1))) |
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#define | LTDC_L1WHPCR LTDC_LxWHPCR(LTDC_LAYER_1) |
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#define | LTDC_L2WHPCR LTDC_LxWHPCR(LTDC_LAYER_2) |
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#define | LTDC_LxWVPCR(x) (MMIO32(LTDC_BASE + 0x8C + 0x80 * ((x) - 1))) |
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#define | LTDC_L1WVPCR LTDC_LxWVPCR(LTDC_LAYER_1) |
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#define | LTDC_L2WVPCR LTDC_LxWVPCR(LTDC_LAYER_2) |
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#define | LTDC_LxCKCR(x) (MMIO32(LTDC_BASE + 0x90 + 0x80 * ((x) - 1))) |
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#define | LTDC_L1CKCR LTDC_LxCKCR(LTDC_LAYER_1) |
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#define | LTDC_L2CKCR LTDC_LxCKCR(LTDC_LAYER_2) |
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#define | LTDC_LxPFCR(x) (MMIO32(LTDC_BASE + 0x94 + 0x80 * ((x) - 1))) |
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#define | LTDC_L1PFCR LTDC_LxPFCR(LTDC_LAYER_1) |
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#define | LTDC_L2PFCR LTDC_LxPFCR(LTDC_LAYER_2) |
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#define | LTDC_LxCACR(x) (MMIO32(LTDC_BASE + 0x98 + 0x80 * ((x) - 1))) |
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#define | LTDC_L1CACR LTDC_LxCACR(LTDC_LAYER_1) |
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#define | LTDC_L2CACR LTDC_LxCACR(LTDC_LAYER_2) |
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#define | LTDC_LxDCCR(x) (MMIO32(LTDC_BASE + 0x9C + 0x80 * ((x) - 1))) |
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#define | LTDC_L1DCCR LTDC_LxDCCR(LTDC_LAYER_1) |
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#define | LTDC_L2DCCR LTDC_LxDCCR(LTDC_LAYER_2) |
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#define | LTDC_LxBFCR(x) (MMIO32(LTDC_BASE + 0xA0 + 0x80 * ((x) - 1))) |
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#define | LTDC_L1BFCR LTDC_LxBFCR(LTDC_LAYER_1) |
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#define | LTDC_L2BFCR LTDC_LxBFCR(LTDC_LAYER_2) |
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#define | LTDC_LxCFBAR(x) (MMIO32(LTDC_BASE + 0xAC + 0x80 * ((x) - 1))) |
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#define | LTDC_L1CFBAR LTDC_LxCFBAR(LTDC_LAYER_1) |
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#define | LTDC_L2CFBAR LTDC_LxCFBAR(LTDC_LAYER_2) |
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#define | LTDC_LxCFBLR(x) (MMIO32(LTDC_BASE + 0xB0 + 0x80 * ((x) - 1))) |
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#define | LTDC_L1CFBLR LTDC_LxCFBLR(LTDC_LAYER_1) |
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#define | LTDC_L2CFBLR LTDC_LxCFBLR(LTDC_LAYER_2) |
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#define | LTDC_LxCFBLNR(x) (MMIO32(LTDC_BASE + 0xB4 + 0x80 * ((x) - 1))) |
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#define | LTDC_L1CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_1) |
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#define | LTDC_L2CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_2) |
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#define | LTDC_LxCLUTWR(x) (MMIO32(LTDC_BASE + 0xC4 + 0x80 * ((x) - 1))) |
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#define | LTDC_L1CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_1) |
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#define | LTDC_L2CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_2) |
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#define | LTDC_LAYER_1 1 |
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#define | LTDC_LAYER_2 2 |
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#define | LTDC_SSCR_HSW_SHIFT 16 |
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#define | LTDC_SSCR_HSW_MASK 0xfff |
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#define | LTDC_SSCR_VSH_SHIFT 0 |
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#define | LTDC_SSCR_VSH_MASK 0x7ff |
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#define | LTDC_BPCR_AHBP_SHIFT 16 |
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#define | LTDC_BPCR_AHBP_MASK 0xfff |
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#define | LTDC_BPCR_AVBP_SHIFT 0 |
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#define | LTDC_BPCR_AVBP_MASK 0x7FF |
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#define | LTDC_AWCR_AAW_SHIFT 16 |
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#define | LTDC_AWCR_AAW_MASK 0xfff |
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#define | LTDC_AWCR_AAH_SHIFT 0 |
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#define | LTDC_AWCR_AAH_MASK 0x7ff |
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#define | LTDC_TWCR_TOTALW_SHIFT 16 |
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#define | LTDC_TWCR_TOTALW_MASK 0xfff |
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#define | LTDC_TWCR_TOTALH_SHIFT 0 |
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#define | LTDC_TWCR_TOTALH_MASK 0x7ff |
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#define | LTDC_GCR_LTDC_ENABLE (1<<0) |
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#define | LTDC_GCR_DITHER_ENABLE (1<<16) |
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#define | LTDC_GCR_PCPOL_ACTIVE_LOW (0<<28) |
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#define | LTDC_GCR_PCPOL_ACTIVE_HIGH (1<<28) |
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#define | LTDC_GCR_DEPOL_ACTIVE_LOW (0<<29) |
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#define | LTDC_GCR_DEPOL_ACTIVE_HIGH (1<<29) |
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#define | LTDC_GCR_VSPOL_ACTIVE_LOW (0<<30) |
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#define | LTDC_GCR_VSPOL_ACTIVE_HIGH (1<<30) |
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#define | LTDC_GCR_HSPOL_ACTIVE_LOW (0<<31) |
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#define | LTDC_GCR_HSPOL_ACTIVE_HIGH (1<<31) |
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#define | LTDC_GCR_HSPOL (1 << 31) |
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#define | LTDC_GCR_VSPOL (1 << 30) |
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#define | LTDC_GCR_DEPOL (1 << 29) |
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#define | LTDC_GCR_PCPOL (1 << 28) |
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#define | LTDC_GCR_DITHER (1 << 16) |
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#define | LTDC_GCR_LTDCEN (1 << 0) |
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#define | LTDC_SRCR_VBR (1 << 1) |
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#define | LTDC_SRCR_IMR (1 << 0) |
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#define | LTDC_SRCR_RELOAD_IMR (1<<0) |
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#define | LTDC_SRCR_RELOAD_VBR (1<<1) |
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#define | LTDC_IER_RRIE (1 << 3) |
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#define | LTDC_IER_TERRIE (1 << 2) |
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#define | LTDC_IER_FUIE (1 << 1) |
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#define | LTDC_IER_LIE (1 << 0) |
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#define | LTDC_ISR_RRIF (1 << 3) |
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#define | LTDC_ISR_TERRIF (1 << 2) |
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#define | LTDC_ISR_FUIF (1 << 1) |
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#define | LTDC_ISR_LIF (1 << 0) |
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#define | LTDC_ICR_CRRIF (1 << 3) |
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#define | LTDC_ICR_CTERRIF (1 << 2) |
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#define | LTDC_ICR_CFUIF (1 << 1) |
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#define | LTDC_ICR_CLIF (1 << 0) |
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#define | LTDC_LIPCR_LIPOS_SHIFT 0 |
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#define | LTDC_LIPCR_LIPOS_MASK 0x7ff |
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#define | LTDC_CPSR_CXPOS_SHIFT 16 |
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#define | LTDC_CPSR_CXPOS_MASK 0xffff |
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#define | LTDC_CPSR_CYPOS_SHIFT 0 |
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#define | LTDC_CPSR_CYPOS_MASK 0xffff |
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#define | LTDC_CDSR_VDES (1<<0) |
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#define | LTDC_CDSR_HDES (1<<1) |
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#define | LTDC_CDSR_VSYNCS (1<<2) |
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#define | LTDC_CDSR_HSYNCS (1<<3) |
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#define | LTDC_LxCR_LAYER_ENABLE (1<<0) |
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#define | LTDC_LxCR_COLKEY_ENABLE (1<<1) |
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#define | LTDC_LxCR_COLTAB_ENABLE (1<<4) |
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#define | LTDC_LxWHPCR_WHSPPOS_SHIFT 16 |
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#define | LTDC_LxWHPCR_WHSPPOS_MASK 0xfff |
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#define | LTDC_LxWHPCR_WHSTPOS_SHIFT 0 |
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#define | LTDC_LxWHPCR_WHSTPOS_MASK 0xfff |
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#define | LTDC_LxWVPCR_WVSPPOS_SHIFT 16 |
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#define | LTDC_LxWVPCR_WVSPPOS_MASK 0x7ff |
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#define | LTDC_LxWVPCR_WVSTPOS_SHIFT 0 |
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#define | LTDC_LxWVPCR_WVSTPOS_MASK 0x7ff |
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#define | LTDC_LxCKCR_CKRED_SHIFT 16 |
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#define | LTDC_LxCKCR_CKRED_MASK 0xff |
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#define | LTDC_LxCKCR_CKGREEN_SHIFT 16 |
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#define | LTDC_LxCKCR_CKGREEN_MASK 0xff |
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#define | LTDC_LxCKCR_CKBLUE_SHIFT 16 |
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#define | LTDC_LxCKCR_CKBLUE_MASK 0xff |
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#define | LTDC_LxPFCR_ARGB8888 (0b000) |
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#define | LTDC_LxPFCR_RGB888 (0b001) |
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#define | LTDC_LxPFCR_RGB565 (0b010) |
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#define | LTDC_LxPFCR_ARGB1555 (0b011) |
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#define | LTDC_LxPFCR_ARGB4444 (0b100) |
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#define | LTDC_LxPFCR_L8 (0b101) |
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#define | LTDC_LxPFCR_AL44 (0b110) |
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#define | LTDC_LxPFCR_AL88 (0b111) |
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#define | LTDC_LxCACR_CONSTA_SHIFT 0 |
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#define | LTDC_LxCACR_CONSTA_MASK 0xff |
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#define | LTDC_LxDCCR_DCALPHA_SHIFT 24 |
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#define | LTDC_LxDCCR_DCALPHA_MASK 1 |
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#define | LTDC_LxDCCR_DCRED_SHIFT 16 |
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#define | LTDC_LxDCCR_DCRED_MASK 1 |
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#define | LTDC_LxDCCR_DCGREEN_SHIFT 8 |
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#define | LTDC_LxDCCR_DCGREEN_MASK 1 |
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#define | LTDC_LxDCCR_DCBLUE_SHIFT 0 |
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#define | LTDC_LxDCCR_DCBLUE_MASK 1 |
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#define | LTDC_LxBFCR_BF1_CONST_ALPHA (0b100) |
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#define | LTDC_LxBFCR_BF1_PIXEL_ALPHA_x_CONST_ALPHA (0b110) |
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#define | LTDC_LxBFCR_BF2_CONST_ALPHA (0b101) |
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#define | LTDC_LxBFCR_BF2_PIXEL_ALPHA_x_CONST_ALPHA (0b111) |
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#define | LTDC_LxCFBAR_CFBAR_SHIFT 0 |
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#define | LTDC_LxCFBAR_CFBAR_MASK 0xffffffff |
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#define | LTDC_LxCFBLR_CFBP_SHIFT 16 |
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#define | LTDC_LxCFBLR_CFBP_MASK 0x1fff |
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#define | LTDC_LxCFBLR_CFBLL_SHIFT 0 |
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#define | LTDC_LxCFBLR_CFBLL_MASK 0x1fff |
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#define | LTDC_LxCFBLNR_CFBLNBR_SHIFT 0 |
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#define | LTDC_LxCFBLNR_CFBLNBR_MASK 0x3ff |
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#define | LTDC_LxCLUTWR_CLUTADD_SHIFT 24 |
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#define | LTDC_LxCLUTWR_CLUTADD_MASK 0xff |
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#define | LTDC_LxCLUTWR_RED_SHIFT 16 |
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#define | LTDC_LxCLUTWR_RED_MASK 0xff |
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#define | LTDC_LxCLUTWR_GREEN_SHIFT 8 |
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#define | LTDC_LxCLUTWR_GREEN_MASK 0xff |
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#define | LTDC_LxCLUTWR_BLUE_SHIFT 0 |
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#define | LTDC_LxCLUTWR_BLUE_MASK 0xff |
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