libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
usb_lm4f.c
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20/**
21 * @defgroup usb_file USB
22 *
23 * @ingroup LM4Fxx
24 *
25 * @author @htmlonly &copy; @endhtmlonly 2013
26 * Alexandru Gagniuc <mr.nuke.me@gmail.com>
27 *
28 * \brief <b>libopencm3 LM4F Universal Serial Bus controller </b>
29 *
30 * The LM4F USB driver is integrated with the libopencm3 USB stack. You should
31 * use the generic stack.
32 *
33 * To use this driver, tell the linker to look for it:
34 * @code{.c}
35 * extern usbd_driver lm4f_usb_driver;
36 * @endcode
37 *
38 * And pass this driver as an argument when initializing the USB stack:
39 * @code{.c}
40 * usbd_device *usbd_dev;
41 * usbd_dev = usbd_init(&lm4f_usb_driver, ...);
42 * @endcode
43 *
44 * <b>Polling or interrupt-driven? </b>
45 *
46 * The LM4F USB driver will work fine regardless of whether it is called from an
47 * interrupt service routine, or from the main program loop.
48 *
49 * Polling USB from the main loop requires calling @ref usbd_poll() from the
50 * main program loop.
51 * For example:
52 * @code{.c}
53 * // Main program loop
54 * while(1) {
55 * usbd_poll(usb_dev);
56 * do_other_stuff();
57 * ...
58 * @endcode
59 *
60 * Running @ref usbd_poll() from an interrupt has the advantage that it is only
61 * called when needed, saving CPU cycles for the main program.
62 *
63 * RESET, DISCON, RESUME, and SUSPEND interrupts must be enabled, along with the
64 * interrupts for any endpoint that is used. The EP0_TX interrupt must be
65 * enabled for the control endpoint to function correctly.
66 * For example, if EP1IN and EP2OUT are used, then the EP0_TX, EP1_TX, and
67 * EP2_RX interrupts should be enabled:
68 * @code{.c}
69 * // Enable USB interrupts for EP0, EP1IN, and EP2OUT
70 * ints = USB_INT_RESET | USB_INT_DISCON | USB_INT_RESUME |
71 * USB_INT_SUSPEND;
72 * usb_enable_interrupts(ints, USB_EP2_INT, USB_EP0_INT | USB_EP1_INT);
73 * // Route the interrupts through the NVIC
74 * nvic_enable_irq(NVIC_USB0_IRQ);
75 * @endcode
76 *
77 * The USB ISR only has to call @ref usbd_poll().
78 *
79 * @code{.c}
80 * void usb0_isr(void)
81 * {
82 * usbd_poll(usb_dev);
83 * }
84 * @endcode
85 * @{
86 */
87
88/*
89 * TODO list:
90 *
91 * 1) Driver works by reading and writing to the FIFOs one byte at a time. It
92 * has no knowledge of DMA.
93 * 2) Double-buffering is supported. How can we take advantage of it to speed
94 * up endpoint transfers.
95 * 3) No benchmarks as to the endpoint's performance has been done.
96 */
97/*
98 * The following are resources referenced in comments:
99 * [1] http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/238784.aspx
100 */
101
103#include <libopencm3/lm4f/usb.h>
104#include <libopencm3/lm4f/rcc.h>
105#include <libopencm3/usb/usbd.h>
106#include "../../lib/usb/usb_private.h"
107
108#include <stdbool.h>
109
110
111#define MAX_FIFO_RAM (4 * 1024)
112
113const struct _usbd_driver lm4f_usb_driver;
114
115/**
116 * \brief Enable Specific USB Interrupts
117 *
118 * Enable any combination of interrupts. Interrupts may be OR'ed together to
119 * enable them with one call. For example, to enable both the RESUME and RESET
120 * interrupts, pass (USB_INT_RESUME | USB_INT_RESET)
121 *
122 * Note that the NVIC must be enabled and properly configured for the interrupt
123 * to be routed to the CPU.
124 *
125 * @param[in] ints Interrupts which to enable. Any combination of interrupts may
126 * be specified by OR'ing then together
127 * @param[in] rx_ints Endpoints for which to generate an interrupt when a packet
128 * packet is received.
129 * @param[in] tx_ints Endpoints for which to generate an interrupt when a packet
130 * packet is finished transmitting.
131 */
133 enum usb_ep_interrupt rx_ints,
134 enum usb_ep_interrupt tx_ints)
135{
136 USB_IE |= ints;
137 USB_RXIE |= rx_ints;
138 USB_TXIE |= tx_ints;
139}
140
141/**
142 * \brief Disable Specific USB Interrupts
143 *
144 * Disable any combination of interrupts. Interrupts may be OR'ed together to
145 * enable them with one call. For example, to disable both the RESUME and RESET
146 * interrupts, pass (USB_INT_RESUME | USB_INT_RESET)
147 *
148 * Note that the NVIC must be enabled and properly configured for the interrupt
149 * to be routed to the CPU.
150 *
151 * @param[in] ints Interrupts which to disable. Any combination of interrupts
152 * may be specified by OR'ing then together
153 * @param[in] rx_ints Endpoints for which to stop generating an interrupt when a
154 * packet packet is received.
155 * @param[in] tx_ints Endpoints for which to stop generating an interrupt when a
156 * packet packet is finished transmitting.
157 */
159 enum usb_ep_interrupt rx_ints,
160 enum usb_ep_interrupt tx_ints)
161{
162 USB_IE &= ~ints;
163 USB_RXIE &= ~rx_ints;
164 USB_TXIE &= ~tx_ints;
165}
166
167/**
168 * @cond private
169 */
170static inline void lm4f_usb_soft_disconnect(void)
171{
172 USB_POWER &= ~USB_POWER_SOFTCONN;
173}
174
175static inline void lm4f_usb_soft_connect(void)
176{
178}
179
180static void lm4f_set_address(usbd_device *usbd_dev, uint8_t addr)
181{
182 (void)usbd_dev;
183
185}
186
187static void lm4f_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
188 uint16_t max_size,
189 void (*callback) (usbd_device *usbd_dev, uint8_t ep))
190{
191 (void)usbd_dev;
192 (void)type;
193
194 uint8_t reg8;
195 uint16_t fifo_size;
196
197 const bool dir_tx = addr & 0x80;
198 const uint8_t ep = addr & 0x0f;
199
200 /*
201 * We do not mess with the maximum packet size, but we can only allocate
202 * the FIFO in power-of-two increments.
203 */
204 if (max_size > 1024) {
205 fifo_size = 2048;
207 } else if (max_size > 512) {
208 fifo_size = 1024;
210 } else if (max_size > 256) {
211 fifo_size = 512;
212 reg8 = USB_FIFOSZ_SIZE_512;
213 } else if (max_size > 128) {
214 fifo_size = 256;
215 reg8 = USB_FIFOSZ_SIZE_256;
216 } else if (max_size > 64) {
217 fifo_size = 128;
218 reg8 = USB_FIFOSZ_SIZE_128;
219 } else if (max_size > 32) {
220 fifo_size = 64;
221 reg8 = USB_FIFOSZ_SIZE_64;
222 } else if (max_size > 16) {
223 fifo_size = 32;
224 reg8 = USB_FIFOSZ_SIZE_32;
225 } else if (max_size > 8) {
226 fifo_size = 16;
227 reg8 = USB_FIFOSZ_SIZE_16;
228 } else {
229 fifo_size = 8;
230 reg8 = USB_FIFOSZ_SIZE_8;
231 }
232
233 /* Endpoint 0 is more special */
234 if (addr == 0) {
235 USB_EPIDX = 0;
236
237 if (reg8 > USB_FIFOSZ_SIZE_64) {
238 reg8 = USB_FIFOSZ_SIZE_64;
239 }
240
241 /* The RX and TX FIFOs are shared for EP0 */
242 USB_RXFIFOSZ = reg8;
243 USB_TXFIFOSZ = reg8;
244
245 /*
246 * Regardless of how much we allocate, the first 64 bytes
247 * are always reserved for EP0.
248 */
249 usbd_dev->fifo_mem_top_ep0 = 64;
250 return;
251 }
252
253 /* Are we out of FIFO space? */
254 if (usbd_dev->fifo_mem_top + fifo_size > MAX_FIFO_RAM) {
255 return;
256 }
257
258 USB_EPIDX = addr & USB_EPIDX_MASK;
259
260 /* FIXME: What about double buffering? */
261 if (dir_tx) {
262 USB_TXMAXP(ep) = max_size;
263 USB_TXFIFOSZ = reg8;
264 USB_TXFIFOADD = ((usbd_dev->fifo_mem_top) >> 3);
265 if (callback) {
266 usbd_dev->user_callback_ctr[ep][USB_TRANSACTION_IN] =
267 (void *)callback;
268 }
269 if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) {
271 } else {
272 USB_TXCSRH(ep) &= ~USB_TXCSRH_ISO;
273 }
274 } else {
275 USB_RXMAXP(ep) = max_size;
276 USB_RXFIFOSZ = reg8;
277 USB_RXFIFOADD = ((usbd_dev->fifo_mem_top) >> 3);
278 if (callback) {
279 usbd_dev->user_callback_ctr[ep][USB_TRANSACTION_OUT] =
280 (void *)callback;
281 }
282 if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) {
284 } else {
285 USB_RXCSRH(ep) &= ~USB_RXCSRH_ISO;
286 }
287 }
288
289 usbd_dev->fifo_mem_top += fifo_size;
290}
291
292static void lm4f_endpoints_reset(usbd_device *usbd_dev)
293{
294 /*
295 * The core resets the endpoints automatically on reset.
296 * The first 64 bytes are always reserved for EP0
297 */
298 usbd_dev->fifo_mem_top = 64;
299}
300
301static void lm4f_ep_stall_set(usbd_device *usbd_dev, uint8_t addr,
302 uint8_t stall)
303{
304 (void)usbd_dev;
305
306 const uint8_t ep = addr & 0x0f;
307 const bool dir_tx = addr & 0x80;
308
309 if (ep == 0) {
310 if (stall) {
312 } else {
313 USB_CSRL0 &= ~USB_CSRL0_STALL;
314 }
315 return;
316 }
317
318 if (dir_tx) {
319 if (stall) {
321 } else {
323 }
324 } else {
325 if (stall) {
327 } else {
329 }
330 }
331}
332
333static uint8_t lm4f_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
334{
335 (void)usbd_dev;
336
337 const uint8_t ep = addr & 0x0f;
338 const bool dir_tx = addr & 0x80;
339
340 if (ep == 0) {
342 }
343
344 if (dir_tx) {
345 return USB_TXCSRL(ep) & USB_TXCSRL_STALLED;
346 } else {
347 return USB_RXCSRL(ep) & USB_RXCSRL_STALLED;
348 }
349}
350
351static void lm4f_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
352{
353 (void)usbd_dev;
354 (void)addr;
355 (void)nak;
356
357 /* NAK's are handled automatically by hardware. Move along. */
358}
359
360static uint16_t lm4f_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
361 const void *buf, uint16_t len)
362{
363 const uint8_t ep = addr & 0xf;
364 uint16_t i;
365
366 (void)usbd_dev;
367
368 /* Don't touch the FIFO if there is still a packet being transmitted */
369 if (ep == 0 && (USB_CSRL0 & USB_CSRL0_TXRDY)) {
370 return 0;
371 } else if (USB_TXCSRL(ep) & USB_TXCSRL_TXRDY) {
372 return 0;
373 }
374
375 /*
376 * We don't need to worry about buf not being aligned. If it's not,
377 * the reads are downgraded to 8-bit in hardware. We lose a bit of
378 * performance, but we don't crash.
379 */
380 for (i = 0; i < (len & ~0x3); i += 4) {
381 USB_FIFO32(ep) = *((uint32_t *)(buf + i));
382 }
383 if (len & 0x2) {
384 USB_FIFO16(ep) = *((uint16_t *)(buf + i));
385 i += 2;
386 }
387 if (len & 0x1) {
388 USB_FIFO8(ep) = *((uint8_t *)(buf + i));
389 i += 1;
390 }
391
392 if (ep == 0) {
393 /*
394 * EP0 is very special. We should only set DATAEND when we
395 * transmit the last packet in the transaction. A transaction
396 * that is a multiple of 64 bytes will end with a zero-length
397 * packet, so our check is sane.
398 */
399 if (len != 64) {
401 } else {
403 }
404 } else {
406 }
407
408 return i;
409}
410
411static uint16_t lm4f_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
412 void *buf, uint16_t len)
413{
414 (void)usbd_dev;
415
416 uint16_t rlen;
417 uint8_t ep = addr & 0xf;
418
419 uint16_t fifoin = USB_RXCOUNT(ep);
420
421 rlen = (fifoin > len) ? len : fifoin;
422
423 /*
424 * We don't need to worry about buf not being aligned. If it's not,
425 * the writes are downgraded to 8-bit in hardware. We lose a bit of
426 * performance, but we don't crash.
427 */
428 for (len = 0; len < (rlen & ~0x3); len += 4) {
429 *((uint32_t *)(buf + len)) = USB_FIFO32(ep);
430 }
431 if (rlen & 0x2) {
432 *((uint16_t *)(buf + len)) = USB_FIFO16(ep);
433 len += 2;
434 }
435 if (rlen & 0x1) {
436 *((uint8_t *)(buf + len)) = USB_FIFO8(ep);
437 }
438
439 if (ep == 0) {
440 /*
441 * Clear RXRDY
442 * Datasheet says that DATAEND must also be set when clearing
443 * RXRDY. We don't do that. If did this when transmitting a
444 * packet larger than 64 bytes, only the first 64 bytes would
445 * be transmitted, followed by a handshake. The host would only
446 * get 64 bytes, seeing it as a malformed packet. Usually, we
447 * would not get past enumeration.
448 */
450
451 } else {
452 USB_RXCSRL(ep) &= ~USB_RXCSRL_RXRDY;
453 }
454
455 return rlen;
456}
457
458static void lm4f_poll(usbd_device *usbd_dev)
459{
460 void (*tx_cb)(usbd_device *usbd_dev, uint8_t ea);
461 void (*rx_cb)(usbd_device *usbd_dev, uint8_t ea);
462 int i;
463
464 /*
465 * The initial state of these registers might change, as we process the
466 * interrupt, but we need the initial state in order to decide how to
467 * handle events.
468 */
469 const uint8_t usb_is = USB_IS;
470 const uint8_t usb_rxis = USB_RXIS;
471 const uint8_t usb_txis = USB_TXIS;
472 const uint8_t usb_csrl0 = USB_CSRL0;
473
474 if ((usb_is & USB_IM_SUSPEND) && (usbd_dev->user_callback_suspend)) {
475 usbd_dev->user_callback_suspend();
476 }
477
478 if ((usb_is & USB_IM_RESUME) && (usbd_dev->user_callback_resume)) {
479 usbd_dev->user_callback_resume();
480 }
481
482 if (usb_is & USB_IM_RESET) {
483 _usbd_reset(usbd_dev);
484 }
485
486 if ((usb_is & USB_IM_SOF) && (usbd_dev->user_callback_sof)) {
487 usbd_dev->user_callback_sof();
488 }
489
490 if (usb_txis & USB_EP0) {
491 /*
492 * The EP0 bit in USB_TXIS is special. It tells us that
493 * something happened on EP0, but does not tell us what. This
494 * bit does not necessarily tell us that a packet was
495 * transmitted, so we have to go through all the possibilities
496 * to figure out exactly what did. Only after we've exhausted
497 * all other possibilities, can we assume this is a EPO
498 * "transmit complete" interrupt.
499 */
500 if (usb_csrl0 & USB_CSRL0_RXRDY) {
501 enum _usbd_transaction type;
502 type = (usbd_dev->control_state.state != DATA_OUT &&
503 usbd_dev->control_state.state != LAST_DATA_OUT)
504 ? USB_TRANSACTION_SETUP :
505 USB_TRANSACTION_OUT;
506 if (type == USB_TRANSACTION_SETUP) {
507 lm4f_ep_read_packet(usbd_dev, 0, &usbd_dev->control_state.req, 8);
508 }
509 if (usbd_dev->user_callback_ctr[0][type]) {
510 usbd_dev->
511 user_callback_ctr[0][type](usbd_dev, 0);
512 }
513
514
515 } else {
516 tx_cb = usbd_dev->user_callback_ctr[0]
517 [USB_TRANSACTION_IN];
518
519 /*
520 * EP0 bit in TXIS is set not only when a packet is
521 * finished transmitting, but also when RXRDY is set, or
522 * when we set TXRDY to transmit a packet. If any of
523 * those are the case, then we do not want to call our
524 * IN callback, since the state machine will be in the
525 * wrong state, and we'll just stall our control
526 * endpoint.
527 * In fact, the only way to know if it's time to call
528 * our TX callback is to know what to expect. The
529 * hardware does not tell us what sort of transaction
530 * this is. We need to work with the state machine to
531 * figure it all out. See [1] for details.
532 */
533 if ((usbd_dev->control_state.state != DATA_IN) &&
534 (usbd_dev->control_state.state != LAST_DATA_IN) &&
535 (usbd_dev->control_state.state != STATUS_IN)) {
536 return;
537 }
538
539 if (tx_cb) {
540 tx_cb(usbd_dev, 0);
541 }
542 }
543 }
544
545 /* See which interrupt occurred */
546 for (i = 1; i < 8; i++) {
547 tx_cb = usbd_dev->user_callback_ctr[i][USB_TRANSACTION_IN];
548 rx_cb = usbd_dev->user_callback_ctr[i][USB_TRANSACTION_OUT];
549
550 if ((usb_txis & (1 << i)) && tx_cb) {
551 tx_cb(usbd_dev, i);
552 }
553
554 if ((usb_rxis & (1 << i)) && rx_cb) {
555 rx_cb(usbd_dev, i);
556 }
557 }
558
559
560}
561
562static void lm4f_disconnect(usbd_device *usbd_dev, bool disconnected)
563{
564 (void)usbd_dev;
565
566 /*
567 * This is all it takes:
568 * usbd_disconnect(dev, 1) followed by usbd_disconnect(dev, 0)
569 * causes the device to re-enumerate and re-configure properly.
570 */
571 if (disconnected) {
572 lm4f_usb_soft_disconnect();
573 } else {
574 lm4f_usb_soft_connect();
575 }
576}
577
578/*
579 * A static struct works as long as we have only one USB peripheral. If we
580 * meet LM4Fs with more than one USB, then we need to rework this approach.
581 */
582static struct _usbd_device usbd_dev;
583
584/** Initialize the USB device controller hardware of the LM4F. */
585static usbd_device *lm4f_usbd_init(void)
586{
587 int i;
588
589 /* Start the USB clock */
591 /* Enable the USB PLL interrupts - used to assert PLL lock */
594
595 /* Make sure we're disconnected. We'll reconnect later */
596 lm4f_usb_soft_disconnect();
597
598 /* Software reset USB */
599 SYSCTL_SRUSB = 1;
600 for (i = 0; i < 1000; i++) {
601 __asm__("nop");
602 }
603 SYSCTL_SRUSB = 0;
604
605 /*
606 * Wait for the PLL to lock before soft connecting
607 * This will result in a deadlock if the system clock is not setup
608 * correctly (clock from main oscillator).
609 */
610 /* Wait for it */
611 i = 0;
612 while ((SYSCTL_RIS & SYSCTL_RIS_USBPLLLRIS) == 0) {
613 i++;
614 if (i > 0xffff) {
615 return 0;
616 }
617 }
618
619 /* Now connect to USB */
620 lm4f_usb_soft_connect();
621
622 /* No FIFO allocated yet, but the first 64 bytes are still reserved */
623 usbd_dev.fifo_mem_top = 64;
624
625 return &usbd_dev;
626}
627
628/* What is this thing even good for */
629#define RX_FIFO_SIZE 512
630
631const struct _usbd_driver lm4f_usb_driver = {
632 .init = lm4f_usbd_init,
633 .set_address = lm4f_set_address,
634 .ep_setup = lm4f_ep_setup,
635 .ep_reset = lm4f_endpoints_reset,
636 .ep_stall_set = lm4f_ep_stall_set,
637 .ep_stall_get = lm4f_ep_stall_get,
638 .ep_nak_set = lm4f_ep_nak_set,
639 .ep_write_packet = lm4f_ep_write_packet,
640 .ep_read_packet = lm4f_ep_read_packet,
641 .poll = lm4f_poll,
642 .disconnect = lm4f_disconnect,
643 .base_address = USB_BASE,
644 .set_address_before_status = false,
645 .rx_fifo_size = RX_FIFO_SIZE,
646};
647/**
648 * @endcond
649 */
650
651/**
652 * @}
653 */
void rcc_usb_pll_on(void)
Power up the USB PLL.
Definition: rcc.c:325
#define SYSCTL_IMC_USBPLLLIM
USB PLL Lock Raw Interrupt Status.
#define SYSCTL_RIS
Definition: systemcontrol.h:52
void periph_clock_enable(enum lm4f_clken periph)
Enable the clock source for the peripheral.
Definition: systemcontrol.c:27
#define SYSCTL_IMC
Definition: systemcontrol.h:54
#define SYSCTL_SRUSB
#define SYSCTL_IMC_PLLLIM
PLL Lock Raw Interrupt Status.
#define SYSCTL_RIS_USBPLLLRIS
USB PLL Lock Raw Interrupt Status.
@ RCC_USB0
#define USB_TXIS
Definition: usb.h:55
usb_interrupt
Definition: usb.h:388
#define USB_RXCSRL_STALL
Send Stall.
Definition: usb.h:325
#define USB_RXCSRH(n)
Definition: usb.h:132
#define USB_FIFOSZ_SIZE_64
Definition: usb.h:241
#define USB_TXCSRH(n)
Definition: usb.h:123
#define USB_FADDR_FUNCADDR_MASK
Function Address.
Definition: usb.h:163
#define USB_FIFO8(n)
Definition: usb.h:82
#define USB_RXCOUNT(n)
Definition: usb.h:135
#define USB_CSRL0_RXRDYC
RXRDY Clear.
Definition: usb.h:263
#define USB_FIFOSZ_SIZE_256
Definition: usb.h:243
#define USB_TXCSRL_TXRDY
Transmit Packet Ready.
Definition: usb.h:299
#define USB_FIFOSZ_SIZE_8
Definition: usb.h:238
#define USB_IM_RESUME
RESUME signaling detected.
Definition: usb.h:207
#define USB_RXCSRL(n)
Definition: usb.h:129
#define USB_EPIDX
Definition: usb.h:76
#define USB_RXIE
Definition: usb.h:64
#define USB_FIFO32(n)
Definition: usb.h:84
#define USB_RXCSRL_STALLED
Endpoint Stalled.
Definition: usb.h:323
#define USB_CSRL0_TXRDY
Transmit Packet Ready.
Definition: usb.h:273
#define USB_CSRL0
Definition: usb.h:108
#define USB_FIFO16(n)
Definition: usb.h:83
#define USB_EP0
Definition: usb.h:193
#define USB_TXIE
Definition: usb.h:61
#define USB_RXMAXP(n)
Definition: usb.h:126
#define USB_FIFOSZ_SIZE_32
Definition: usb.h:240
#define USB_RXCSRH_ISO
Isochronous transfers.
Definition: usb.h:343
#define USB_POWER_SOFTCONN
Soft Connect/Disconnect.
Definition: usb.h:171
#define USB_TXFIFOADD
Definition: usb.h:93
#define USB_IM_RESET
RESET signaling detected.
Definition: usb.h:205
#define USB_FIFOSZ_SIZE_16
Definition: usb.h:239
#define USB_IM_SOF
Start of frame.
Definition: usb.h:203
#define USB_CSRL0_DATAEND
Data End.
Definition: usb.h:269
#define USB_CSRL0_STALLED
Endpoint Stalled.
Definition: usb.h:271
#define USB_FIFOSZ_SIZE_512
Definition: usb.h:244
#define USB_CSRL0_RXRDY
Receive Packet Ready.
Definition: usb.h:275
#define USB_TXCSRH_ISO
Isochronous transfers.
Definition: usb.h:307
#define USB_CSRL0_STALL
Send Stall.
Definition: usb.h:265
#define USB_IE
Definition: usb.h:70
#define USB_FIFOSZ_SIZE_128
Definition: usb.h:242
#define USB_TXCSRL_STALLED
Endpoint Stalled.
Definition: usb.h:289
#define USB_IM_SUSPEND
SUSPEND signaling detected.
Definition: usb.h:209
#define USB_EPIDX_MASK
Endpoint Index.
Definition: usb.h:221
#define USB_TXCSRL_STALL
Send Stall.
Definition: usb.h:291
#define USB_FIFOSZ_SIZE_1024
Definition: usb.h:245
#define USB_FADDR
Definition: usb.h:49
#define USB_RXFIFOADD
Definition: usb.h:96
#define USB_RXFIFOSZ
Definition: usb.h:90
#define USB_POWER
Definition: usb.h:52
#define USB_TXMAXP(n)
Definition: usb.h:117
usb_ep_interrupt
Definition: usb.h:396
#define USB_RXIS
Definition: usb.h:58
#define USB_TXCSRL(n)
Definition: usb.h:120
#define USB_TXFIFOSZ
Definition: usb.h:87
#define USB_FIFOSZ_SIZE_2048
Definition: usb.h:246
#define USB_IS
Definition: usb.h:67
struct _usbd_device usbd_device
Definition: usbd.h:53
void _usbd_reset(usbd_device *usbd_dev)
Definition: usb.c:113
void usb_disable_interrupts(enum usb_interrupt ints, enum usb_ep_interrupt rx_ints, enum usb_ep_interrupt tx_ints)
Disable Specific USB Interrupts.
Definition: usb_lm4f.c:158
#define MAX_FIFO_RAM
Definition: usb_lm4f.c:111
void usb_enable_interrupts(enum usb_interrupt ints, enum usb_ep_interrupt rx_ints, enum usb_ep_interrupt tx_ints)
Enable Specific USB Interrupts.
Definition: usb_lm4f.c:132
const struct _usbd_driver lm4f_usb_driver
Definition: usb_lm4f.c:113
#define USB_ENDPOINT_ATTR_ISOCHRONOUS
Definition: usbstd.h:233
#define USB_BASE