libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
i2c_common_v1.h
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1/** @addtogroup i2c_defines
2 *
3 * @author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
4 *
5 */
6/*
7 * This file is part of the libopencm3 project.
8 *
9 * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
10 *
11 * This library is free software: you can redistribute it and/or modify
12 * it under the terms of the GNU Lesser General Public License as published by
13 * the Free Software Foundation, either version 3 of the License, or
14 * (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public License
22 * along with this library. If not, see <http://www.gnu.org/licenses/>.
23 */
24
25/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H
26The order of header inclusion is important. i2c.h includes the device
27specific memorymap.h header before including this header file.*/
28
29/**@{*/
30
31/** @cond */
32#ifdef LIBOPENCM3_I2C_H
33/** @endcond */
34#ifndef LIBOPENCM3_I2C_COMMON_V1_H
35#define LIBOPENCM3_I2C_COMMON_V1_H
36
37#include <stddef.h>
38#include <stdint.h>
39
40/* --- Convenience macros -------------------------------------------------- */
41
42/* I2C register base addresses (for convenience) */
43/****************************************************************************/
44/** @defgroup i2c_reg_base I2C register base address
45@ingroup i2c_defines
46
47@{*/
48#define I2C1 I2C1_BASE
49#define I2C2 I2C2_BASE
50#ifdef I2C3_BASE
51#define I2C3 I2C3_BASE
52#endif
53/**@}*/
54
55/* --- I2C registers ------------------------------------------------------- */
56
57/* Control register 1 (I2Cx_CR1) */
58#define I2C_CR1(i2c_base) MMIO32((i2c_base) + 0x00)
59#define I2C1_CR1 I2C_CR1(I2C1)
60#define I2C2_CR1 I2C_CR1(I2C2)
61
62/* Control register 2 (I2Cx_CR2) */
63#define I2C_CR2(i2c_base) MMIO32((i2c_base) + 0x04)
64#define I2C1_CR2 I2C_CR2(I2C1)
65#define I2C2_CR2 I2C_CR2(I2C2)
66
67/* Own address register 1 (I2Cx_OAR1) */
68#define I2C_OAR1(i2c_base) MMIO32((i2c_base) + 0x08)
69#define I2C1_OAR1 I2C_OAR1(I2C1)
70#define I2C2_OAR1 I2C_OAR1(I2C2)
71
72/* Own address register 2 (I2Cx_OAR2) */
73#define I2C_OAR2(i2c_base) MMIO32((i2c_base) + 0x0c)
74#define I2C1_OAR2 I2C_OAR2(I2C1)
75#define I2C2_OAR2 I2C_OAR2(I2C2)
76
77/* Data register (I2Cx_DR) */
78#define I2C_DR(i2c_base) MMIO32((i2c_base) + 0x10)
79#define I2C1_DR I2C_DR(I2C1)
80#define I2C2_DR I2C_DR(I2C2)
81
82/* Status register 1 (I2Cx_SR1) */
83#define I2C_SR1(i2c_base) MMIO32((i2c_base) + 0x14)
84#define I2C1_SR1 I2C_SR1(I2C1)
85#define I2C2_SR1 I2C_SR1(I2C2)
86
87/* Status register 2 (I2Cx_SR2) */
88#define I2C_SR2(i2c_base) MMIO32((i2c_base) + 0x18)
89#define I2C1_SR2 I2C_SR2(I2C1)
90#define I2C2_SR2 I2C_SR2(I2C2)
91
92/* Clock control register (I2Cx_CCR) */
93#define I2C_CCR(i2c_base) MMIO32((i2c_base) + 0x1c)
94#define I2C1_CCR I2C_CCR(I2C1)
95#define I2C2_CCR I2C_CCR(I2C2)
96
97/* TRISE register (I2Cx_CCR) */
98#define I2C_TRISE(i2c_base) MMIO32((i2c_base) + 0x20)
99#define I2C1_TRISE I2C_TRISE(I2C1)
100#define I2C2_TRISE I2C_TRISE(I2C2)
101
102/* Not all parts have i2c3 */
103#ifdef I2C3_BASE
104#define I2C3_CR1 I2C_CR1(I2C3)
105#define I2C3_CR2 I2C_CR2(I2C3)
106#define I2C3_OAR1 I2C_OAR1(I2C3)
107#define I2C3_OAR2 I2C_OAR2(I2C3)
108#define I2C3_DR I2C_DR(I2C3)
109#define I2C3_SR1 I2C_SR1(I2C3)
110#define I2C3_SR2 I2C_SR2(I2C3)
111#define I2C3_CCR I2C_CCR(I2C3)
112#define I2C3_TRISE I2C_TRISE(I2C3)
113#endif
114
115/* --- I2Cx_CR1 values ----------------------------------------------------- */
116
117/* SWRST: Software reset */
118#define I2C_CR1_SWRST (1 << 15)
119
120/* Note: Bit 14 is reserved, and forced to 0 by hardware. */
121
122/* ALERT: SMBus alert */
123#define I2C_CR1_ALERT (1 << 13)
124
125/* PEC: Packet error checking */
126#define I2C_CR1_PEC (1 << 12)
127
128/* POS: Acknowledge / PEC position */
129#define I2C_CR1_POS (1 << 11)
130
131/* ACK: Acknowledge enable */
132#define I2C_CR1_ACK (1 << 10)
133
134/* STOP: STOP generation */
135#define I2C_CR1_STOP (1 << 9)
136
137/* START: START generation */
138#define I2C_CR1_START (1 << 8)
139
140/* NOSTRETCH: Clock stretching disable (slave mode) */
141#define I2C_CR1_NOSTRETCH (1 << 7)
142
143/* ENGC: General call enable */
144#define I2C_CR1_ENGC (1 << 6)
145
146/* ENPEC: Enable PEC */
147#define I2C_CR1_ENPEC (1 << 5)
148
149/* ENARP: ARP enable */
150#define I2C_CR1_ENARP (1 << 4)
151
152/* SMBTYPE: SMBus type */
153#define I2C_CR1_SMBTYPE (1 << 3)
154
155/* Note: Bit 2 is reserved, and forced to 0 by hardware. */
156
157/* SMBUS: SMBus mode */
158#define I2C_CR1_SMBUS (1 << 1)
159
160/* PE: Peripheral enable */
161#define I2C_CR1_PE (1 << 0)
162
163/* --- I2Cx_CR2 values ----------------------------------------------------- */
164
165/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */
166
167/* LAST: DMA last transfer */
168#define I2C_CR2_LAST (1 << 12)
169
170/* DMAEN: DMA requests enable */
171#define I2C_CR2_DMAEN (1 << 11)
172
173/* ITBUFEN: Buffer interrupt enable */
174#define I2C_CR2_ITBUFEN (1 << 10)
175
176/* ITEVTEN: Event interrupt enable */
177#define I2C_CR2_ITEVTEN (1 << 9)
178
179/* ITERREN: Error interrupt enable */
180#define I2C_CR2_ITERREN (1 << 8)
181
182/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
183
185 I2C_CR2_FREQ_2MHZ __attribute__ ((deprecated("Replace with 2 directly"))) = 2,
186 I2C_CR2_FREQ_3MHZ __attribute__ ((deprecated("Replace with 3 directly"))),
187 I2C_CR2_FREQ_4MHZ __attribute__ ((deprecated("Replace with 4 directly"))),
188 I2C_CR2_FREQ_5MHZ __attribute__ ((deprecated("Replace with 5 directly"))),
189 I2C_CR2_FREQ_6MHZ __attribute__ ((deprecated("Replace with 6 directly"))),
190 I2C_CR2_FREQ_7MHZ __attribute__ ((deprecated("Replace with 7 directly"))),
191 I2C_CR2_FREQ_8MHZ __attribute__ ((deprecated("Replace with 8 directly"))),
192 I2C_CR2_FREQ_9MHZ __attribute__ ((deprecated("Replace with 9 directly"))),
193 I2C_CR2_FREQ_10MHZ __attribute__ ((deprecated("Replace with 10 directly"))),
194 I2C_CR2_FREQ_11MHZ __attribute__ ((deprecated("Replace with 11 directly"))),
195 I2C_CR2_FREQ_12MHZ __attribute__ ((deprecated("Replace with 12 directly"))),
196 I2C_CR2_FREQ_13MHZ __attribute__ ((deprecated("Replace with 13 directly"))),
197 I2C_CR2_FREQ_14MHZ __attribute__ ((deprecated("Replace with 14 directly"))),
198 I2C_CR2_FREQ_15MHZ __attribute__ ((deprecated("Replace with 15 directly"))),
199 I2C_CR2_FREQ_16MHZ __attribute__ ((deprecated("Replace with 16 directly"))),
200 I2C_CR2_FREQ_17MHZ __attribute__ ((deprecated("Replace with 17 directly"))),
201 I2C_CR2_FREQ_18MHZ __attribute__ ((deprecated("Replace with 18 directly"))),
202 I2C_CR2_FREQ_19MHZ __attribute__ ((deprecated("Replace with 19 directly"))),
203 I2C_CR2_FREQ_20MHZ __attribute__ ((deprecated("Replace with 20 directly"))),
204 I2C_CR2_FREQ_21MHZ __attribute__ ((deprecated("Replace with 21 directly"))),
205 I2C_CR2_FREQ_22MHZ __attribute__ ((deprecated("Replace with 22 directly"))),
206 I2C_CR2_FREQ_23MHZ __attribute__ ((deprecated("Replace with 23 directly"))),
207 I2C_CR2_FREQ_24MHZ __attribute__ ((deprecated("Replace with 24 directly"))),
208 I2C_CR2_FREQ_25MHZ __attribute__ ((deprecated("Replace with 25 directly"))),
209 I2C_CR2_FREQ_26MHZ __attribute__ ((deprecated("Replace with 26 directly"))),
210 I2C_CR2_FREQ_27MHZ __attribute__ ((deprecated("Replace with 27 directly"))),
211 I2C_CR2_FREQ_28MHZ __attribute__ ((deprecated("Replace with 28 directly"))),
212 I2C_CR2_FREQ_29MHZ __attribute__ ((deprecated("Replace with 29 directly"))),
213 I2C_CR2_FREQ_30MHZ __attribute__ ((deprecated("Replace with 30 directly"))),
214 I2C_CR2_FREQ_31MHZ __attribute__ ((deprecated("Replace with 31 directly"))),
215 I2C_CR2_FREQ_32MHZ __attribute__ ((deprecated("Replace with 32 directly"))),
216 I2C_CR2_FREQ_33MHZ __attribute__ ((deprecated("Replace with 33 directly"))),
217 I2C_CR2_FREQ_34MHZ __attribute__ ((deprecated("Replace with 34 directly"))),
218 I2C_CR2_FREQ_35MHZ __attribute__ ((deprecated("Replace with 35 directly"))),
219 I2C_CR2_FREQ_36MHZ __attribute__ ((deprecated("Replace with 36 directly"))),
220 I2C_CR2_FREQ_37MHZ __attribute__ ((deprecated("Replace with 37 directly"))),
221 I2C_CR2_FREQ_38MHZ __attribute__ ((deprecated("Replace with 38 directly"))),
222 I2C_CR2_FREQ_39MHZ __attribute__ ((deprecated("Replace with 39 directly"))),
223 I2C_CR2_FREQ_40MHZ __attribute__ ((deprecated("Replace with 40 directly"))),
224 I2C_CR2_FREQ_41MHZ __attribute__ ((deprecated("Replace with 41 directly"))),
225 I2C_CR2_FREQ_42MHZ __attribute__ ((deprecated("Replace with 42 directly"))),
226} __attribute__ ((deprecated("Replace _nMHZ with n directly")));
227
228
229/* --- I2Cx_OAR1 values ---------------------------------------------------- */
230
231/* ADDMODE: Addressing mode (slave mode) */
232#define I2C_OAR1_ADDMODE (1 << 15)
233#define I2C_OAR1_ADDMODE_7BIT 0
234#define I2C_OAR1_ADDMODE_10BIT 1
235
236/* Note: Bit 14 should always be kept at 1 by software! */
237
238/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */
239
240/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */
241
242/* --- I2Cx_OAR2 values ---------------------------------------------------- */
243
244/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
245
246/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */
247
248/* ENDUAL: Dual addressing mode enable */
249#define I2C_OAR2_ENDUAL (1 << 0)
250
251/* --- I2Cx_DR values ------------------------------------------------------ */
252
253/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
254
255/* DR[7:0] 8-bit data register */
256
257/* --- I2Cx_SR1 values ----------------------------------------------------- */
258
259/* SMBALERT: SMBus alert */
260#define I2C_SR1_SMBALERT (1 << 15)
261
262/* TIMEOUT: Timeout or Tlow Error */
263#define I2C_SR1_TIMEOUT (1 << 14)
264
265/* Note: Bit 13 is reserved, and forced to 0 by hardware. */
266
267/* PECERR: PEC Error in reception */
268#define I2C_SR1_PECERR (1 << 12)
269
270/* OVR: Overrun/Underrun */
271#define I2C_SR1_OVR (1 << 11)
272
273/* AF: Acknowledge failure */
274#define I2C_SR1_AF (1 << 10)
275
276/* ARLO: Arbitration lost (master mode) */
277#define I2C_SR1_ARLO (1 << 9)
278
279/* BERR: Bus error */
280#define I2C_SR1_BERR (1 << 8)
281
282/* TxE: Data register empty (transmitters) */
283#define I2C_SR1_TxE (1 << 7)
284
285/* RxNE: Data register not empty (receivers) */
286#define I2C_SR1_RxNE (1 << 6)
287
288/* Note: Bit 5 is reserved, and forced to 0 by hardware. */
289
290/* STOPF: STOP detection (slave mode) */
291#define I2C_SR1_STOPF (1 << 4)
292
293/* ADD10: 10-bit header sent (master mode) */
294#define I2C_SR1_ADD10 (1 << 3)
295
296/* BTF: Byte transfer finished */
297#define I2C_SR1_BTF (1 << 2)
298
299/* ADDR: Address sent (master mode) / address matched (slave mode) */
300#define I2C_SR1_ADDR (1 << 1)
301
302/* SB: Start bit (master mode) */
303#define I2C_SR1_SB (1 << 0)
304
305/* --- I2Cx_SR2 values ----------------------------------------------------- */
306
307/* Bits [15:8]: PEC[7:0]: Packet error checking register */
308
309/* DUALF: Dual flag (slave mode) */
310#define I2C_SR2_DUALF (1 << 7)
311
312/* SMBHOST: SMBus host header (slave mode) */
313#define I2C_SR2_SMBHOST (1 << 6)
314
315/* SMBDEFAULT: SMBus device default address (slave mode) */
316#define I2C_SR2_SMBDEFAULT (1 << 5)
317
318/* GENCALL: General call address (slave mode) */
319#define I2C_SR2_GENCALL (1 << 4)
320
321/* Note: Bit 3 is reserved, and forced to 0 by hardware. */
322
323/* TRA: Transmitter / receiver */
324#define I2C_SR2_TRA (1 << 2)
325
326/* BUSY: Bus busy */
327#define I2C_SR2_BUSY (1 << 1)
328
329/* MSL: Master / slave */
330#define I2C_SR2_MSL (1 << 0)
331
332/* --- I2Cx_CCR values ----------------------------------------------------- */
333
334/* F/S: I2C Master mode selection (fast / standard) */
335#define I2C_CCR_FS (1 << 15)
336
337/* DUTY: Fast Mode Duty Cycle */
338/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles
339@ingroup i2c_defines
340
341@{*/
342#define I2C_CCR_DUTY (1 << 14)
343#define I2C_CCR_DUTY_DIV2 0
344#define I2C_CCR_DUTY_16_DIV_9 1
345/**@}*/
346
347/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
348
349/*
350 * Bits [11:0]:
351 * CCR[11:0]: Clock control register in Fast/Standard mode (master mode)
352 */
353
354/* --- I2Cx_TRISE values --------------------------------------------------- */
355
356/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
357
358/*
359 * Bits [5:0]:
360 * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
361 */
362
363/* --- I2C constant definitions -------------------------------------------- */
364
365/****************************************************************************/
366/** @defgroup i2c_rw I2C Read/Write bit
367@ingroup i2c_defines
368
369@{*/
370#define I2C_WRITE 0
371#define I2C_READ 1
372/**@}*/
373
374/* --- I2C function prototypes---------------------------------------------- */
375
376/**
377 * I2C speed modes.
378 */
385
387
388void i2c_peripheral_enable(uint32_t i2c);
389void i2c_peripheral_disable(uint32_t i2c);
390void i2c_send_start(uint32_t i2c);
391void i2c_send_stop(uint32_t i2c);
392void i2c_clear_stop(uint32_t i2c);
393void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave);
394void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave);
395void i2c_set_own_7bit_slave_address_two(uint32_t i2c, uint8_t slave);
396void i2c_enable_dual_addressing_mode(uint32_t i2c);
397void i2c_disable_dual_addressing_mode(uint32_t i2c);
398void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq);
399void i2c_send_data(uint32_t i2c, uint8_t data);
400void i2c_set_fast_mode(uint32_t i2c);
401void i2c_set_standard_mode(uint32_t i2c);
402void i2c_set_ccr(uint32_t i2c, uint16_t freq);
403void i2c_set_trise(uint32_t i2c, uint16_t trise);
404void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite);
405uint8_t i2c_get_data(uint32_t i2c);
406void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt);
407void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt);
408void i2c_enable_ack(uint32_t i2c);
409void i2c_disable_ack(uint32_t i2c);
410void i2c_nack_next(uint32_t i2c);
411void i2c_nack_current(uint32_t i2c);
412void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle);
413void i2c_enable_dma(uint32_t i2c);
414void i2c_disable_dma(uint32_t i2c);
415void i2c_set_dma_last_transfer(uint32_t i2c);
416void i2c_clear_dma_last_transfer(uint32_t i2c);
417void i2c_transfer7(uint32_t i2c, uint8_t addr, const uint8_t *w, size_t wn, uint8_t *r, size_t rn);
418void i2c_set_speed(uint32_t i2c, enum i2c_speeds speed, uint32_t clock_megahz);
419
421
422#endif
423/** @cond */
424#else
425#warning "i2c_common_v1.h should not be included explicitly, only via i2c.h"
426#endif
427/** @endcond */
428/**@}*/
429
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
I2C Disable Interrupt.
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
I2C Enable Interrupt.
void i2c_disable_ack(uint32_t i2c)
I2C Disable ACK.
void i2c_set_dma_last_transfer(uint32_t i2c)
I2C Set DMA last transfer.
void i2c_nack_current(uint32_t i2c)
I2C NACK Next Byte.
i2c_cr2_freq_values
void i2c_set_fast_mode(uint32_t i2c)
I2C Set Fast Mode.
void i2c_enable_ack(uint32_t i2c)
I2C Enable ACK.
void i2c_send_start(uint32_t i2c)
I2C Send Start Condition.
Definition: i2c_common_v1.c:80
void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq)
I2C Set Peripheral Clock Frequency.
void i2c_peripheral_disable(uint32_t i2c)
I2C Peripheral Disable.
Definition: i2c_common_v1.c:65
void i2c_set_own_7bit_slave_address_two(uint32_t i2c, uint8_t slave)
I2C Set the secondary 7 bit Slave Address for the Peripheral.
void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle)
I2C Set clock duty cycle.
void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
I2C Set the 7 bit Slave Address for the Peripheral.
void i2c_disable_dual_addressing_mode(uint32_t i2c)
I2C Disable dual addressing mode for the Peripheral.
void i2c_set_standard_mode(uint32_t i2c)
I2C Set Standard Mode.
void i2c_set_trise(uint32_t i2c, uint16_t trise)
I2C Set the Rise Time.
void i2c_send_stop(uint32_t i2c)
I2C Send Stop Condition.
Definition: i2c_common_v1.c:94
void i2c_peripheral_enable(uint32_t i2c)
I2C Peripheral Enable.
Definition: i2c_common_v1.c:51
i2c_speeds
I2C speed modes.
void i2c_nack_next(uint32_t i2c)
I2C NACK Next Byte.
void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
I2C Set the 10 bit Slave Address for the Peripheral.
void i2c_disable_dma(uint32_t i2c)
I2C Disable DMA.
void i2c_send_data(uint32_t i2c, uint8_t data)
I2C Send Data.
void i2c_clear_dma_last_transfer(uint32_t i2c)
I2C Clear DMA last transfer.
uint8_t i2c_get_data(uint32_t i2c)
I2C Get Data.
void i2c_clear_stop(uint32_t i2c)
I2C Clear Stop Flag.
void i2c_set_ccr(uint32_t i2c, uint16_t freq)
I2C Set Bus Clock Frequency.
void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite)
I2C Send the 7-bit Slave Address.
void i2c_enable_dual_addressing_mode(uint32_t i2c)
I2C Enable dual addressing mode for the Peripheral.
void i2c_transfer7(uint32_t i2c, uint8_t addr, const uint8_t *w, size_t wn, uint8_t *r, size_t rn)
Run a write/read transaction to a given 7bit i2c address If both write & read are provided,...
void i2c_enable_dma(uint32_t i2c)
I2C Enable DMA.
void i2c_set_speed(uint32_t i2c, enum i2c_speeds speed, uint32_t clock_megahz)
Set the i2c communication speed.
@ I2C_CR2_FREQ_41MHZ
@ I2C_CR2_FREQ_22MHZ
@ I2C_CR2_FREQ_35MHZ
@ I2C_CR2_FREQ_7MHZ
@ I2C_CR2_FREQ_34MHZ
@ I2C_CR2_FREQ_9MHZ
@ I2C_CR2_FREQ_4MHZ
@ I2C_CR2_FREQ_33MHZ
@ I2C_CR2_FREQ_20MHZ
@ I2C_CR2_FREQ_15MHZ
@ I2C_CR2_FREQ_36MHZ
@ I2C_CR2_FREQ_23MHZ
@ I2C_CR2_FREQ_13MHZ
@ I2C_CR2_FREQ_32MHZ
@ I2C_CR2_FREQ_6MHZ
@ I2C_CR2_FREQ_12MHZ
@ I2C_CR2_FREQ_37MHZ
@ I2C_CR2_FREQ_25MHZ
@ I2C_CR2_FREQ_17MHZ
@ I2C_CR2_FREQ_28MHZ
@ I2C_CR2_FREQ_10MHZ
@ I2C_CR2_FREQ_14MHZ
@ I2C_CR2_FREQ_30MHZ
@ I2C_CR2_FREQ_42MHZ
@ I2C_CR2_FREQ_18MHZ
@ I2C_CR2_FREQ_21MHZ
@ I2C_CR2_FREQ_3MHZ
@ I2C_CR2_FREQ_8MHZ
@ I2C_CR2_FREQ_38MHZ
@ I2C_CR2_FREQ_27MHZ
@ I2C_CR2_FREQ_29MHZ
@ I2C_CR2_FREQ_19MHZ
@ I2C_CR2_FREQ_11MHZ
@ I2C_CR2_FREQ_24MHZ
@ I2C_CR2_FREQ_26MHZ
@ I2C_CR2_FREQ_5MHZ
@ I2C_CR2_FREQ_40MHZ
@ I2C_CR2_FREQ_16MHZ
@ I2C_CR2_FREQ_31MHZ
@ I2C_CR2_FREQ_39MHZ
@ I2C_CR2_FREQ_2MHZ
@ i2c_speed_fmp_1m
@ i2c_speed_unknown
@ i2c_speed_fm_400k
@ i2c_speed_sm_100k