libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
timer_common_all.c
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1/** @addtogroup timer_file TIMER peripheral API
2@ingroup peripheral_apis
3
4@author @htmlonly © @endhtmlonly 2010
5Edward Cheeseman <evbuilder@users.sourceforge.org>
6@author @htmlonly &copy; @endhtmlonly 2011
7Stephen Caudle <scaudle@doceme.com>
8
9@section tim_common Notes for All Timers
10
11This library supports the General Purpose and Advanced Control Timers for
12the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.
13
14The STM32 series have four general purpose timers (2-5), while some have
15an additional two advanced timers (1,8), and some have two basic timers (6,7).
16Some of the larger devices have additional general purpose timers (9-14).
17
18@todo Add timer DMA burst settings
19
20@section tim_api_ex Basic TIMER handling API.
21
22Enable the timer clock first. The timer mode sets the clock division ratio, the
23count alignment (edge or centred) and count direction. Finally enable the
24timer.
25
26The timer output compare block produces a signal that can be configured for
27output to a pin or passed to other peripherals for use as a trigger. In all
28cases the output compare mode must be set to define how the output responds to
29a compare match, and the output must be enabled. If output to a pin is
30required, enable the appropriate GPIO clock and set the pin to alternate output
31mode.
32
33Example: Timer 2 with 2x clock divide, edge aligned and up counting.
34@code
35 rcc_periph_clock_enable(RCC_TIM2);
36 timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT_MUL_2,
37 TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
38 ...
39 timer_set_period(TIM2, 1000);
40 timer_enable_counter(TIM2);
41@endcode
42Example: Timer 1 with PWM output, no clock divide and centre alignment. Set the
43Output Compare mode to PWM and enable the output of channel 1. Note that for
44the advanced timers the break functionality must be enabled before the signal
45will appear at the output, even though break is not being used. This is in
46addition to the normal output enable. Enable the alternate function clock (APB2
47only) and port A clock. Set port A8 (timer 1 channel 1 compare output) to
48alternate function push-pull output where the PWM output will appear.
49
50@code
51 rcc_periph_clock_enable(RCC_TIM1);
52 rcc_periph_clock_enable(RCC_GPIOA);
53
54 // for F1....
55 rcc_periph_clock_enable(RCC_AFIO);
56 gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO8);
57 // For anyone else
58 gpio_set_output_options(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO8);
59 // End of family specific
60
61 rcc_periph_clock_enable(RCC_TIM1);
62 timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1,
63 TIM_CR1_DIR_UP);
64 timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM2);
65 timer_enable_oc_output(TIM1, TIM_OC1);
66 timer_enable_break_main_output(TIM1);
67 timer_set_oc_value(TIM1, TIM_OC1, 200);
68 timer_set_period(TIM1, 1000);
69 timer_enable_counter(TIM1);
70@endcode
71Example: Timer 3 as a Quadrature encoder counting input from a motor or control
72knob.
73
74@code
75 rcc_periph_clock_enable(RCC_TIM3);
76 timer_set_period(TIM3, 1024);
77 timer_slave_set_mode(TIM3, 0x3); // encoder
78 timer_ic_set_input(TIM3, TIM_IC1, TIM_IC_IN_TI1);
79 timer_ic_set_input(TIM3, TIM_IC2, TIM_IC_IN_TI2);
80 timer_enable_counter(TIM3);
81 ...
82 int motor_pos = timer_get_count(TIM3);
83@endcode
84
85@todo input capture example
86
87*/
88
89/*
90 * This file is part of the libopencm3 project.
91 *
92 * Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org>
93 * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
94 *
95 * This library is free software: you can redistribute it and/or modify
96 * it under the terms of the GNU Lesser General Public License as published by
97 * the Free Software Foundation, either version 3 of the License, or
98 * (at your option) any later version.
99 *
100 * This library is distributed in the hope that it will be useful,
101 * but WITHOUT ANY WARRANTY; without even the implied warranty of
102 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
103 * GNU Lesser General Public License for more details.
104 *
105 * You should have received a copy of the GNU Lesser General Public License
106 * along with this library. If not, see <http://www.gnu.org/licenses/>.
107 */
108
109/*
110 * Basic TIMER handling API.
111 *
112 * Examples:
113 * timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT_MUL_2,
114 * TIM_CR1_CMS_CENTRE_3, TIM_CR1_DIR_UP);
115 */
116
117/**@{*/
118
120#include <libopencm3/stm32/rcc.h>
121
122/*---------------------------------------------------------------------------*/
123/** @brief Enable Interrupts for a Timer
124
125@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
126tim_reg_base
127@param[in] irq Unsigned int32. @ref tim_irq_enable. Logical OR of all interrupt
128enable bits to be set
129*/
130
131void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq)
132{
133 TIM_DIER(timer_peripheral) |= irq;
134}
135
136/*---------------------------------------------------------------------------*/
137/** @brief Disable Interrupts for a Timer.
138
139@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
140tim_reg_base
141@param[in] irq Unsigned int32. @ref tim_irq_enable. Logical OR of all interrupt
142enable bits to be cleared
143*/
144
145void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq)
146{
147 TIM_DIER(timer_peripheral) &= ~irq;
148}
149
150/*---------------------------------------------------------------------------*/
151/** @brief Return Interrupt Source.
152
153Returns true if the specified interrupt flag (UIF, TIF or CCxIF, with BIF or
154COMIF for advanced timers) was set and the interrupt was enabled. If the
155specified flag is not an interrupt flag, the function returns false.
156
157@todo Timers 6-7, 9-14 have fewer interrupts, but invalid flags are not caught
158here.
159
160@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
161tim_reg_base
162@param[in] flag Unsigned int32. Status register flag @ref tim_sr_values.
163@returns boolean: flag set.
164*/
165
166bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag)
167{
168/* flag not set or interrupt disabled or not an interrupt source */
169 if (((TIM_SR(timer_peripheral) &
170 TIM_DIER(timer_peripheral) & flag) == 0) ||
171 (flag > TIM_SR_BIF)) {
172 return false;
173 }
174 return true;
175}
176
177/*---------------------------------------------------------------------------*/
178/** @brief Read a Status Flag.
179
180@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
181tim_reg_base
182@param[in] flag Unsigned int32. Status register flag @ref tim_sr_values.
183@returns boolean: flag set.
184*/
185
186bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag)
187{
188 if ((TIM_SR(timer_peripheral) & flag) != 0) {
189 return true;
190 }
191
192 return false;
193}
194
195/*---------------------------------------------------------------------------*/
196/** @brief Clear a Status Flag.
197
198@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
199tim_reg_base
200@param[in] flag Unsigned int32. @ref tim_sr_values. Status register flag.
201*/
202
203void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag)
204{
205 /* All defined bits are rc_w0 */
206 TIM_SR(timer_peripheral) = ~flag;
207}
208
209/*---------------------------------------------------------------------------*/
210/** @brief Set the Timer Mode.
211
212The modes are:
213
214@li Clock divider ratio (to form the sampling clock for the input filters,
215and the dead-time clock in the advanced timers 1 and 8)
216@li Edge/centre alignment
217@li Count direction
218
219The alignment and count direction are effective only for timers 1 to 5 and 8
220while the clock divider ratio is effective for all timers except 6,7
221The remaining timers are limited hardware timers which do not support these mode
222settings.
223
224@note: When center alignment mode is selected, count direction is controlled by
225hardware and cannot be written. The count direction setting has no effect
226in this case.
227
228@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
229tim_reg_base (TIM1, TIM2 ... TIM5, TIM8)
230@param[in] clock_div Unsigned int32. Clock Divider Ratio in bits 8,9: @ref
231tim_x_cr1_cdr
232@param[in] alignment Unsigned int32. Alignment bits in 5,6: @ref tim_x_cr1_cms
233@param[in] direction Unsigned int32. Count direction in bit 4,: @ref
234tim_x_cr1_dir
235*/
236
237void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div,
238 uint32_t alignment, uint32_t direction)
239{
240 uint32_t cr1;
241
242 cr1 = TIM_CR1(timer_peripheral);
243
245
246 cr1 |= clock_div | alignment | direction;
247
248 TIM_CR1(timer_peripheral) = cr1;
249}
250
251/*---------------------------------------------------------------------------*/
252/** @brief Set Input Filter and Dead-time Clock Divider Ratio.
253
254This forms the sampling clock for the input filters and the dead-time clock
255in the advanced timers 1 and 8, by division from the timer clock.
256
257@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
258tim_reg_base
259@param[in] clock_div Unsigned int32. Clock Divider Ratio in bits 8,9: @ref
260tim_x_cr1_cdr
261*/
262
263void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div)
264{
265 clock_div &= TIM_CR1_CKD_CK_INT_MASK;
266 TIM_CR1(timer_peripheral) &= ~TIM_CR1_CKD_CK_INT_MASK;
267 TIM_CR1(timer_peripheral) |= clock_div;
268}
269
270/*---------------------------------------------------------------------------*/
271/** @brief Enable Auto-Reload Buffering.
272
273During counter operation this causes the counter to be loaded from its
274auto-reload register only at the next update event.
275
276@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
277tim_reg_base
278*/
279
280void timer_enable_preload(uint32_t timer_peripheral)
281{
282 TIM_CR1(timer_peripheral) |= TIM_CR1_ARPE;
283}
284
285/*---------------------------------------------------------------------------*/
286/** @brief Disable Auto-Reload Buffering.
287
288This causes the counter to be loaded immediately with a new count value when the
289auto-reload register is written, so that the new value becomes effective for the
290current count cycle rather than for the cycle following an update event.
291
292@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
293tim_reg_base
294*/
295
296void timer_disable_preload(uint32_t timer_peripheral)
297{
298 TIM_CR1(timer_peripheral) &= ~TIM_CR1_ARPE;
299}
300
301/*---------------------------------------------------------------------------*/
302/** @brief Specify the counter alignment mode.
303
304The mode can be edge aligned or centered.
305
306@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
307tim_reg_base
308@param[in] alignment Unsigned int32. Alignment bits in 5,6: @ref tim_x_cr1_cms
309*/
310
311void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment)
312{
313 alignment &= TIM_CR1_CMS_MASK;
314 TIM_CR1(timer_peripheral) &= ~TIM_CR1_CMS_MASK;
315 TIM_CR1(timer_peripheral) |= alignment;
316}
317
318/*---------------------------------------------------------------------------*/
319/** @brief Set the Timer to Count Up.
320
321This has no effect if the timer is set to center aligned.
322
323@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
324tim_reg_base
325*/
326
327void timer_direction_up(uint32_t timer_peripheral)
328{
329 TIM_CR1(timer_peripheral) &= ~TIM_CR1_DIR_DOWN;
330}
331
332/*---------------------------------------------------------------------------*/
333/** @brief Set the Timer to Count Down.
334
335This has no effect if the timer is set to center aligned.
336
337@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
338tim_reg_base
339*/
340
341void timer_direction_down(uint32_t timer_peripheral)
342{
343 TIM_CR1(timer_peripheral) |= TIM_CR1_DIR_DOWN;
344}
345
346/*---------------------------------------------------------------------------*/
347/** @brief Enable the Timer for One Cycle and Stop.
348
349@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
350tim_reg_base
351*/
352
353void timer_one_shot_mode(uint32_t timer_peripheral)
354{
355 TIM_CR1(timer_peripheral) |= TIM_CR1_OPM;
356}
357
358/*---------------------------------------------------------------------------*/
359/** @brief Enable the Timer to Run Continuously.
360
361@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
362tim_reg_base
363*/
364
365void timer_continuous_mode(uint32_t timer_peripheral)
366{
367 TIM_CR1(timer_peripheral) &= ~TIM_CR1_OPM;
368}
369
370/*---------------------------------------------------------------------------*/
371/** @brief Set the Timer to Generate Update IRQ or DMA on any Event.
372
373The events which will generate an interrupt or DMA request can be
374@li a counter underflow/overflow,
375@li a forced update,
376@li an event from the slave mode controller.
377
378@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
379tim_reg_base
380*/
381
382void timer_update_on_any(uint32_t timer_peripheral)
383{
384 TIM_CR1(timer_peripheral) &= ~TIM_CR1_URS;
385}
386
387/*---------------------------------------------------------------------------*/
388/** @brief Set the Timer to Generate Update IRQ or DMA only from Under/Overflow
389Events.
390
391@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
392tim_reg_base
393*/
394
395void timer_update_on_overflow(uint32_t timer_peripheral)
396{
397 TIM_CR1(timer_peripheral) |= TIM_CR1_URS;
398}
399
400/*---------------------------------------------------------------------------*/
401/** @brief Enable Timer Update Events.
402
403@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
404tim_reg_base
405*/
406
407void timer_enable_update_event(uint32_t timer_peripheral)
408{
409 TIM_CR1(timer_peripheral) &= ~TIM_CR1_UDIS;
410}
411
412/*---------------------------------------------------------------------------*/
413/** @brief Disable Timer Update Events.
414
415Update events are not generated and the shadow registers keep their values.
416
417@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
418tim_reg_base
419*/
420
421void timer_disable_update_event(uint32_t timer_peripheral)
422{
423 TIM_CR1(timer_peripheral) |= TIM_CR1_UDIS;
424}
425
426/*---------------------------------------------------------------------------*/
427/** @brief Enable the timer to start counting.
428
429This should be called after the timer initial configuration has been completed.
430
431@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
432tim_reg_base
433*/
434
435void timer_enable_counter(uint32_t timer_peripheral)
436{
437 TIM_CR1(timer_peripheral) |= TIM_CR1_CEN;
438}
439
440/*---------------------------------------------------------------------------*/
441/** @brief Stop the timer from counting.
442
443@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
444tim_reg_base
445*/
446
447void timer_disable_counter(uint32_t timer_peripheral)
448{
449 TIM_CR1(timer_peripheral) &= ~TIM_CR1_CEN;
450}
451
452/*---------------------------------------------------------------------------*/
453/** @brief Set Timer Output Idle States High.
454
455This determines the value of the timer output compare when it enters idle state.
456
457@sa @ref timer_set_oc_idle_state_set
458
459@note This setting is only valid for the advanced timers.
460
461@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
462tim_reg_base
463@param[in] outputs Unsigned int32. Timer Output Idle State Controls @ref
464tim_x_cr2_ois. If several settings are to be made, use the logical OR of the
465output control values.
466*/
467
468void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs)
469{
470 TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK;
471}
472
473/*---------------------------------------------------------------------------*/
474/** @brief Set Timer Output Idle States Low.
475
476This determines the value of the timer output compare when it enters idle state.
477
478@sa @ref timer_set_oc_idle_state_unset
479
480@note This setting is only valid for the advanced timers.
481
482@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
483tim_reg_base
484@param[in] outputs Unsigned int32. Timer Output Idle State Controls @ref
485tim_x_cr2_ois
486*/
487
488void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs)
489{
490 TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK);
491}
492
493/*---------------------------------------------------------------------------*/
494/** @brief Set Timer 1 Input to XOR of Three Channels.
495
496The first timer capture input is formed from the XOR of the first three timer
497input channels 1, 2, 3.
498
499@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
500tim_reg_base
501*/
502
503void timer_set_ti1_ch123_xor(uint32_t timer_peripheral)
504{
505 TIM_CR2(timer_peripheral) |= TIM_CR2_TI1S;
506}
507
508/*---------------------------------------------------------------------------*/
509/** @brief Set Timer 1 Input to Channel 1.
510
511The first timer capture input is taken from the timer input channel 1 only.
512
513@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
514tim_reg_base
515*/
516
517void timer_set_ti1_ch1(uint32_t timer_peripheral)
518{
519 TIM_CR2(timer_peripheral) &= ~TIM_CR2_TI1S;
520}
521
522/*---------------------------------------------------------------------------*/
523/** @brief Set the Master Mode
524
525This sets the Trigger Output TRGO for synchronizing with slave timers or
526passing as an internal trigger to the ADC or DAC.
527
528@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
529tim_reg_base
530@param[in] mode Unsigned int32. Master Mode @ref tim_mastermode
531*/
532
533void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode)
534{
535 TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK;
536 TIM_CR2(timer_peripheral) |= mode;
537}
538
539/*---------------------------------------------------------------------------*/
540/** @brief Set Timer DMA Requests on Capture/Compare Events.
541
542Capture/compare events will cause DMA requests to be generated.
543
544@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
545tim_reg_base
546*/
547
548void timer_set_dma_on_compare_event(uint32_t timer_peripheral)
549{
550 TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCDS;
551}
552
553/*---------------------------------------------------------------------------*/
554/** @brief Set Timer DMA Requests on Update Events.
555
556Update events will cause DMA requests to be generated.
557
558@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
559tim_reg_base
560*/
561
562void timer_set_dma_on_update_event(uint32_t timer_peripheral)
563{
564 TIM_CR2(timer_peripheral) |= TIM_CR2_CCDS;
565}
566
567/*---------------------------------------------------------------------------*/
568/** @brief Enable Timer Capture/Compare Control Update with Trigger.
569
570If the capture/compare control bits CCxE, CCxNE and OCxM are set to be
571preloaded, they are updated by software generating the COMG event (@ref
572timer_generate_event) or when a rising edge occurs on the trigger input TRGI.
573
574@note This setting is only valid for the advanced timer channels with
575complementary outputs.
576
577@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
578tim_reg_base
579*/
580
582{
583 TIM_CR2(timer_peripheral) |= TIM_CR2_CCUS;
584}
585
586/*---------------------------------------------------------------------------*/
587/** @brief Disable Timer Capture/Compare Control Update with Trigger.
588
589If the capture/compare control bits CCxE, CCxNE and OCxM are set to be
590preloaded, they are updated by software generating the COMG event (@ref
591timer_generate_event).
592
593@note This setting is only valid for the advanced timer channels with
594complementary outputs.
595
596@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
597tim_reg_base
598*/
599
601{
602 TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCUS;
603}
604
605/*---------------------------------------------------------------------------*/
606/** @brief Enable Timer Capture/Compare Control Preload.
607
608The capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded
609when a COM event occurs.
610
611@note This setting is only valid for the advanced timer channels with
612complementary outputs.
613
614@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
615tim_reg_base
616*/
617
619{
620 TIM_CR2(timer_peripheral) |= TIM_CR2_CCPC;
621}
622
623/*---------------------------------------------------------------------------*/
624/** @brief Disable Timer Capture/Compare Control Preload.
625
626The capture/compare control bits CCxE, CCxNE and OCxM preload is disabled.
627
628@note This setting is only valid for the advanced timer channels with
629complementary outputs.
630
631@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
632tim_reg_base
633*/
634
636{
637 TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCPC;
638}
639
640/*---------------------------------------------------------------------------*/
641/** @brief Set the Value for the Timer Prescaler.
642
643The timer clock is prescaled by the 16 bit scale value plus 1.
644
645@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
646tim_reg_base
647@param[in] value Unsigned int32. Prescaler values 0...0xFFFF.
648*/
649
650void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value)
651{
652 TIM_PSC(timer_peripheral) = value;
653}
654
655/*---------------------------------------------------------------------------*/
656/** @brief Set the Value for the Timer Repetition Counter.
657
658A timer update event is generated only after the specified number of repeat
659count cycles have been completed.
660
661@note This setting is only valid for the advanced timers.
662
663@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
664tim_reg_base
665@param[in] value Unsigned int32. Repetition values 0...0xFF.
666*/
667
668void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value)
669{
670 TIM_RCR(timer_peripheral) = value;
671}
672
673/*---------------------------------------------------------------------------*/
674/** @brief Timer Set Period
675
676Specify the timer period in the auto-reload register.
677
678@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
679tim_reg_base
680@param[in] period Unsigned int32. Period in counter clock ticks.
681*/
682
683void timer_set_period(uint32_t timer_peripheral, uint32_t period)
684{
685 TIM_ARR(timer_peripheral) = period;
686}
687
688/*---------------------------------------------------------------------------*/
689/** @brief Timer Enable the Output Compare Clear Function
690
691When this is enabled, the output compare signal is cleared when a high is
692detected on the external trigger input. This works in the output compare and
693PWM modes only (not forced mode).
694The output compare signal remains off until the next update event.
695
696@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
697tim_reg_base
698@param[in] oc_id enum ::tim_oc_id OC channel designators
699 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
700*/
701
702void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id)
703{
704 switch (oc_id) {
705 case TIM_OC1:
706 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1CE;
707 break;
708 case TIM_OC2:
709 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2CE;
710 break;
711 case TIM_OC3:
712 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3CE;
713 break;
714 case TIM_OC4:
715 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4CE;
716 break;
717 case TIM_OC1N:
718 case TIM_OC2N:
719 case TIM_OC3N:
720 /* Ignoring as oc clear enable only applies to the whole
721 * channel.
722 */
723 break;
724 }
725}
726
727/*---------------------------------------------------------------------------*/
728/** @brief Timer Disable the Output Compare Clear Function
729
730@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
731tim_reg_base
732@param[in] oc_id enum ::tim_oc_id OC channel designators
733 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
734*/
735
736void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id)
737{
738 switch (oc_id) {
739 case TIM_OC1:
740 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1CE;
741 break;
742 case TIM_OC2:
743 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2CE;
744 break;
745 case TIM_OC3:
746 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3CE;
747 break;
748 case TIM_OC4:
749 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4CE;
750 break;
751 case TIM_OC1N:
752 case TIM_OC2N:
753 case TIM_OC3N:
754 /* Ignoring as oc clear enable only applies to the whole
755 * channel.
756 */
757 break;
758 }
759}
760
761/*---------------------------------------------------------------------------*/
762/** @brief Timer Enable the Output Compare Fast Mode
763
764When this is enabled, the output compare signal is forced to the compare state
765by a trigger input, independently of the compare match. This speeds up the
766setting of the output compare to 3 clock cycles as opposed to at least 5 in the
767slow mode. This works in the PWM1 and PWM2 modes only.
768
769@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
770tim_reg_base
771@param[in] oc_id enum ::tim_oc_id OC channel designators
772 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
773*/
774
775void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
776{
777 switch (oc_id) {
778 case TIM_OC1:
779 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1FE;
780 break;
781 case TIM_OC2:
782 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2FE;
783 break;
784 case TIM_OC3:
785 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3FE;
786 break;
787 case TIM_OC4:
788 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4FE;
789 break;
790 case TIM_OC1N:
791 case TIM_OC2N:
792 case TIM_OC3N:
793 /* Ignoring as fast enable only applies to the whole channel. */
794 break;
795 }
796}
797
798/*---------------------------------------------------------------------------*/
799/** @brief Timer Enable the Output Compare Slow Mode
800
801This disables the fast compare mode and the output compare depends on the
802counter and compare register values.
803
804@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
805tim_reg_base
806@param[in] oc_id enum ::tim_oc_id OC channel designators
807 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
808*/
809
810void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
811{
812 switch (oc_id) {
813 case TIM_OC1:
814 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1FE;
815 break;
816 case TIM_OC2:
817 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2FE;
818 break;
819 case TIM_OC3:
820 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3FE;
821 break;
822 case TIM_OC4:
823 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4FE;
824 break;
825 case TIM_OC1N:
826 case TIM_OC2N:
827 case TIM_OC3N:
828 /* Ignoring as this option applies to the whole channel. */
829 break;
830 }
831}
832
833/*---------------------------------------------------------------------------*/
834/** @brief Timer Set Output Compare Mode
835
836Specifies how the comparator output will respond to a compare match. The mode
837can be:
838@li Frozen - the output does not respond to a match.
839@li Active - the output assumes the active state on the first match.
840@li Inactive - the output assumes the inactive state on the first match.
841@li Toggle - The output switches between active and inactive states on each
842match.
843@li Force inactive. The output is forced low regardless of the compare state.
844@li Force active. The output is forced high regardless of the compare state.
845@li PWM1 - The output is active when the counter is less than the compare
846register contents and inactive otherwise.
847@li PWM2 - The output is inactive when the counter is less than the compare
848register contents and active otherwise.
849
850@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
851tim_reg_base
852@param[in] oc_id enum ::tim_oc_id OC channel designators
853 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
854@param[in] oc_mode enum ::tim_oc_mode. OC mode designators.
855 TIM_OCM_FROZEN, TIM_OCM_ACTIVE, TIM_OCM_INACTIVE,
856 TIM_OCM_TOGGLE, TIM_OCM_FORCE_LOW, TIM_OCM_FORCE_HIGH,
857 TIM_OCM_PWM1, TIM_OCM_PWM2
858*/
859
860void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
861 enum tim_oc_mode oc_mode)
862{
863 switch (oc_id) {
864 case TIM_OC1:
865 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK;
866 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC1S_OUT;
867 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1M_MASK;
868 switch (oc_mode) {
869 case TIM_OCM_FROZEN:
870 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FROZEN;
871 break;
872 case TIM_OCM_ACTIVE:
873 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_ACTIVE;
874 break;
875 case TIM_OCM_INACTIVE:
876 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_INACTIVE;
877 break;
878 case TIM_OCM_TOGGLE:
879 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_TOGGLE;
880 break;
882 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW;
883 break;
885 TIM_CCMR1(timer_peripheral) |=
887 break;
888 case TIM_OCM_PWM1:
889 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1;
890 break;
891 case TIM_OCM_PWM2:
892 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM2;
893 break;
894 }
895 break;
896 case TIM_OC2:
897 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK;
898 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC2S_OUT;
899 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2M_MASK;
900 switch (oc_mode) {
901 case TIM_OCM_FROZEN:
902 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FROZEN;
903 break;
904 case TIM_OCM_ACTIVE:
905 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_ACTIVE;
906 break;
907 case TIM_OCM_INACTIVE:
908 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_INACTIVE;
909 break;
910 case TIM_OCM_TOGGLE:
911 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_TOGGLE;
912 break;
914 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW;
915 break;
917 TIM_CCMR1(timer_peripheral) |=
919 break;
920 case TIM_OCM_PWM1:
921 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1;
922 break;
923 case TIM_OCM_PWM2:
924 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM2;
925 break;
926 }
927 break;
928 case TIM_OC3:
929 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
930 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_CC3S_OUT;
931 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK;
932 switch (oc_mode) {
933 case TIM_OCM_FROZEN:
934 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN;
935 break;
936 case TIM_OCM_ACTIVE:
937 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE;
938 break;
939 case TIM_OCM_INACTIVE:
940 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE;
941 break;
942 case TIM_OCM_TOGGLE:
943 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_TOGGLE;
944 break;
946 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW;
947 break;
949 TIM_CCMR2(timer_peripheral) |=
951 break;
952 case TIM_OCM_PWM1:
953 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1;
954 break;
955 case TIM_OCM_PWM2:
956 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM2;
957 break;
958 }
959 break;
960 case TIM_OC4:
961 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
962 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_CC4S_OUT;
963 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK;
964 switch (oc_mode) {
965 case TIM_OCM_FROZEN:
966 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN;
967 break;
968 case TIM_OCM_ACTIVE:
969 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE;
970 break;
971 case TIM_OCM_INACTIVE:
972 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE;
973 break;
974 case TIM_OCM_TOGGLE:
975 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_TOGGLE;
976 break;
978 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW;
979 break;
981 TIM_CCMR2(timer_peripheral) |=
983 break;
984 case TIM_OCM_PWM1:
985 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1;
986 break;
987 case TIM_OCM_PWM2:
988 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM2;
989 break;
990 }
991 break;
992 case TIM_OC1N:
993 case TIM_OC2N:
994 case TIM_OC3N:
995 /* Ignoring as this option applies to the whole channel. */
996 break;
997 }
998}
999
1000/*---------------------------------------------------------------------------*/
1001/** @brief Timer Enable the Output Compare Preload Register
1002
1003@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
1004tim_reg_base
1005@param[in] oc_id enum ::tim_oc_id OC channel designators
1006 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
1007*/
1008
1009void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id)
1010{
1011 switch (oc_id) {
1012 case TIM_OC1:
1013 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1PE;
1014 break;
1015 case TIM_OC2:
1016 TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2PE;
1017 break;
1018 case TIM_OC3:
1019 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3PE;
1020 break;
1021 case TIM_OC4:
1022 TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4PE;
1023 break;
1024 case TIM_OC1N:
1025 case TIM_OC2N:
1026 case TIM_OC3N:
1027 /* Ignoring as this option applies to the whole channel. */
1028 break;
1029 }
1030}
1031
1032/*---------------------------------------------------------------------------*/
1033/** @brief Timer Disable the Output Compare Preload Register
1034
1035@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
1036tim_reg_base
1037@param[in] oc_id enum ::tim_oc_id OC channel designators
1038 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action)
1039*/
1040
1041void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id)
1042{
1043 switch (oc_id) {
1044 case TIM_OC1:
1045 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1PE;
1046 break;
1047 case TIM_OC2:
1048 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2PE;
1049 break;
1050 case TIM_OC3:
1051 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3PE;
1052 break;
1053 case TIM_OC4:
1054 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4PE;
1055 break;
1056 case TIM_OC1N:
1057 case TIM_OC2N:
1058 case TIM_OC3N:
1059 /* Ignoring as this option applies to the whole channel. */
1060 break;
1061 }
1062}
1063
1064/*---------------------------------------------------------------------------*/
1065/** @brief Timer Set the Output Polarity High
1066
1067The polarity of the channel output is set active high.
1068
1069@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
1070tim_reg_base
1071@param[in] oc_id enum ::tim_oc_id OC channel designators
1072 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced
1073 timers 1 and 8)
1074*/
1075
1076void timer_set_oc_polarity_high(uint32_t timer_peripheral, enum tim_oc_id oc_id)
1077{
1078 switch (oc_id) {
1079 case TIM_OC1:
1080 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1P;
1081 break;
1082 case TIM_OC2:
1083 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2P;
1084 break;
1085 case TIM_OC3:
1086 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3P;
1087 break;
1088 case TIM_OC4:
1089 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4P;
1090 break;
1091 case TIM_OC1N:
1092 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NP;
1093 break;
1094 case TIM_OC2N:
1095 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NP;
1096 break;
1097 case TIM_OC3N:
1098 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NP;
1099 break;
1100 }
1101}
1102
1103/*---------------------------------------------------------------------------*/
1104/** @brief Timer Set the Output Polarity Low
1105
1106The polarity of the channel output is set active low.
1107
1108@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
1109tim_reg_base
1110@param[in] oc_id enum ::tim_oc_id OC channel designators
1111 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced
1112 timers 1 and 8)
1113*/
1114
1115void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id)
1116{
1117 switch (oc_id) {
1118 case TIM_OC1:
1119 TIM_CCER(timer_peripheral) |= TIM_CCER_CC1P;
1120 break;
1121 case TIM_OC2:
1122 TIM_CCER(timer_peripheral) |= TIM_CCER_CC2P;
1123 break;
1124 case TIM_OC3:
1125 TIM_CCER(timer_peripheral) |= TIM_CCER_CC3P;
1126 break;
1127 case TIM_OC4:
1128 TIM_CCER(timer_peripheral) |= TIM_CCER_CC4P;
1129 break;
1130 case TIM_OC1N:
1131 TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NP;
1132 break;
1133 case TIM_OC2N:
1134 TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NP;
1135 break;
1136 case TIM_OC3N:
1137 TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NP;
1138 break;
1139 }
1140}
1141
1142/*---------------------------------------------------------------------------*/
1143/** @brief Timer Enable the Output Compare
1144
1145The channel output compare functionality is enabled.
1146
1147@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
1148tim_reg_base
1149@param[in] oc_id enum ::tim_oc_id OC channel designators
1150 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced
1151 timers 1 and 8)
1152*/
1153
1154void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id)
1155{
1156 switch (oc_id) {
1157 case TIM_OC1:
1158 TIM_CCER(timer_peripheral) |= TIM_CCER_CC1E;
1159 break;
1160 case TIM_OC2:
1161 TIM_CCER(timer_peripheral) |= TIM_CCER_CC2E;
1162 break;
1163 case TIM_OC3:
1164 TIM_CCER(timer_peripheral) |= TIM_CCER_CC3E;
1165 break;
1166 case TIM_OC4:
1167 TIM_CCER(timer_peripheral) |= TIM_CCER_CC4E;
1168 break;
1169 case TIM_OC1N:
1170 TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NE;
1171 break;
1172 case TIM_OC2N:
1173 TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NE;
1174 break;
1175 case TIM_OC3N:
1176 TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NE;
1177 break;
1178 }
1179}
1180
1181/*---------------------------------------------------------------------------*/
1182/** @brief Timer Disable the Output Compare
1183
1184The channel output compare functionality is disabled.
1185
1186@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
1187tim_reg_base
1188@param[in] oc_id enum ::tim_oc_id OC channel designators
1189 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced
1190 timers 1 and 8)
1191*/
1192
1193void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id)
1194{
1195 switch (oc_id) {
1196 case TIM_OC1:
1197 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1E;
1198 break;
1199 case TIM_OC2:
1200 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2E;
1201 break;
1202 case TIM_OC3:
1203 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3E;
1204 break;
1205 case TIM_OC4:
1206 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4E;
1207 break;
1208 case TIM_OC1N:
1209 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NE;
1210 break;
1211 case TIM_OC2N:
1212 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NE;
1213 break;
1214 case TIM_OC3N:
1215 TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NE;
1216 break;
1217 }
1218}
1219
1220/*---------------------------------------------------------------------------*/
1221/** @brief Timer set Output Compare Idle State High
1222
1223@sa Similar function suitable for multiple OC idle state settings
1224@ref timer_set_output_idle_state
1225
1226@note This setting is only valid for the advanced timers.
1227
1228@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
1229tim_reg_base
1230@param[in] oc_id enum ::tim_oc_id OC channel designators
1231 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced
1232 timers 1 and 8)
1233*/
1234
1235void timer_set_oc_idle_state_set(uint32_t timer_peripheral,
1236 enum tim_oc_id oc_id)
1237{
1238 switch (oc_id) {
1239 case TIM_OC1:
1240 TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1;
1241 break;
1242 case TIM_OC1N:
1243 TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1N;
1244 break;
1245 case TIM_OC2:
1246 TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2;
1247 break;
1248 case TIM_OC2N:
1249 TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2N;
1250 break;
1251 case TIM_OC3:
1252 TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3;
1253 break;
1254 case TIM_OC3N:
1255 TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3N;
1256 break;
1257 case TIM_OC4:
1258 TIM_CR2(timer_peripheral) |= TIM_CR2_OIS4;
1259 break;
1260 }
1261}
1262
1263/*---------------------------------------------------------------------------*/
1264/** @brief Timer Set Output Compare Idle State Low
1265
1266@sa Similar function suitable for multiple OC idle state settings
1267@ref timer_reset_output_idle_state
1268
1269@note This setting is only valid for the advanced timers.
1270
1271@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
1272tim_reg_base
1273@param[in] oc_id enum ::tim_oc_id OC channel designators
1274 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced
1275 timers 1 and 8)
1276*/
1277
1278void timer_set_oc_idle_state_unset(uint32_t timer_peripheral,
1279 enum tim_oc_id oc_id)
1280{
1281 switch (oc_id) {
1282 case TIM_OC1:
1283 TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1;
1284 break;
1285 case TIM_OC1N:
1286 TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1N;
1287 break;
1288 case TIM_OC2:
1289 TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2;
1290 break;
1291 case TIM_OC2N:
1292 TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2N;
1293 break;
1294 case TIM_OC3:
1295 TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3;
1296 break;
1297 case TIM_OC3N:
1298 TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3N;
1299 break;
1300 case TIM_OC4:
1301 TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS4;
1302 break;
1303 }
1304}
1305
1306/*---------------------------------------------------------------------------*/
1307/** @brief Timer Set Output Compare Value
1308
1309This is a convenience function to set the OC preload register value for loading
1310to the compare register.
1311
1312@param[in] timer_peripheral Unsigned int32. Timer register address base @ref
1313 tim_reg_base (TIM9 .. TIM14 not yet supported here).
1314@param[in] oc_id enum ::tim_oc_id OC channel designators
1315 TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
1316@param[in] value Unsigned int32. Compare value.
1317*/
1318
1319void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id,
1320 uint32_t value)
1321{
1322 switch (oc_id) {
1323 case TIM_OC1:
1324 TIM_CCR1(timer_peripheral) = value;
1325 break;
1326 case TIM_OC2:
1327 TIM_CCR2(timer_peripheral) = value;
1328 break;
1329 case TIM_OC3:
1330 TIM_CCR3(timer_peripheral) = value;
1331 break;
1332 case TIM_OC4:
1333 TIM_CCR4(timer_peripheral) = value;
1334 break;
1335 case TIM_OC1N:
1336 case TIM_OC2N:
1337 case TIM_OC3N:
1338 /* Ignoring as this option applies to the whole channel. */
1339 break;
1340 }
1341}
1342
1343/*---------------------------------------------------------------------------*/
1344/** @brief Enable Output in Break
1345
1346Enables the output in the Break feature of an advanced timer. This does not
1347enable the break functionality itself but only sets the Master Output Enable in
1348the Break and Deadtime Register.
1349
1350@note Not all timers support Break/Deadtime features
1351
1352@note It is necessary to call this function to enable the output on an advanced
1353timer <b>even if break or deadtime features are not being used</b>.
1354
1355@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1356TIM8
1357*/
1358
1359void timer_enable_break_main_output(uint32_t timer_peripheral)
1360{
1361 TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE;
1362}
1363
1364/*---------------------------------------------------------------------------*/
1365/** @brief Disable Output in Break
1366
1367Disables the output in the Break feature of an advanced timer. This clears
1368the Master Output Enable in the Break and Deadtime Register.
1369
1370@note Not all timers support Break/Deadtime features
1371
1372@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1373TIM8
1374*/
1375
1376void timer_disable_break_main_output(uint32_t timer_peripheral)
1377{
1378 TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE;
1379}
1380
1381/*---------------------------------------------------------------------------*/
1382/** @brief Enable Automatic Output in Break
1383
1384Enables the automatic output feature of the Break function of an advanced
1385timer so that the output is re-enabled at the next update event following a
1386break event.
1387
1388@note Not all timers support Break/Deadtime features
1389
1390@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1391TIM8
1392*/
1393
1394void timer_enable_break_automatic_output(uint32_t timer_peripheral)
1395{
1396 TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE;
1397}
1398
1399/*---------------------------------------------------------------------------*/
1400/** @brief Disable Automatic Output in Break
1401
1402Disables the automatic output feature of the Break function of an advanced
1403timer so that the output is re-enabled at the next update event following a
1404break event.
1405
1406@note Not all timers support Break/Deadtime features
1407
1408@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1409TIM8
1410*/
1411
1412void timer_disable_break_automatic_output(uint32_t timer_peripheral)
1413{
1414 TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE;
1415}
1416
1417/*---------------------------------------------------------------------------*/
1418/** @brief Activate Break when Input High
1419
1420Sets the break function to activate when the break input becomes high.
1421
1422@note Not all timers support Break/Deadtime features
1423
1424@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1425TIM8
1426*/
1427
1428void timer_set_break_polarity_high(uint32_t timer_peripheral)
1429{
1430 TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP;
1431}
1432
1433/*---------------------------------------------------------------------------*/
1434/** @brief Activate Break when Input Low
1435
1436Sets the break function to activate when the break input becomes low.
1437
1438@note Not all timers support Break/Deadtime features
1439
1440@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1441TIM8
1442*/
1443
1444void timer_set_break_polarity_low(uint32_t timer_peripheral)
1445{
1446 TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP;
1447}
1448
1449/*---------------------------------------------------------------------------*/
1450/** @brief Enable Break
1451
1452Enables the break function of an advanced timer.
1453
1454@note Not all timers support Break/Deadtime features
1455
1456@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1457TIM8
1458*/
1459
1460void timer_enable_break(uint32_t timer_peripheral)
1461{
1462 TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE;
1463}
1464
1465/*---------------------------------------------------------------------------*/
1466/** @brief Disable Break
1467
1468Disables the break function of an advanced timer.
1469
1470@note Not all timers support Break/Deadtime features
1471
1472@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1473TIM8
1474*/
1475
1476void timer_disable_break(uint32_t timer_peripheral)
1477{
1478 TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE;
1479}
1480
1481/*---------------------------------------------------------------------------*/
1482/** @brief Enable Off-State in Run Mode
1483
1484Enables the off-state in run mode for the break function of an advanced
1485timer in which the complementary outputs have been configured. It has no effect
1486if no complementary output is present. When the capture-compare output is
1487disabled while the complementary output is enabled, the output is set to its
1488inactive level as defined by the output polarity.
1489
1490@note Not all timers support Break/Deadtime features
1491
1492@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1493TIM8
1494*/
1495
1496void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral)
1497{
1498 TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR;
1499}
1500
1501/*---------------------------------------------------------------------------*/
1502/** @brief Disable Off-State in Run Mode
1503
1504Disables the off-state in run mode for the break function of an advanced
1505timer in which the complementary outputs have been configured. It has no effect
1506if no complementary output is present. When the capture-compare output is
1507disabled, the output is also disabled.
1508
1509@note Not all timers support Break/Deadtime features
1510
1511@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1512TIM8
1513*/
1514
1515void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral)
1516{
1517 TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR;
1518}
1519
1520/*---------------------------------------------------------------------------*/
1521/** @brief Enable Off-State in Idle Mode
1522
1523Enables the off-state in idle mode for the break function of an advanced
1524timer. When the master output is disabled the output is set to its
1525inactive level as defined by the output polarity.
1526
1527@note Not all timers support Break/Deadtime features
1528
1529@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1530TIM8
1531*/
1532
1533void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral)
1534{
1535 TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI;
1536}
1537
1538/*---------------------------------------------------------------------------*/
1539/** @brief Disable Off-State in Idle Mode
1540
1541Disables the off-state in idle mode for the break function of an advanced
1542timer. When the master output is disabled the output is also disabled.
1543
1544@note Not all timers support Break/Deadtime features
1545
1546@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1547TIM8
1548*/
1549
1550void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral)
1551{
1552 TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI;
1553}
1554
1555/*---------------------------------------------------------------------------*/
1556/** @brief Set Lock Bits
1557
1558Set the lock bits for an advanced timer. Three levels of lock providing
1559protection against software errors. Once written they cannot be changed until a
1560timer reset has occurred.
1561
1562@note Not all timers support Break/Deadtime features
1563
1564@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1565TIM8
1566@param[in] lock Unsigned int32. Lock specification @ref tim_lock
1567*/
1568
1569void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock)
1570{
1571 TIM_BDTR(timer_peripheral) |= lock;
1572}
1573
1574/*---------------------------------------------------------------------------*/
1575/** @brief Set Deadtime
1576
1577The deadtime and sampling clock (DTSC) is set in the clock division ratio part
1578of the timer mode settings. The deadtime count is an 8 bit value defined in
1579terms of the number of DTSC cycles:
1580
1581@li Bit 7 = 0, deadtime = bits(6:0)
1582@li Bits 7:6 = 10, deadtime = 2x(64+bits(5:0))
1583@li Bits 7:5 = 110, deadtime = 8x(32+bits(5:0))
1584@li Bits 7:5 = 111, deadtime = 16x(32+bits(5:0))
1585
1586@note Not all timers support Break/Deadtime features
1587
1588@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
1589TIM8
1590@param[in] deadtime Unsigned int32. Deadtime count specification as defined
1591above.
1592*/
1593
1594void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime)
1595{
1596 TIM_BDTR(timer_peripheral) |= deadtime;
1597}
1598
1599/*---------------------------------------------------------------------------*/
1600/** @brief Force generate a timer event.
1601
1602The event specification consists of 8 possible events that can be forced on the
1603timer. The forced events are automatically cleared by hardware. The UG event is
1604useful to cause shadow registers to be preloaded before the timer is started to
1605avoid uncertainties in the first cycle in case an update event may never be
1606generated.
1607
1608@param[in] timer_peripheral Unsigned int32. Timer register address base
1609@param[in] event Unsigned int32. Event specification @ref tim_event_gen
1610*/
1611
1612void timer_generate_event(uint32_t timer_peripheral, uint32_t event)
1613{
1614 TIM_EGR(timer_peripheral) |= event;
1615}
1616
1617/*---------------------------------------------------------------------------*/
1618/** @brief Read Counter
1619
1620Read back the value of a timer's counter register contents
1621
1622@param[in] timer_peripheral Unsigned int32. Timer register address base
1623@returns Unsigned int32. Counter value.
1624*/
1625
1626uint32_t timer_get_counter(uint32_t timer_peripheral)
1627{
1628 return TIM_CNT(timer_peripheral);
1629}
1630
1631/*---------------------------------------------------------------------------*/
1632/** @brief Set Counter
1633
1634Set the value of a timer's counter register contents.
1635
1636@param[in] timer_peripheral Unsigned int32. Timer register address base
1637@param[in] count Unsigned int32. Counter value.
1638*/
1639
1640void timer_set_counter(uint32_t timer_peripheral, uint32_t count)
1641{
1642 TIM_CNT(timer_peripheral) = count;
1643}
1644
1645/*---------------------------------------------------------------------------*/
1646/** @brief Set Input Capture Filter Parameters
1647
1648Set the input filter parameters for an input channel, specifying:
1649@li the frequency of sampling from the Deadtime and Sampling clock
1650(@see @ref timer_set_clock_division)
1651@li the number of events that must occur before a transition is considered
1652valid.
1653
1654@param[in] timer_peripheral Unsigned int32. Timer register address base
1655@param[in] ic ::tim_ic_id. Input Capture channel designator.
1656@param[in] flt ::tim_ic_filter. Input Capture Filter identifier.
1657*/
1658
1659void timer_ic_set_filter(uint32_t timer_peripheral, enum tim_ic_id ic,
1660 enum tim_ic_filter flt)
1661{
1662 switch (ic) {
1663 case TIM_IC1:
1664 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC1F_MASK;
1665 TIM_CCMR1(timer_peripheral) |= flt << 4;
1666 break;
1667 case TIM_IC2:
1668 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC2F_MASK;
1669 TIM_CCMR1(timer_peripheral) |= flt << 12;
1670 break;
1671 case TIM_IC3:
1672 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC3F_MASK;
1673 TIM_CCMR2(timer_peripheral) |= flt << 4;
1674 break;
1675 case TIM_IC4:
1676 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC4F_MASK;
1677 TIM_CCMR2(timer_peripheral) |= flt << 12;
1678 break;
1679 }
1680}
1681
1682/*---------------------------------------------------------------------------*/
1683/** @brief Set Input Capture Prescaler
1684
1685Set the number of events between each capture.
1686
1687@param[in] timer_peripheral Unsigned int32. Timer register address base
1688@param[in] ic ::tim_ic_id. Input Capture channel designator.
1689@param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler.
1690*/
1691
1692void timer_ic_set_prescaler(uint32_t timer_peripheral, enum tim_ic_id ic,
1693 enum tim_ic_psc psc)
1694{
1695 switch (ic) {
1696 case TIM_IC1:
1697 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC1PSC_MASK;
1698 TIM_CCMR1(timer_peripheral) |= psc << 2;
1699 break;
1700 case TIM_IC2:
1701 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC2PSC_MASK;
1702 TIM_CCMR1(timer_peripheral) |= psc << 10;
1703 break;
1704 case TIM_IC3:
1705 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC3PSC_MASK;
1706 TIM_CCMR2(timer_peripheral) |= psc << 2;
1707 break;
1708 case TIM_IC4:
1709 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC4PSC_MASK;
1710 TIM_CCMR2(timer_peripheral) |= psc << 10;
1711 break;
1712 }
1713}
1714
1715/*---------------------------------------------------------------------------*/
1716/** @brief Set Capture/Compare Channel Direction/Input
1717
1718The Capture/Compare channel is defined as output (compare) or input with the
1719input mapping specified:
1720
1721@li channel is configured as output
1722@li channel is configured as input and mapped on corresponding input
1723@li channel is configured as input and mapped on alternate input
1724(TI2 for channel 1, TI1 for channel 2, TI4 for channel 3, TI3 for channel 4)
1725@li channel is configured as input and is mapped on TRC (requires an
1726internal trigger input selected through TS bit
1727
1728@note not all combinations of the input and channel are valid, see datasheets.
1729@note these parameters are writable only when the channel is off.
1730
1731@param[in] timer_peripheral Unsigned int32. Timer register address base
1732@param[in] ic ::tim_ic_id. Input Capture channel designator.
1733@param[in] in ::tim_ic_input. Input Capture channel direction and source input.
1734*/
1735
1736void timer_ic_set_input(uint32_t timer_peripheral, enum tim_ic_id ic,
1737 enum tim_ic_input in)
1738{
1739 in &= 3;
1740
1741 if (((ic == TIM_IC2) || (ic == TIM_IC4)) &&
1742 ((in == TIM_IC_IN_TI1) || (in == TIM_IC_IN_TI2))) {
1743 /* Input select bits are flipped for these combinations */
1744 in ^= 3;
1745 }
1746
1747 switch (ic) {
1748 case TIM_IC1:
1749 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK;
1750 TIM_CCMR1(timer_peripheral) |= in;
1751 break;
1752 case TIM_IC2:
1753 TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK;
1754 TIM_CCMR1(timer_peripheral) |= in << 8;
1755 break;
1756 case TIM_IC3:
1757 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
1758 TIM_CCMR2(timer_peripheral) |= in;
1759 break;
1760 case TIM_IC4:
1761 TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
1762 TIM_CCMR2(timer_peripheral) |= in << 8;
1763 break;
1764 }
1765}
1766
1767/*---------------------------------------------------------------------------*/
1768/** @brief Enable Timer Input Capture
1769
1770@param[in] timer_peripheral Unsigned int32. Timer register address base
1771@param[in] ic ::tim_ic_id. Input Capture channel designator.
1772*/
1773
1774void timer_ic_enable(uint32_t timer_peripheral, enum tim_ic_id ic)
1775{
1776 TIM_CCER(timer_peripheral) |= (0x1 << (ic * 4));
1777}
1778
1779/*---------------------------------------------------------------------------*/
1780/** @brief Disable Timer Input Capture
1781
1782@param[in] timer_peripheral Unsigned int32. Timer register address base
1783@param[in] ic ::tim_ic_id. Input Capture channel designator.
1784*/
1785
1786void timer_ic_disable(uint32_t timer_peripheral, enum tim_ic_id ic)
1787{
1788 TIM_CCER(timer_peripheral) &= ~(0x1 << (ic * 4));
1789}
1790
1791/*---------------------------------------------------------------------------*/
1792/** @brief Set External Trigger Filter Parameters for Slave
1793
1794Set the input filter parameters for the external trigger, specifying:
1795@li the frequency of sampling from the Deadtime and Sampling clock
1796(@see @ref timer_set_clock_division)
1797@li the number of events that must occur before a transition is considered
1798valid.
1799
1800@param[in] timer_peripheral Unsigned int32. Timer register address base
1801@param[in] flt ::tim_ic_filter. Input Capture Filter identifier.
1802*/
1803
1804void timer_slave_set_filter(uint32_t timer_peripheral, enum tim_ic_filter flt)
1805{
1806 TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETF_MASK;
1807 TIM_SMCR(timer_peripheral) |= flt << 8;
1808}
1809
1810/*---------------------------------------------------------------------------*/
1811/** @brief Set External Trigger Prescaler for Slave
1812
1813Set the external trigger frequency division ratio.
1814
1815@param[in] timer_peripheral Unsigned int32. Timer register address base
1816@param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler.
1817*/
1818
1819void timer_slave_set_prescaler(uint32_t timer_peripheral, enum tim_ic_psc psc)
1820{
1821 TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETPS_MASK;
1822 TIM_SMCR(timer_peripheral) |= psc << 12;
1823}
1824
1825/*---------------------------------------------------------------------------*/
1826/** @brief Set External Trigger Polarity for Slave
1827
1828@param[in] timer_peripheral Unsigned int32. Timer register address base
1829@param[in] pol ::tim_et_pol. Slave External Trigger polarity.
1830*/
1831
1832void timer_slave_set_polarity(uint32_t timer_peripheral, enum tim_et_pol pol)
1833{
1834 if (pol) {
1835 TIM_SMCR(timer_peripheral) |= TIM_SMCR_ETP;
1836 } else {
1837 TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETP;
1838 }
1839}
1840
1841/*---------------------------------------------------------------------------*/
1842/** @brief Set Slave Mode
1843
1844@param[in] timer_peripheral Unsigned int32. Timer register address base
1845@param[in] mode Unsigned int8. Slave mode @ref tim_sms
1846*/
1847
1848void timer_slave_set_mode(uint32_t timer_peripheral, uint8_t mode)
1849{
1850 TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_SMS_MASK;
1851 TIM_SMCR(timer_peripheral) |= mode;
1852}
1853
1854/*---------------------------------------------------------------------------*/
1855/** @brief Set Slave Trigger Source
1856
1857@param[in] timer_peripheral Unsigned int32. Timer register address base
1858@param[in] trigger Unsigned int8. Slave trigger source @ref tim_ts
1859*/
1860
1861void timer_slave_set_trigger(uint32_t timer_peripheral, uint8_t trigger)
1862{
1863 TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_TS_MASK;
1864 TIM_SMCR(timer_peripheral) |= trigger;
1865}
1866
1867/*---------------------------------------------------------------------------*/
1868/** @brief Set External Clock Mode 2
1869
1870@param[in] timer_peripheral Unsigned int32. Timer register address base
1871@param[in] state ::tim_ecm2_state. External Clock Mode 2 state
1872*/
1873
1874void timer_slave_set_extclockmode2(uint32_t timer_peripheral,
1875 enum tim_ecm2_state state)
1876{
1877 if (state) {
1878 TIM_SMCR(timer_peripheral) |= TIM_SMCR_ECE;
1879 } else {
1880 TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ECE;
1881 }
1882}
1883
1884/* TODO Timer DMA burst */
1885
1886/**@}*/
1887
#define TIM_SR_BIF
Break interrupt flag.
#define TIM_CR1_CKD_CK_INT_MASK
#define TIM_CR1_CMS_MASK
#define TIM_CR1_DIR_DOWN
#define TIM_CR2_OIS3N
Output idle state 3 (OC3N output)
#define TIM_CR2_OIS1
Output idle state 1 (OC1 output)
#define TIM_CR2_OIS_MASK
#define TIM_CR2_OIS2
Output idle state 2 (OC2 output)
#define TIM_CR2_OIS2N
Output idle state 2 (OC2N output)
#define TIM_CR2_OIS4
Output idle state 4 (OC4 output)
#define TIM_CR2_OIS3
Output idle state 3 (OC3 output)
#define TIM_CR2_OIS1N
Output idle state 1 (OC1N output)
#define TIM_CCMR2_CC4S_OUT
#define TIM_CCMR2_OC4M_TOGGLE
#define TIM_CR1_URS
#define TIM_CCMR2_OC4M_FORCE_HIGH
#define TIM_CCER_CC1P
#define TIM_CCMR2_OC4CE
#define TIM_CCR4(tim_base)
#define TIM_CCMR1_OC2CE
#define TIM_CCMR1_OC1PE
#define TIM_CCMR2_OC3M_FORCE_HIGH
#define TIM_CCER_CC3E
#define TIM_PSC(tim_base)
#define TIM_CCMR2_OC3PE
#define TIM_BDTR_MOE
#define TIM_SMCR_ETP
#define TIM_CCER_CC2P
tim_ic_psc
Input Capture input prescaler.
#define TIM_BDTR_BKP
#define TIM_SMCR_ECE
#define TIM_CCMR2_OC4M_PWM2
#define TIM_CCER_CC2NP
#define TIM_CCMR1_OC2M_PWM2
#define TIM_CCMR1_OC1M_INACTIVE
#define TIM_CCMR1_OC2FE
#define TIM_CCMR1_OC1M_PWM2
#define TIM_CCMR2_OC4PE
#define TIM_CCR2(tim_base)
#define TIM_EGR(tim_base)
#define TIM_CCER_CC1E
#define TIM_CCER_CC4P
#define TIM_CCER_CC3NP
#define TIM_CCER_CC1NP
#define TIM_CR2(tim_base)
#define TIM_CCMR2_OC3CE
#define TIM_CCMR1_OC1M_PWM1
#define TIM_CR1_ARPE
#define TIM_CCMR1_OC1M_TOGGLE
#define TIM_CCMR1_OC2M_FROZEN
#define TIM_CCMR2_CC3S_OUT
#define TIM_CCMR2_OC3M_PWM1
#define TIM_BDTR_AOE
#define TIM_CCER_CC3P
#define TIM_CCMR2_OC4M_INACTIVE
#define TIM_CCER_CC2NE
#define TIM_CCMR1_OC1M_FORCE_HIGH
#define TIM_CR1_OPM
#define TIM_CCMR2_OC4M_ACTIVE
#define TIM_CCMR2_OC4FE
#define TIM_CCMR2_OC3M_ACTIVE
#define TIM_CCMR2_OC3M_FORCE_LOW
#define TIM_BDTR_BKE
#define TIM_CCER_CC2E
#define TIM_CCMR2_OC4M_PWM1
#define TIM_CCER_CC1NE
#define TIM_CCR1(tim_base)
#define TIM_CNT(tim_base)
#define TIM_CCMR1_OC1M_ACTIVE
tim_ic_filter
Input Capture input filter.
#define TIM_CCMR1_OC2M_PWM1
#define TIM_CCMR1_OC1CE
#define TIM_CCMR1_OC2M_INACTIVE
#define TIM_CCMR2_OC3M_TOGGLE
#define TIM_CR1_CEN
#define TIM_CCER_CC4E
#define TIM_CCMR2_OC3M_FROZEN
#define TIM_ARR(tim_base)
tim_oc_mode
Output Compare mode designators.
#define TIM_CCMR1_CC2S_OUT
tim_et_pol
Slave external trigger polarity.
#define TIM_CR1_UDIS
#define TIM_CCR3(tim_base)
#define TIM_CR2_CCPC
#define TIM_CCMR1_OC2M_TOGGLE
#define TIM_CCER(tim_base)
#define TIM_BDTR_OSSI
#define TIM_SMCR(tim_base)
#define TIM_CCMR2_OC4M_FROZEN
#define TIM_CCMR1_OC1FE
#define TIM_CR1(tim_base)
#define TIM_CCMR1_OC2PE
#define TIM_CCMR2(tim_base)
tim_oc_id
Output Compare channel designators.
#define TIM_CCMR1(tim_base)
#define TIM_CCMR1_OC1M_FROZEN
#define TIM_CR2_TI1S
#define TIM_BDTR(tim_base)
#define TIM_CCMR1_OC2M_FORCE_HIGH
tim_ecm2_state
External clock mode 2.
tim_ic_input
Input Capture input source.
#define TIM_CCER_CC3NE
#define TIM_RCR(tim_base)
#define TIM_SR(tim_base)
#define TIM_CCMR2_OC3M_INACTIVE
#define TIM_CR2_CCDS
#define TIM_CCMR1_OC2M_ACTIVE
#define TIM_CCMR2_OC3FE
#define TIM_CCMR1_OC2M_FORCE_LOW
#define TIM_CCMR1_CC1S_OUT
#define TIM_CR2_CCUS
#define TIM_CCMR1_OC1M_FORCE_LOW
tim_ic_id
Input Capture channel designators.
#define TIM_BDTR_OSSR
#define TIM_DIER(tim_base)
#define TIM_CCMR2_OC3M_PWM2
#define TIM_CCMR2_OC4M_FORCE_LOW
@ TIM_OCM_FROZEN
@ TIM_OCM_FORCE_LOW
@ TIM_OCM_INACTIVE
@ TIM_OCM_FORCE_HIGH
@ TIM_OCM_PWM2
@ TIM_OCM_TOGGLE
@ TIM_OCM_PWM1
@ TIM_OCM_ACTIVE
@ TIM_OC1N
@ TIM_OC4
@ TIM_OC1
@ TIM_OC3N
@ TIM_OC3
@ TIM_OC2
@ TIM_OC2N
@ TIM_IC_IN_TI2
@ TIM_IC_IN_TI1
@ TIM_IC1
@ TIM_IC2
@ TIM_IC3
@ TIM_IC4
void timer_continuous_mode(uint32_t timer_peripheral)
Enable the Timer to Run Continuously.
void timer_slave_set_trigger(uint32_t timer_peripheral, uint8_t trigger)
Set Slave Trigger Source.
void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Enable the Output Compare Slow Mode.
void timer_enable_preload(uint32_t timer_peripheral)
Enable Auto-Reload Buffering.
void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs)
Set Timer Output Idle States Low.
void timer_one_shot_mode(uint32_t timer_peripheral)
Enable the Timer for One Cycle and Stop.
void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode)
Set the Master Mode.
void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral)
Disable Timer Capture/Compare Control Preload.
void timer_set_dma_on_compare_event(uint32_t timer_peripheral)
Set Timer DMA Requests on Capture/Compare Events.
void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Enable the Output Compare Fast Mode.
void timer_update_on_overflow(uint32_t timer_peripheral)
Set the Timer to Generate Update IRQ or DMA only from Under/Overflow Events.
void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral)
Disable Off-State in Idle Mode.
void timer_slave_set_mode(uint32_t timer_peripheral, uint8_t mode)
Set Slave Mode.
bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag)
Read a Status Flag.
void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral)
Enable Timer Capture/Compare Control Update with Trigger.
void timer_disable_break_main_output(uint32_t timer_peripheral)
Disable Output in Break.
void timer_enable_break(uint32_t timer_peripheral)
Enable Break.
void timer_set_oc_polarity_high(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Set the Output Polarity High.
void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div, uint32_t alignment, uint32_t direction)
Set the Timer Mode.
void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Disable the Output Compare Clear Function.
void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock)
Set Lock Bits.
void timer_disable_preload(uint32_t timer_peripheral)
Disable Auto-Reload Buffering.
void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value)
Set the Value for the Timer Prescaler.
void timer_disable_counter(uint32_t timer_peripheral)
Stop the timer from counting.
void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Enable the Output Compare Clear Function.
void timer_set_break_polarity_high(uint32_t timer_peripheral)
Activate Break when Input High.
void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode)
Timer Set Output Compare Mode.
void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Set Output Compare Idle State Low.
void timer_ic_disable(uint32_t timer_peripheral, enum tim_ic_id ic)
Disable Timer Input Capture.
bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag)
Return Interrupt Source.
void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime)
Set Deadtime.
void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment)
Specify the counter alignment mode.
void timer_slave_set_polarity(uint32_t timer_peripheral, enum tim_et_pol pol)
Set External Trigger Polarity for Slave.
void timer_set_counter(uint32_t timer_peripheral, uint32_t count)
Set Counter.
void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Enable the Output Compare Preload Register.
void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs)
Set Timer Output Idle States High.
void timer_set_dma_on_update_event(uint32_t timer_peripheral)
Set Timer DMA Requests on Update Events.
void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral)
Enable Off-State in Idle Mode.
void timer_enable_update_event(uint32_t timer_peripheral)
Enable Timer Update Events.
void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral)
Enable Timer Capture/Compare Control Preload.
void timer_enable_counter(uint32_t timer_peripheral)
Enable the timer to start counting.
void timer_ic_set_prescaler(uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_psc psc)
Set Input Capture Prescaler.
void timer_ic_set_filter(uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_filter flt)
Set Input Capture Filter Parameters.
void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Disable the Output Compare.
void timer_set_ti1_ch1(uint32_t timer_peripheral)
Set Timer 1 Input to Channel 1.
void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer set Output Compare Idle State High.
void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Disable the Output Compare Preload Register.
void timer_direction_down(uint32_t timer_peripheral)
Set the Timer to Count Down.
void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral)
Disable Timer Capture/Compare Control Update with Trigger.
void timer_update_on_any(uint32_t timer_peripheral)
Set the Timer to Generate Update IRQ or DMA on any Event.
void timer_disable_break(uint32_t timer_peripheral)
Disable Break.
void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq)
Enable Interrupts for a Timer.
void timer_enable_break_automatic_output(uint32_t timer_peripheral)
Enable Automatic Output in Break.
void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral)
Enable Off-State in Run Mode.
void timer_direction_up(uint32_t timer_peripheral)
Set the Timer to Count Up.
void timer_enable_break_main_output(uint32_t timer_peripheral)
Enable Output in Break.
void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral)
Disable Off-State in Run Mode.
void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Enable the Output Compare.
void timer_disable_update_event(uint32_t timer_peripheral)
Disable Timer Update Events.
void timer_set_ti1_ch123_xor(uint32_t timer_peripheral)
Set Timer 1 Input to XOR of Three Channels.
void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value)
Timer Set Output Compare Value.
void timer_slave_set_prescaler(uint32_t timer_peripheral, enum tim_ic_psc psc)
Set External Trigger Prescaler for Slave.
void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Set the Output Polarity Low.
void timer_ic_set_input(uint32_t timer_peripheral, enum tim_ic_id ic, enum tim_ic_input in)
Set Capture/Compare Channel Direction/Input.
void timer_disable_break_automatic_output(uint32_t timer_peripheral)
Disable Automatic Output in Break.
void timer_ic_enable(uint32_t timer_peripheral, enum tim_ic_id ic)
Enable Timer Input Capture.
void timer_set_break_polarity_low(uint32_t timer_peripheral)
Activate Break when Input Low.
uint32_t timer_get_counter(uint32_t timer_peripheral)
Read Counter.
void timer_generate_event(uint32_t timer_peripheral, uint32_t event)
Force generate a timer event.
void timer_slave_set_extclockmode2(uint32_t timer_peripheral, enum tim_ecm2_state state)
Set External Clock Mode 2.
void timer_set_period(uint32_t timer_peripheral, uint32_t period)
Timer Set Period.
void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value)
Set the Value for the Timer Repetition Counter.
void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag)
Clear a Status Flag.
void timer_slave_set_filter(uint32_t timer_peripheral, enum tim_ic_filter flt)
Set External Trigger Filter Parameters for Slave.
void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq)
Disable Interrupts for a Timer.
void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div)
Set Input Filter and Dead-time Clock Divider Ratio.