libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
timer_common_all.h
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1 /** @addtogroup timer_defines
2  *
3  * @author @htmlonly &copy; @endhtmlonly 2009 Piotr Esden-Tempski <piotr@esden.net>
4  *
5  */
6 /*
7  * This file is part of the libopencm3 project.
8  *
9  * Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net>
10  *
11  * This library is free software: you can redistribute it and/or modify
12  * it under the terms of the GNU Lesser General Public License as published by
13  * the Free Software Foundation, either version 3 of the License, or
14  * (at your option) any later version.
15  *
16  * This library is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU Lesser General Public License for more details.
20  *
21  * You should have received a copy of the GNU Lesser General Public License
22  * along with this library. If not, see <http://www.gnu.org/licenses/>.
23  */
24 
25 /**@{*/
26 
27 /* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H
28 The order of header inclusion is important. timer.h includes the device
29 specific memorymap.h header before including this header file.*/
30 
31 #pragma once
32 /* --- Convenience macros -------------------------------------------------- */
33 
34 /* Timer register base addresses (for convenience) */
35 /****************************************************************************/
36 /** @defgroup tim_reg_base Timer register base addresses
37 @{*/
38 #define TIM1 TIM1_BASE
39 #define TIM2 TIM2_BASE
40 #define TIM3 TIM3_BASE
41 #if defined(TIM4_BASE)
42 #define TIM4 TIM4_BASE
43 #endif
44 #define TIM5 TIM5_BASE
45 #define TIM6 TIM6_BASE
46 #define TIM7 TIM7_BASE
47 #if defined(TIM8_BASE)
48 # define TIM8 TIM8_BASE
49 #endif
50 #if defined(TIM9_BASE)
51 # define TIM9 TIM9_BASE
52 #endif
53 #if defined(TIM10_BASE)
54 # define TIM10 TIM10_BASE
55 #endif
56 #if defined(TIM11_BASE)
57 # define TIM11 TIM11_BASE
58 #endif
59 #if defined(TIM12_BASE)
60 # define TIM12 TIM12_BASE
61 #endif
62 #if defined(TIM13_BASE)
63 # define TIM13 TIM13_BASE
64 #endif
65 #if defined(TIM14_BASE)
66 # define TIM14 TIM14_BASE
67 #endif
68 #if defined(TIM15_BASE)
69 # define TIM15 TIM15_BASE
70 #endif
71 #if defined(TIM16_BASE)
72 # define TIM16 TIM16_BASE
73 #endif
74 #if defined(TIM17_BASE)
75 # define TIM17 TIM17_BASE
76 #endif
77 #if defined(TIM21_BASE)
78 # define TIM21 TIM21_BASE
79 #endif
80 #if defined(TIM22_BASE)
81 # define TIM22 TIM22_BASE
82 #endif
83 /**@}*/
84 
85 /* --- Timer registers ----------------------------------------------------- */
86 
87 /* Control register 1 (TIMx_CR1) */
88 #define TIM_CR1(tim_base) MMIO32((tim_base) + 0x00)
89 #define TIM1_CR1 TIM_CR1(TIM1)
90 #define TIM2_CR1 TIM_CR1(TIM2)
91 #define TIM3_CR1 TIM_CR1(TIM3)
92 #define TIM4_CR1 TIM_CR1(TIM4)
93 #define TIM5_CR1 TIM_CR1(TIM5)
94 #define TIM6_CR1 TIM_CR1(TIM6)
95 #define TIM7_CR1 TIM_CR1(TIM7)
96 #define TIM8_CR1 TIM_CR1(TIM8)
97 #define TIM9_CR1 TIM_CR1(TIM9)
98 #define TIM10_CR1 TIM_CR1(TIM10)
99 #define TIM11_CR1 TIM_CR1(TIM11)
100 #define TIM12_CR1 TIM_CR1(TIM12)
101 #define TIM13_CR1 TIM_CR1(TIM13)
102 #define TIM14_CR1 TIM_CR1(TIM14)
103 #define TIM15_CR1 TIM_CR1(TIM15)
104 #define TIM16_CR1 TIM_CR1(TIM16)
105 #define TIM17_CR1 TIM_CR1(TIM17)
106 
107 /* Control register 2 (TIMx_CR2) */
108 #define TIM_CR2(tim_base) MMIO32((tim_base) + 0x04)
109 #define TIM1_CR2 TIM_CR2(TIM1)
110 #define TIM2_CR2 TIM_CR2(TIM2)
111 #define TIM3_CR2 TIM_CR2(TIM3)
112 #define TIM4_CR2 TIM_CR2(TIM4)
113 #define TIM5_CR2 TIM_CR2(TIM5)
114 #define TIM6_CR2 TIM_CR2(TIM6)
115 #define TIM7_CR2 TIM_CR2(TIM7)
116 #define TIM8_CR2 TIM_CR2(TIM8)
117 #define TIM15_CR2 TIM_CR2(TIM15)
118 #define TIM16_CR2 TIM_CR2(TIM16)
119 #define TIM17_CR2 TIM_CR2(TIM17)
120 
121 /* Slave mode control register (TIMx_SMCR) */
122 #define TIM_SMCR(tim_base) MMIO32((tim_base) + 0x08)
123 #define TIM1_SMCR TIM_SMCR(TIM1)
124 #define TIM2_SMCR TIM_SMCR(TIM2)
125 #define TIM3_SMCR TIM_SMCR(TIM3)
126 #define TIM4_SMCR TIM_SMCR(TIM4)
127 #define TIM5_SMCR TIM_SMCR(TIM5)
128 #define TIM8_SMCR TIM_SMCR(TIM8)
129 #define TIM9_SMCR TIM_SMCR(TIM9)
130 #define TIM12_SMCR TIM_SMCR(TIM12)
131 #define TIM15_SMCR TIM_SMCR(TIM15)
132 
133 /* DMA/Interrupt enable register (TIMx_DIER) */
134 #define TIM_DIER(tim_base) MMIO32((tim_base) + 0x0C)
135 #define TIM1_DIER TIM_DIER(TIM1)
136 #define TIM2_DIER TIM_DIER(TIM2)
137 #define TIM3_DIER TIM_DIER(TIM3)
138 #define TIM4_DIER TIM_DIER(TIM4)
139 #define TIM5_DIER TIM_DIER(TIM5)
140 #define TIM6_DIER TIM_DIER(TIM6)
141 #define TIM7_DIER TIM_DIER(TIM7)
142 #define TIM8_DIER TIM_DIER(TIM8)
143 #define TIM9_DIER TIM_DIER(TIM9)
144 #define TIM10_DIER TIM_DIER(TIM10)
145 #define TIM11_DIER TIM_DIER(TIM11)
146 #define TIM12_DIER TIM_DIER(TIM12)
147 #define TIM13_DIER TIM_DIER(TIM13)
148 #define TIM14_DIER TIM_DIER(TIM14)
149 #define TIM15_DIER TIM_DIER(TIM15)
150 #define TIM16_DIER TIM_DIER(TIM16)
151 #define TIM17_DIER TIM_DIER(TIM17)
152 
153 /* Status register (TIMx_SR) */
154 #define TIM_SR(tim_base) MMIO32((tim_base) + 0x10)
155 #define TIM1_SR TIM_SR(TIM1)
156 #define TIM2_SR TIM_SR(TIM2)
157 #define TIM3_SR TIM_SR(TIM3)
158 #define TIM4_SR TIM_SR(TIM4)
159 #define TIM5_SR TIM_SR(TIM5)
160 #define TIM6_SR TIM_SR(TIM6)
161 #define TIM7_SR TIM_SR(TIM7)
162 #define TIM8_SR TIM_SR(TIM8)
163 #define TIM9_SR TIM_SR(TIM9)
164 #define TIM10_SR TIM_SR(TIM10)
165 #define TIM11_SR TIM_SR(TIM11)
166 #define TIM12_SR TIM_SR(TIM12)
167 #define TIM13_SR TIM_SR(TIM13)
168 #define TIM14_SR TIM_SR(TIM14)
169 #define TIM15_SR TIM_SR(TIM15)
170 #define TIM16_SR TIM_SR(TIM16)
171 #define TIM17_SR TIM_SR(TIM17)
172 
173 /* Event generation register (TIMx_EGR) */
174 #define TIM_EGR(tim_base) MMIO32((tim_base) + 0x14)
175 #define TIM1_EGR TIM_EGR(TIM1)
176 #define TIM2_EGR TIM_EGR(TIM2)
177 #define TIM3_EGR TIM_EGR(TIM3)
178 #define TIM4_EGR TIM_EGR(TIM4)
179 #define TIM5_EGR TIM_EGR(TIM5)
180 #define TIM6_EGR TIM_EGR(TIM6)
181 #define TIM7_EGR TIM_EGR(TIM7)
182 #define TIM8_EGR TIM_EGR(TIM8)
183 #define TIM9_EGR TIM_EGR(TIM9)
184 #define TIM10_EGR TIM_EGR(TIM10)
185 #define TIM11_EGR TIM_EGR(TIM11)
186 #define TIM12_EGR TIM_EGR(TIM12)
187 #define TIM13_EGR TIM_EGR(TIM13)
188 #define TIM14_EGR TIM_EGR(TIM14)
189 #define TIM15_EGR TIM_EGR(TIM15)
190 #define TIM16_EGR TIM_EGR(TIM16)
191 #define TIM17_EGR TIM_EGR(TIM17)
192 
193 /* Capture/compare mode register 1 (TIMx_CCMR1) */
194 #define TIM_CCMR1(tim_base) MMIO32((tim_base) + 0x18)
195 #define TIM1_CCMR1 TIM_CCMR1(TIM1)
196 #define TIM2_CCMR1 TIM_CCMR1(TIM2)
197 #define TIM3_CCMR1 TIM_CCMR1(TIM3)
198 #define TIM4_CCMR1 TIM_CCMR1(TIM4)
199 #define TIM5_CCMR1 TIM_CCMR1(TIM5)
200 #define TIM8_CCMR1 TIM_CCMR1(TIM8)
201 #define TIM9_CCMR1 TIM_CCMR1(TIM9)
202 #define TIM10_CCMR1 TIM_CCMR1(TIM10)
203 #define TIM11_CCMR1 TIM_CCMR1(TIM11)
204 #define TIM12_CCMR1 TIM_CCMR1(TIM12)
205 #define TIM13_CCMR1 TIM_CCMR1(TIM13)
206 #define TIM14_CCMR1 TIM_CCMR1(TIM14)
207 #define TIM15_CCMR1 TIM_CCMR1(TIM15)
208 #define TIM16_CCMR1 TIM_CCMR1(TIM16)
209 #define TIM17_CCMR1 TIM_CCMR1(TIM17)
210 
211 /* Capture/compare mode register 2 (TIMx_CCMR2) */
212 #define TIM_CCMR2(tim_base) MMIO32((tim_base) + 0x1C)
213 #define TIM1_CCMR2 TIM_CCMR2(TIM1)
214 #define TIM2_CCMR2 TIM_CCMR2(TIM2)
215 #define TIM3_CCMR2 TIM_CCMR2(TIM3)
216 #define TIM4_CCMR2 TIM_CCMR2(TIM4)
217 #define TIM5_CCMR2 TIM_CCMR2(TIM5)
218 #define TIM8_CCMR2 TIM_CCMR2(TIM8)
219 
220 /* Capture/compare enable register (TIMx_CCER) */
221 #define TIM_CCER(tim_base) MMIO32((tim_base) + 0x20)
222 #define TIM1_CCER TIM_CCER(TIM1)
223 #define TIM2_CCER TIM_CCER(TIM2)
224 #define TIM3_CCER TIM_CCER(TIM3)
225 #define TIM4_CCER TIM_CCER(TIM4)
226 #define TIM5_CCER TIM_CCER(TIM5)
227 #define TIM8_CCER TIM_CCER(TIM8)
228 #define TIM9_CCER TIM_CCER(TIM9)
229 #define TIM10_CCER TIM_CCER(TIM10)
230 #define TIM11_CCER TIM_CCER(TIM11)
231 #define TIM12_CCER TIM_CCER(TIM12)
232 #define TIM13_CCER TIM_CCER(TIM13)
233 #define TIM14_CCER TIM_CCER(TIM14)
234 #define TIM15_CCER TIM_CCER(TIM15)
235 #define TIM16_CCER TIM_CCER(TIM16)
236 #define TIM17_CCER TIM_CCER(TIM17)
237 
238 /* Counter (TIMx_CNT) */
239 #define TIM_CNT(tim_base) MMIO32((tim_base) + 0x24)
240 #define TIM1_CNT TIM_CNT(TIM1)
241 #define TIM2_CNT TIM_CNT(TIM2)
242 #define TIM3_CNT TIM_CNT(TIM3)
243 #define TIM4_CNT TIM_CNT(TIM4)
244 #define TIM5_CNT TIM_CNT(TIM5)
245 #define TIM6_CNT TIM_CNT(TIM6)
246 #define TIM7_CNT TIM_CNT(TIM7)
247 #define TIM8_CNT TIM_CNT(TIM8)
248 #define TIM9_CNT TIM_CNT(TIM9)
249 #define TIM10_CNT TIM_CNT(TIM10)
250 #define TIM11_CNT TIM_CNT(TIM11)
251 #define TIM12_CNT TIM_CNT(TIM12)
252 #define TIM13_CNT TIM_CNT(TIM13)
253 #define TIM14_CNT TIM_CNT(TIM14)
254 #define TIM15_CNT TIM_CNT(TIM15)
255 #define TIM16_CNT TIM_CNT(TIM16)
256 #define TIM17_CNT TIM_CNT(TIM17)
257 
258 /* Prescaler (TIMx_PSC) */
259 #define TIM_PSC(tim_base) MMIO32((tim_base) + 0x28)
260 #define TIM1_PSC TIM_PSC(TIM1)
261 #define TIM2_PSC TIM_PSC(TIM2)
262 #define TIM3_PSC TIM_PSC(TIM3)
263 #define TIM4_PSC TIM_PSC(TIM4)
264 #define TIM5_PSC TIM_PSC(TIM5)
265 #define TIM6_PSC TIM_PSC(TIM6)
266 #define TIM7_PSC TIM_PSC(TIM7)
267 #define TIM8_PSC TIM_PSC(TIM8)
268 #define TIM9_PSC TIM_PSC(TIM9)
269 #define TIM10_PSC TIM_PSC(TIM10)
270 #define TIM11_PSC TIM_PSC(TIM11)
271 #define TIM12_PSC TIM_PSC(TIM12)
272 #define TIM13_PSC TIM_PSC(TIM13)
273 #define TIM14_PSC TIM_PSC(TIM14)
274 #define TIM15_PSC TIM_PSC(TIM15)
275 #define TIM16_PSC TIM_PSC(TIM16)
276 #define TIM17_PSC TIM_PSC(TIM17)
277 
278 /* Auto-reload register (TIMx_ARR) */
279 #define TIM_ARR(tim_base) MMIO32((tim_base) + 0x2C)
280 #define TIM1_ARR TIM_ARR(TIM1)
281 #define TIM2_ARR TIM_ARR(TIM2)
282 #define TIM3_ARR TIM_ARR(TIM3)
283 #define TIM4_ARR TIM_ARR(TIM4)
284 #define TIM5_ARR TIM_ARR(TIM5)
285 #define TIM6_ARR TIM_ARR(TIM6)
286 #define TIM7_ARR TIM_ARR(TIM7)
287 #define TIM8_ARR TIM_ARR(TIM8)
288 #define TIM9_ARR TIM_ARR(TIM9)
289 #define TIM10_ARR TIM_ARR(TIM10)
290 #define TIM11_ARR TIM_ARR(TIM11)
291 #define TIM12_ARR TIM_ARR(TIM12)
292 #define TIM13_ARR TIM_ARR(TIM13)
293 #define TIM14_ARR TIM_ARR(TIM14)
294 #define TIM15_ARR TIM_ARR(TIM15)
295 #define TIM16_ARR TIM_ARR(TIM16)
296 #define TIM17_ARR TIM_ARR(TIM17)
297 
298 /* Repetition counter register (TIMx_RCR) */
299 #define TIM_RCR(tim_base) MMIO32((tim_base) + 0x30)
300 #define TIM1_RCR TIM_RCR(TIM1)
301 #define TIM8_RCR TIM_RCR(TIM8)
302 #define TIM15_RCR TIM_RCR(TIM15)
303 #define TIM16_RCR TIM_RCR(TIM16)
304 #define TIM17_RCR TIM_RCR(TIM17)
305 
306 /* Capture/compare register 1 (TIMx_CCR1) */
307 #define TIM_CCR1(tim_base) MMIO32((tim_base) + 0x34)
308 #define TIM1_CCR1 TIM_CCR1(TIM1)
309 #define TIM2_CCR1 TIM_CCR1(TIM2)
310 #define TIM3_CCR1 TIM_CCR1(TIM3)
311 #define TIM4_CCR1 TIM_CCR1(TIM4)
312 #define TIM5_CCR1 TIM_CCR1(TIM5)
313 #define TIM8_CCR1 TIM_CCR1(TIM8)
314 #define TIM9_CCR1 TIM_CCR1(TIM9)
315 #define TIM10_CCR1 TIM_CCR1(TIM10)
316 #define TIM11_CCR1 TIM_CCR1(TIM11)
317 #define TIM12_CCR1 TIM_CCR1(TIM12)
318 #define TIM13_CCR1 TIM_CCR1(TIM13)
319 #define TIM14_CCR1 TIM_CCR1(TIM14)
320 #define TIM15_CCR1 TIM_CCR1(TIM15)
321 #define TIM16_CCR1 TIM_CCR1(TIM16)
322 #define TIM17_CCR1 TIM_CCR1(TIM17)
323 
324 /* Capture/compare register 2 (TIMx_CCR2) */
325 #define TIM_CCR2(tim_base) MMIO32((tim_base) + 0x38)
326 #define TIM1_CCR2 TIM_CCR2(TIM1)
327 #define TIM2_CCR2 TIM_CCR2(TIM2)
328 #define TIM3_CCR2 TIM_CCR2(TIM3)
329 #define TIM4_CCR2 TIM_CCR2(TIM4)
330 #define TIM5_CCR2 TIM_CCR2(TIM5)
331 #define TIM8_CCR2 TIM_CCR2(TIM8)
332 #define TIM9_CCR2 TIM_CCR2(TIM9)
333 #define TIM12_CCR2 TIM_CCR2(TIM12)
334 #define TIM15_CCR2 TIM_CCR2(TIM15)
335 
336 /* Capture/compare register 3 (TIMx_CCR3) */
337 #define TIM_CCR3(tim_base) MMIO32((tim_base) + 0x3C)
338 #define TIM1_CCR3 TIM_CCR3(TIM1)
339 #define TIM2_CCR3 TIM_CCR3(TIM2)
340 #define TIM3_CCR3 TIM_CCR3(TIM3)
341 #define TIM4_CCR3 TIM_CCR3(TIM4)
342 #define TIM5_CCR3 TIM_CCR3(TIM5)
343 #define TIM8_CCR3 TIM_CCR3(TIM8)
344 
345 /* Capture/compare register 4 (TIMx_CCR4) */
346 #define TIM_CCR4(tim_base) MMIO32((tim_base) + 0x40)
347 #define TIM1_CCR4 TIM_CCR4(TIM1)
348 #define TIM2_CCR4 TIM_CCR4(TIM2)
349 #define TIM3_CCR4 TIM_CCR4(TIM3)
350 #define TIM4_CCR4 TIM_CCR4(TIM4)
351 #define TIM5_CCR4 TIM_CCR4(TIM5)
352 #define TIM8_CCR4 TIM_CCR4(TIM8)
353 
354 /* Break and dead-time register (TIMx_BDTR) */
355 #define TIM_BDTR(tim_base) MMIO32((tim_base) + 0x44)
356 #define TIM1_BDTR TIM_BDTR(TIM1)
357 #define TIM8_BDTR TIM_BDTR(TIM8)
358 #define TIM15_BDTR TIM_BDTR(TIM15)
359 #define TIM16_BDTR TIM_BDTR(TIM16)
360 #define TIM17_BDTR TIM_BDTR(TIM17)
361 
362 /* DMA control register (TIMx_DCR) */
363 #define TIM_DCR(tim_base) MMIO32((tim_base) + 0x48)
364 #define TIM1_DCR TIM_DCR(TIM1)
365 #define TIM2_DCR TIM_DCR(TIM2)
366 #define TIM3_DCR TIM_DCR(TIM3)
367 #define TIM4_DCR TIM_DCR(TIM4)
368 #define TIM5_DCR TIM_DCR(TIM5)
369 #define TIM8_DCR TIM_DCR(TIM8)
370 #define TIM15_DCR TIM_DCR(TIM15)
371 #define TIM16_DCR TIM_DCR(TIM16)
372 #define TIM17_DCR TIM_DCR(TIM17)
373 
374 /* DMA address for full transfer (TIMx_DMAR) */
375 #define TIM_DMAR(tim_base) MMIO32((tim_base) + 0x4C)
376 #define TIM1_DMAR TIM_DMAR(TIM1)
377 #define TIM2_DMAR TIM_DMAR(TIM2)
378 #define TIM3_DMAR TIM_DMAR(TIM3)
379 #define TIM4_DMAR TIM_DMAR(TIM4)
380 #define TIM5_DMAR TIM_DMAR(TIM5)
381 #define TIM8_DMAR TIM_DMAR(TIM8)
382 #define TIM15_DMAR TIM_DMAR(TIM15)
383 #define TIM16_DMAR TIM_DMAR(TIM16)
384 #define TIM17_DMAR TIM_DMAR(TIM17)
385 
386 /* --- TIMx_CR1 values ----------------------------------------------------- */
387 
388 /****************************************************************************/
389 /** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio
390 @{*/
391 /* CKD[1:0]: Clock division */
392 #define TIM_CR1_CKD_CK_INT (0x0 << 8)
393 #define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8)
394 #define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8)
395 #define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8)
396 /**@}*/
397 
398 /* ARPE: Auto-reload preload enable */
399 #define TIM_CR1_ARPE (1 << 7)
400 
401 /* CMS[1:0]: Center-aligned mode selection */
402 /****************************************************************************/
403 /** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection
404 @{*/
405 #define TIM_CR1_CMS_EDGE (0x0 << 5)
406 #define TIM_CR1_CMS_CENTER_1 (0x1 << 5)
407 #define TIM_CR1_CMS_CENTER_2 (0x2 << 5)
408 #define TIM_CR1_CMS_CENTER_3 (0x3 << 5)
409 #define TIM_CR1_CMS_MASK (0x3 << 5)
410 /**@}*/
411 
412 /* DIR: Direction */
413 /****************************************************************************/
414 /** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction
415 @{*/
416 #define TIM_CR1_DIR_UP (0 << 4)
417 #define TIM_CR1_DIR_DOWN (1 << 4)
418 /**@}*/
419 
420 /* OPM: One pulse mode */
421 #define TIM_CR1_OPM (1 << 3)
422 
423 /* URS: Update request source */
424 #define TIM_CR1_URS (1 << 2)
425 
426 /* UDIS: Update disable */
427 #define TIM_CR1_UDIS (1 << 1)
428 
429 /* CEN: Counter enable */
430 #define TIM_CR1_CEN (1 << 0)
431 
432 /* --- TIMx_CR2 values ----------------------------------------------------- */
433 
434 /****************************************************************************/
435 /** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values
436 @{*/
437 /* OIS4:*//** Output idle state 4 (OC4 output) */
438 #define TIM_CR2_OIS4 (1 << 14)
439 
440 /* OIS3N:*//** Output idle state 3 (OC3N output) */
441 #define TIM_CR2_OIS3N (1 << 13)
442 
443 /* OIS3:*//** Output idle state 3 (OC3 output) */
444 #define TIM_CR2_OIS3 (1 << 12)
445 
446 /* OIS2N:*//** Output idle state 2 (OC2N output) */
447 #define TIM_CR2_OIS2N (1 << 11)
448 
449 /* OIS2:*//** Output idle state 2 (OC2 output) */
450 #define TIM_CR2_OIS2 (1 << 10)
451 
452 /* OIS1N:*//** Output idle state 1 (OC1N output) */
453 #define TIM_CR2_OIS1N (1 << 9)
454 
455 /* OIS1:*//** Output idle state 1 (OC1 output) */
456 #define TIM_CR2_OIS1 (1 << 8)
457 #define TIM_CR2_OIS_MASK (0x7f << 8)
458 /**@}*/
459 
460 /* TI1S: TI1 selection */
461 #define TIM_CR2_TI1S (1 << 7)
462 
463 /* MMS[2:0]: Master mode selection */
464 /****************************************************************************/
465 /** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection
466 @{*/
467 #define TIM_CR2_MMS_RESET (0x0 << 4)
468 #define TIM_CR2_MMS_ENABLE (0x1 << 4)
469 #define TIM_CR2_MMS_UPDATE (0x2 << 4)
470 #define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4)
471 #define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4)
472 #define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4)
473 #define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4)
474 #define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4)
475 #define TIM_CR2_MMS_MASK (0x7 << 4)
476 /**@}*/
477 
478 /* CCDS: Capture/compare DMA selection */
479 #define TIM_CR2_CCDS (1 << 3)
480 
481 /* CCUS: Capture/compare control update selection */
482 #define TIM_CR2_CCUS (1 << 2)
483 
484 /* CCPC: Capture/compare preload control */
485 #define TIM_CR2_CCPC (1 << 0)
486 
487 /* --- TIMx_SMCR values ---------------------------------------------------- */
488 
489 /* ETP: External trigger polarity */
490 #define TIM_SMCR_ETP (1 << 15)
491 
492 /* ECE: External clock enable */
493 #define TIM_SMCR_ECE (1 << 14)
494 
495 /* ETPS[1:0]: External trigger prescaler */
496 #define TIM_SMCR_ETPS_OFF (0x0 << 12)
497 #define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12)
498 #define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12)
499 #define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12)
500 #define TIM_SMCR_ETPS_MASK (0X3 << 12)
501 
502 /* ETF[3:0]: External trigger filter */
503 #define TIM_SMCR_ETF_OFF (0x0 << 8)
504 #define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8)
505 #define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8)
506 #define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8)
507 #define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8)
508 #define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8)
509 #define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8)
510 #define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8)
511 #define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8)
512 #define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8)
513 #define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8)
514 #define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8)
515 #define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8)
516 #define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8)
517 #define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8)
518 #define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8)
519 #define TIM_SMCR_ETF_MASK (0xF << 8)
520 
521 /* MSM: Master/slave mode */
522 #define TIM_SMCR_MSM (1 << 7)
523 
524 /* TS[2:0]: Trigger selection */
525 /** @defgroup tim_ts TIMx_SMCR TS Trigger selection
526 @{*/
527 /** Internal Trigger 0 (ITR0) */
528 #define TIM_SMCR_TS_ITR0 (0x0 << 4)
529 /** Internal Trigger 1 (ITR1) */
530 #define TIM_SMCR_TS_ITR1 (0x1 << 4)
531 /** Internal Trigger 2 (ITR2) */
532 #define TIM_SMCR_TS_ITR2 (0x2 << 4)
533 /** Internal Trigger 3 (ITR3) */
534 #define TIM_SMCR_TS_ITR3 (0x3 << 4)
535 /** TI1 Edge Detector (TI1F_ED) */
536 #define TIM_SMCR_TS_TI1F_ED (0x4 << 4)
537 /** Filtered Timer Input 1 (TI1FP1) */
538 #define TIM_SMCR_TS_TI1FP1 (0x5 << 4)
539 /** Filtered Timer Input 2 (TI2FP2) */
540 #define TIM_SMCR_TS_TI2FP2 (0x6 << 4)
541 /** External Trigger input (ETRF) */
542 #define TIM_SMCR_TS_ETRF (0x7 << 4)
543 #define TIM_SMCR_TS_MASK (0x7 << 4)
544 /**@}*/
545 
546 /* SMS[2:0]: Slave mode selection */
547 /** @defgroup tim_sms TIMx_SMCR SMS Slave mode selection
548 @{*/
549 /** Slave mode disabled */
550 #define TIM_SMCR_SMS_OFF (0x0 << 0)
551 /** Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
552 level. */
553 #define TIM_SMCR_SMS_EM1 (0x1 << 0)
554 /** Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
555 level. */
556 #define TIM_SMCR_SMS_EM2 (0x2 << 0)
557 /** Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
558 depending on the level of the complementary input. */
559 #define TIM_SMCR_SMS_EM3 (0x3 << 0)
560 /** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes
561  * the counter and generates an update of the registers.
562  */
563 #define TIM_SMCR_SMS_RM (0x4 << 0)
564 /** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is
565  * high.
566  */
567 #define TIM_SMCR_SMS_GM (0x5 << 0)
568 /** Trigger Mode - The counter starts at a rising edge of the trigger TRGI. */
569 #define TIM_SMCR_SMS_TM (0x6 << 0)
570 /** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock
571  * the counter.
572  */
573 #define TIM_SMCR_SMS_ECM1 (0x7 << 0)
574 #define TIM_SMCR_SMS_MASK (0x7 << 0)
575 /**@}*/
576 
577 /* --- TIMx_DIER values ---------------------------------------------------- */
578 
579 /****************************************************************************/
580 /** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values
581 @{*/
582 /* TDE:*//** Trigger DMA request enable */
583 #define TIM_DIER_TDE (1 << 14)
584 
585 /* COMDE:*//** COM DMA request enable */
586 #define TIM_DIER_COMDE (1 << 13)
587 
588 /* CC4DE:*//** Capture/Compare 4 DMA request enable */
589 #define TIM_DIER_CC4DE (1 << 12)
590 
591 /* CC3DE:*//** Capture/Compare 3 DMA request enable */
592 #define TIM_DIER_CC3DE (1 << 11)
593 
594 /* CC2DE:*//** Capture/Compare 2 DMA request enable */
595 #define TIM_DIER_CC2DE (1 << 10)
596 
597 /* CC1DE:*//** Capture/Compare 1 DMA request enable */
598 #define TIM_DIER_CC1DE (1 << 9)
599 
600 /* UDE*//**: Update DMA request enable */
601 #define TIM_DIER_UDE (1 << 8)
602 
603 /* BIE:*//** Break interrupt enable */
604 #define TIM_DIER_BIE (1 << 7)
605 
606 /* TIE:*//** Trigger interrupt enable */
607 #define TIM_DIER_TIE (1 << 6)
608 
609 /* COMIE:*//** COM interrupt enable */
610 #define TIM_DIER_COMIE (1 << 5)
611 
612 /* CC4IE:*//** Capture/compare 4 interrupt enable */
613 #define TIM_DIER_CC4IE (1 << 4)
614 
615 /* CC3IE:*//** Capture/compare 3 interrupt enable */
616 #define TIM_DIER_CC3IE (1 << 3)
617 
618 /* CC2IE:*//** Capture/compare 2 interrupt enable */
619 #define TIM_DIER_CC2IE (1 << 2)
620 
621 /* CC1IE:*//** Capture/compare 1 interrupt enable */
622 #define TIM_DIER_CC1IE (1 << 1)
623 
624 /* UIE:*//** Update interrupt enable */
625 #define TIM_DIER_UIE (1 << 0)
626 /**@}*/
627 
628 /* --- TIMx_SR values ------------------------------------------------------ */
629 /****************************************************************************/
630 /** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags
631 @{*/
632 
633 /* CC4OF:*//** Capture/compare 4 overcapture flag */
634 #define TIM_SR_CC4OF (1 << 12)
635 
636 /* CC3OF:*//** Capture/compare 3 overcapture flag */
637 #define TIM_SR_CC3OF (1 << 11)
638 
639 /* CC2OF:*//** Capture/compare 2 overcapture flag */
640 #define TIM_SR_CC2OF (1 << 10)
641 
642 /* CC1OF:*//** Capture/compare 1 overcapture flag */
643 #define TIM_SR_CC1OF (1 << 9)
644 
645 /* BIF:*//** Break interrupt flag */
646 #define TIM_SR_BIF (1 << 7)
647 
648 /* TIF:*//** Trigger interrupt flag */
649 #define TIM_SR_TIF (1 << 6)
650 
651 /* COMIF:*//** COM interrupt flag */
652 #define TIM_SR_COMIF (1 << 5)
653 
654 /* CC4IF:*//** Capture/compare 4 interrupt flag */
655 #define TIM_SR_CC4IF (1 << 4)
656 
657 /* CC3IF:*//** Capture/compare 3 interrupt flag */
658 #define TIM_SR_CC3IF (1 << 3)
659 
660 /* CC2IF:*//** Capture/compare 2 interrupt flag */
661 #define TIM_SR_CC2IF (1 << 2)
662 
663 /* CC1IF:*//** Capture/compare 1 interrupt flag */
664 #define TIM_SR_CC1IF (1 << 1)
665 
666 /* UIF:*//** Update interrupt flag */
667 #define TIM_SR_UIF (1 << 0)
668 /**@}*/
669 
670 /* --- TIMx_EGR values ----------------------------------------------------- */
671 
672 /****************************************************************************/
673 /** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values
674 @{*/
675 
676 /* BG:*//** Break generation */
677 #define TIM_EGR_BG (1 << 7)
678 
679 /* TG:*//** Trigger generation */
680 #define TIM_EGR_TG (1 << 6)
681 
682 /* COMG:*//** Capture/compare control update generation */
683 #define TIM_EGR_COMG (1 << 5)
684 
685 /* CC4G:*//** Capture/compare 4 generation */
686 #define TIM_EGR_CC4G (1 << 4)
687 
688 /* CC3G:*//** Capture/compare 3 generation */
689 #define TIM_EGR_CC3G (1 << 3)
690 
691 /* CC2G:*//** Capture/compare 2 generation */
692 #define TIM_EGR_CC2G (1 << 2)
693 
694 /* CC1G:*//** Capture/compare 1 generation */
695 #define TIM_EGR_CC1G (1 << 1)
696 
697 /* UG:*//** Update generation */
698 #define TIM_EGR_UG (1 << 0)
699 /**@}*/
700 
701 /* --- TIMx_CCMR1 values --------------------------------------------------- */
702 
703 /* --- Output compare mode --- */
704 
705 /* OC2CE: Output compare 2 clear enable */
706 #define TIM_CCMR1_OC2CE (1 << 15)
707 
708 /* OC2M[2:0]: Output compare 2 mode */
709 #define TIM_CCMR1_OC2M_FROZEN (0x0 << 12)
710 #define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12)
711 #define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12)
712 #define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12)
713 #define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12)
714 #define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12)
715 #define TIM_CCMR1_OC2M_PWM1 (0x6 << 12)
716 #define TIM_CCMR1_OC2M_PWM2 (0x7 << 12)
717 #define TIM_CCMR1_OC2M_MASK (0x7 << 12)
718 
719 /* OC2PE: Output compare 2 preload enable */
720 #define TIM_CCMR1_OC2PE (1 << 11)
721 
722 /* OC2FE: Output compare 2 fast enable */
723 #define TIM_CCMR1_OC2FE (1 << 10)
724 
725 /* CC2S[1:0]: Capture/compare 2 selection */
726 /* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
727  * TIMx_CCER). */
728 #define TIM_CCMR1_CC2S_OUT (0x0 << 8)
729 #define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8)
730 #define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8)
731 #define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8)
732 #define TIM_CCMR1_CC2S_MASK (0x3 << 8)
733 
734 /* OC1CE: Output compare 1 clear enable */
735 #define TIM_CCMR1_OC1CE (1 << 7)
736 
737 /* OC1M[2:0]: Output compare 1 mode */
738 #define TIM_CCMR1_OC1M_FROZEN (0x0 << 4)
739 #define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4)
740 #define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4)
741 #define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4)
742 #define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4)
743 #define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4)
744 #define TIM_CCMR1_OC1M_PWM1 (0x6 << 4)
745 #define TIM_CCMR1_OC1M_PWM2 (0x7 << 4)
746 #define TIM_CCMR1_OC1M_MASK (0x7 << 4)
747 
748 /* OC1PE: Output compare 1 preload enable */
749 #define TIM_CCMR1_OC1PE (1 << 3)
750 
751 /* OC1FE: Output compare 1 fast enable */
752 #define TIM_CCMR1_OC1FE (1 << 2)
753 
754 /* CC1S[1:0]: Capture/compare 1 selection */
755 /* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
756  * TIMx_CCER). */
757 #define TIM_CCMR1_CC1S_OUT (0x0 << 0)
758 #define TIM_CCMR1_CC1S_IN_TI2 (0x2 << 0)
759 #define TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0)
760 #define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0)
761 #define TIM_CCMR1_CC1S_MASK (0x3 << 0)
762 
763 /* --- Input capture mode --- */
764 
765 /* IC2F[3:0]: Input capture 2 filter */
766 #define TIM_CCMR1_IC2F_OFF (0x0 << 12)
767 #define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12)
768 #define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12)
769 #define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12)
770 #define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12)
771 #define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12)
772 #define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12)
773 #define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12)
774 #define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12)
775 #define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12)
776 #define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12)
777 #define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12)
778 #define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12)
779 #define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12)
780 #define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12)
781 #define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12)
782 #define TIM_CCMR1_IC2F_MASK (0xF << 12)
783 
784 /* IC2PSC[1:0]: Input capture 2 prescaler */
785 #define TIM_CCMR1_IC2PSC_OFF (0x0 << 10)
786 #define TIM_CCMR1_IC2PSC_2 (0x1 << 10)
787 #define TIM_CCMR1_IC2PSC_4 (0x2 << 10)
788 #define TIM_CCMR1_IC2PSC_8 (0x3 << 10)
789 #define TIM_CCMR1_IC2PSC_MASK (0x3 << 10)
790 
791 /* IC1F[3:0]: Input capture 1 filter */
792 #define TIM_CCMR1_IC1F_OFF (0x0 << 4)
793 #define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4)
794 #define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4)
795 #define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4)
796 #define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4)
797 #define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4)
798 #define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4)
799 #define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4)
800 #define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4)
801 #define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4)
802 #define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4)
803 #define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4)
804 #define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4)
805 #define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4)
806 #define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4)
807 #define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4)
808 #define TIM_CCMR1_IC1F_MASK (0xF << 4)
809 
810 /* IC1PSC[1:0]: Input capture 1 prescaler */
811 #define TIM_CCMR1_IC1PSC_OFF (0x0 << 2)
812 #define TIM_CCMR1_IC1PSC_2 (0x1 << 2)
813 #define TIM_CCMR1_IC1PSC_4 (0x2 << 2)
814 #define TIM_CCMR1_IC1PSC_8 (0x3 << 2)
815 #define TIM_CCMR1_IC1PSC_MASK (0x3 << 2)
816 
817 /* --- TIMx_CCMR2 values --------------------------------------------------- */
818 
819 /* --- Output compare mode --- */
820 
821 /* OC4CE: Output compare 4 clear enable */
822 #define TIM_CCMR2_OC4CE (1 << 15)
823 
824 /* OC4M[2:0]: Output compare 4 mode */
825 #define TIM_CCMR2_OC4M_FROZEN (0x0 << 12)
826 #define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12)
827 #define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12)
828 #define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12)
829 #define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12)
830 #define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12)
831 #define TIM_CCMR2_OC4M_PWM1 (0x6 << 12)
832 #define TIM_CCMR2_OC4M_PWM2 (0x7 << 12)
833 #define TIM_CCMR2_OC4M_MASK (0x7 << 12)
834 
835 /* OC4PE: Output compare 4 preload enable */
836 #define TIM_CCMR2_OC4PE (1 << 11)
837 
838 /* OC4FE: Output compare 4 fast enable */
839 #define TIM_CCMR2_OC4FE (1 << 10)
840 
841 /* CC4S[1:0]: Capture/compare 4 selection */
842 /* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
843  * TIMx_CCER). */
844 #define TIM_CCMR2_CC4S_OUT (0x0 << 8)
845 #define TIM_CCMR2_CC4S_IN_TI4 (0x1 << 8)
846 #define TIM_CCMR2_CC4S_IN_TI3 (0x2 << 8)
847 #define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8)
848 #define TIM_CCMR2_CC4S_MASK (0x3 << 8)
849 
850 /* OC3CE: Output compare 3 clear enable */
851 #define TIM_CCMR2_OC3CE (1 << 7)
852 
853 /* OC3M[2:0]: Output compare 3 mode */
854 #define TIM_CCMR2_OC3M_FROZEN (0x0 << 4)
855 #define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4)
856 #define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4)
857 #define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4)
858 #define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4)
859 #define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4)
860 #define TIM_CCMR2_OC3M_PWM1 (0x6 << 4)
861 #define TIM_CCMR2_OC3M_PWM2 (0x7 << 4)
862 #define TIM_CCMR2_OC3M_MASK (0x7 << 4)
863 
864 /* OC3PE: Output compare 3 preload enable */
865 #define TIM_CCMR2_OC3PE (1 << 3)
866 
867 /* OC3FE: Output compare 3 fast enable */
868 #define TIM_CCMR2_OC3FE (1 << 2)
869 
870 /* CC3S[1:0]: Capture/compare 3 selection */
871 /* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
872  * TIMx_CCER). */
873 #define TIM_CCMR2_CC3S_OUT (0x0 << 0)
874 #define TIM_CCMR2_CC3S_IN_TI3 (0x1 << 0)
875 #define TIM_CCMR2_CC3S_IN_TI4 (0x2 << 0)
876 #define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0)
877 #define TIM_CCMR2_CC3S_MASK (0x3 << 0)
878 
879 /* --- Input capture mode --- */
880 
881 /* IC4F[3:0]: Input capture 4 filter */
882 #define TIM_CCMR2_IC4F_OFF (0x0 << 12)
883 #define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12)
884 #define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12)
885 #define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12)
886 #define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12)
887 #define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12)
888 #define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12)
889 #define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12)
890 #define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12)
891 #define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12)
892 #define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12)
893 #define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12)
894 #define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12)
895 #define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12)
896 #define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12)
897 #define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12)
898 #define TIM_CCMR2_IC4F_MASK (0xF << 12)
899 
900 /* IC4PSC[1:0]: Input capture 4 prescaler */
901 #define TIM_CCMR2_IC4PSC_OFF (0x0 << 10)
902 #define TIM_CCMR2_IC4PSC_2 (0x1 << 10)
903 #define TIM_CCMR2_IC4PSC_4 (0x2 << 10)
904 #define TIM_CCMR2_IC4PSC_8 (0x3 << 10)
905 #define TIM_CCMR2_IC4PSC_MASK (0x3 << 10)
906 
907 /* IC3F[3:0]: Input capture 3 filter */
908 #define TIM_CCMR2_IC3F_OFF (0x0 << 4)
909 #define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4)
910 #define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4)
911 #define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4)
912 #define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4)
913 #define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4)
914 #define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4)
915 #define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4)
916 #define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4)
917 #define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4)
918 #define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4)
919 #define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4)
920 #define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4)
921 #define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4)
922 #define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4)
923 #define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4)
924 #define TIM_CCMR2_IC3F_MASK (0xF << 4)
925 
926 /* IC3PSC[1:0]: Input capture 3 prescaler */
927 #define TIM_CCMR2_IC3PSC_OFF (0x0 << 2)
928 #define TIM_CCMR2_IC3PSC_2 (0x1 << 2)
929 #define TIM_CCMR2_IC3PSC_4 (0x2 << 2)
930 #define TIM_CCMR2_IC3PSC_8 (0x3 << 2)
931 #define TIM_CCMR2_IC3PSC_MASK (0x3 << 2)
932 
933 /* --- TIMx_CCER values ---------------------------------------------------- */
934 
935 /* CC4NP: Capture/compare 4 complementary output polarity */
936 #define TIM_CCER_CC4NP (1 << 15)
937 
938 /* CC4P: Capture/compare 4 output polarity */
939 #define TIM_CCER_CC4P (1 << 13)
940 
941 /* CC4E: Capture/compare 4 output enable */
942 #define TIM_CCER_CC4E (1 << 12)
943 
944 /* CC3NP: Capture/compare 3 complementary output polarity */
945 #define TIM_CCER_CC3NP (1 << 11)
946 
947 /* CC3NE: Capture/compare 3 complementary output enable */
948 #define TIM_CCER_CC3NE (1 << 10)
949 
950 /* CC3P: Capture/compare 3 output polarity */
951 #define TIM_CCER_CC3P (1 << 9)
952 
953 /* CC3E: Capture/compare 3 output enable */
954 #define TIM_CCER_CC3E (1 << 8)
955 
956 /* CC2NP: Capture/compare 2 complementary output polarity */
957 #define TIM_CCER_CC2NP (1 << 7)
958 
959 /* CC2NE: Capture/compare 2 complementary output enable */
960 #define TIM_CCER_CC2NE (1 << 6)
961 
962 /* CC2P: Capture/compare 2 output polarity */
963 #define TIM_CCER_CC2P (1 << 5)
964 
965 /* CC2E: Capture/compare 2 output enable */
966 #define TIM_CCER_CC2E (1 << 4)
967 
968 /* CC1NP: Capture/compare 1 complementary output polarity */
969 #define TIM_CCER_CC1NP (1 << 3)
970 
971 /* CC1NE: Capture/compare 1 complementary output enable */
972 #define TIM_CCER_CC1NE (1 << 2)
973 
974 /* CC1P: Capture/compare 1 output polarity */
975 #define TIM_CCER_CC1P (1 << 1)
976 
977 /* CC1E: Capture/compare 1 output enable */
978 #define TIM_CCER_CC1E (1 << 0)
979 
980 /* --- TIMx_CNT values ----------------------------------------------------- */
981 
982 /* CNT[15:0]: Counter value */
983 
984 /* --- TIMx_PSC values ----------------------------------------------------- */
985 
986 /* PSC[15:0]: Prescaler value */
987 
988 /* --- TIMx_ARR values ----------------------------------------------------- */
989 
990 /* ARR[15:0]: Prescaler value */
991 
992 /* --- TIMx_RCR values ----------------------------------------------------- */
993 
994 /* REP[15:0]: Repetition counter value */
995 
996 /* --- TIMx_CCR1 values ---------------------------------------------------- */
997 
998 /* CCR1[15:0]: Capture/compare 1 value */
999 
1000 /* --- TIMx_CCR2 values ---------------------------------------------------- */
1001 
1002 /* CCR2[15:0]: Capture/compare 2 value */
1003 
1004 /* --- TIMx_CCR3 values ---------------------------------------------------- */
1005 
1006 /* CCR3[15:0]: Capture/compare 3 value */
1007 
1008 /* --- TIMx_CCR4 values ---------------------------------------------------- */
1009 
1010 /* CCR4[15:0]: Capture/compare 4 value */
1011 
1012 /* --- TIMx_BDTR values ---------------------------------------------------- */
1013 
1014 /* MOE: Main output enable */
1015 #define TIM_BDTR_MOE (1 << 15)
1016 
1017 /* AOE: Automatic output enable */
1018 #define TIM_BDTR_AOE (1 << 14)
1019 
1020 /* BKP: Break polarity */
1021 #define TIM_BDTR_BKP (1 << 13)
1022 
1023 /* BKE: Break enable */
1024 #define TIM_BDTR_BKE (1 << 12)
1025 
1026 /* OSSR: Off-state selection of run mode */
1027 #define TIM_BDTR_OSSR (1 << 11)
1028 
1029 /* OSSI: Off-state selection of idle mode */
1030 #define TIM_BDTR_OSSI (1 << 10)
1031 
1032 /* LOCK[1:0]: Lock configuration */
1033 /****************************************************************************/
1034 /** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values
1035 @{*/
1036 #define TIM_BDTR_LOCK_OFF (0x0 << 8)
1037 #define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8)
1038 #define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8)
1039 #define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8)
1040 #define TIM_BDTR_LOCK_MASK (0x3 << 8)
1041 /**@}*/
1042 
1043 /* DTG[7:0]: Dead-time generator set-up */
1044 #define TIM_BDTR_DTG_MASK 0x00FF
1045 
1046 /* --- TIMx_DCR values ----------------------------------------------------- */
1047 
1048 /* DBL[4:0]: DMA burst length */
1049 #define TIM_BDTR_DBL_MASK (0x1F << 8)
1050 
1051 /* DBA[4:0]: DMA base address */
1052 #define TIM_BDTR_DBA_MASK (0x1F << 0)
1053 
1054 /* --- TIMx_DMAR values ---------------------------------------------------- */
1055 
1056 /* DMAB[15:0]: DMA register for burst accesses */
1057 
1058 /* --- TIMx convenience defines -------------------------------------------- */
1059 
1060 /** Output Compare channel designators */
1062  TIM_OC1 = 0,
1069 };
1070 
1071 /** Output Compare mode designators */
1081 };
1082 
1083 /** Input Capture channel designators */
1089 };
1090 
1091 /** Input Capture input filter. The frequency used to sample the
1092 input and the number of events needed to validate an output transition.
1093 
1094 TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency
1095 (DTF), filter length x
1096 TIM_IC_DTF_DIV_y_N_x Division by y from the DTF, filter length x
1097  */
1115 };
1116 
1117 /** Input Capture input prescaler.
1118 
1119 TIM_IC_PSC_x Input capture is done every x events*/
1125 };
1126 
1127 /** Input Capture input source.
1128 
1129 The direction of the channel (input/output) as well as the input used.
1130  */
1138 };
1139 
1140 /** Slave external trigger polarity */
1144 };
1145 
1146 /* --- TIM function prototypes --------------------------------------------- */
1147 
1149 
1150 void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq);
1151 void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq);
1152 bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag);
1153 bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag);
1154 void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag);
1155 void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div,
1156  uint32_t alignment, uint32_t direction);
1157 void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div);
1158 void timer_enable_preload(uint32_t timer_peripheral);
1159 void timer_disable_preload(uint32_t timer_peripheral);
1160 void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment);
1161 void timer_direction_up(uint32_t timer_peripheral);
1162 void timer_direction_down(uint32_t timer_peripheral);
1163 void timer_one_shot_mode(uint32_t timer_peripheral);
1164 void timer_continuous_mode(uint32_t timer_peripheral);
1165 void timer_update_on_any(uint32_t timer_peripheral);
1166 void timer_update_on_overflow(uint32_t timer_peripheral);
1167 void timer_enable_update_event(uint32_t timer_peripheral);
1168 void timer_disable_update_event(uint32_t timer_peripheral);
1169 void timer_enable_counter(uint32_t timer_peripheral);
1170 void timer_disable_counter(uint32_t timer_peripheral);
1171 void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs);
1172 void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs);
1173 void timer_set_ti1_ch123_xor(uint32_t timer_peripheral);
1174 void timer_set_ti1_ch1(uint32_t timer_peripheral);
1175 void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode);
1176 void timer_set_dma_on_compare_event(uint32_t timer_peripheral);
1177 void timer_set_dma_on_update_event(uint32_t timer_peripheral);
1178 void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral);
1179 void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral);
1180 void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral);
1181 void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral);
1182 void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value);
1183 void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value);
1184 void timer_set_period(uint32_t timer_peripheral, uint32_t period);
1185 void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id);
1186 void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id);
1187 void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id);
1188 void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id);
1189 void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
1190  enum tim_oc_mode oc_mode);
1191 void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id);
1192 void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id);
1193 void timer_set_oc_polarity_high(uint32_t timer_peripheral,
1194  enum tim_oc_id oc_id);
1195 void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id);
1196 void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id);
1197 void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id);
1198 void timer_set_oc_idle_state_set(uint32_t timer_peripheral,
1199  enum tim_oc_id oc_id);
1200 void timer_set_oc_idle_state_unset(uint32_t timer_peripheral,
1201  enum tim_oc_id oc_id);
1202 void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id,
1203  uint32_t value);
1204 void timer_enable_break_main_output(uint32_t timer_peripheral);
1205 void timer_disable_break_main_output(uint32_t timer_peripheral);
1206 void timer_enable_break_automatic_output(uint32_t timer_peripheral);
1207 void timer_disable_break_automatic_output(uint32_t timer_peripheral);
1208 void timer_set_break_polarity_high(uint32_t timer_peripheral);
1209 void timer_set_break_polarity_low(uint32_t timer_peripheral);
1210 void timer_enable_break(uint32_t timer_peripheral);
1211 void timer_disable_break(uint32_t timer_peripheral);
1212 void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral);
1213 void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral);
1214 void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral);
1215 void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral);
1216 void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock);
1217 void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime);
1218 void timer_generate_event(uint32_t timer_peripheral, uint32_t event);
1219 uint32_t timer_get_counter(uint32_t timer_peripheral);
1220 void timer_set_counter(uint32_t timer_peripheral, uint32_t count);
1221 
1222 void timer_ic_set_filter(uint32_t timer, enum tim_ic_id ic,
1223  enum tim_ic_filter flt);
1224 void timer_ic_set_prescaler(uint32_t timer, enum tim_ic_id ic,
1225  enum tim_ic_psc psc);
1226 void timer_ic_set_input(uint32_t timer, enum tim_ic_id ic,
1227  enum tim_ic_input in);
1228 void timer_ic_enable(uint32_t timer, enum tim_ic_id ic);
1229 void timer_ic_disable(uint32_t timer, enum tim_ic_id ic);
1230 
1231 void timer_slave_set_filter(uint32_t timer, enum tim_ic_filter flt);
1232 void timer_slave_set_prescaler(uint32_t timer, enum tim_ic_psc psc);
1233 void timer_slave_set_polarity(uint32_t timer, enum tim_et_pol pol);
1234 void timer_slave_set_mode(uint32_t timer, uint8_t mode);
1235 void timer_slave_set_trigger(uint32_t timer, uint8_t trigger);
1236 
1237 END_DECLS
1238 
1239 /**@}*/
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
void timer_continuous_mode(uint32_t timer_peripheral)
Enable the Timer to Run Continuously.
void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Enable the Output Compare Slow Mode.
void timer_enable_preload(uint32_t timer_peripheral)
Enable Auto-Reload Buffering.
void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs)
Set Timer Output Idle States Low.
void timer_one_shot_mode(uint32_t timer_peripheral)
Enable the Timer for One Cycle and Stop.
void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode)
Set the Master Mode.
void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral)
Disable Timer Capture/Compare Control Preload.
void timer_set_dma_on_compare_event(uint32_t timer_peripheral)
Set Timer DMA Requests on Capture/Compare Events.
void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Enable the Output Compare Fast Mode.
void timer_update_on_overflow(uint32_t timer_peripheral)
Set the Timer to Generate Update IRQ or DMA only from Under/Overflow Events.
void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral)
Disable Off-State in Idle Mode.
tim_ic_psc
Input Capture input prescaler.
bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag)
Read a Status Flag.
void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral)
Enable Timer Capture/Compare Control Update with Trigger.
void timer_disable_break_main_output(uint32_t timer_peripheral)
Disable Output in Break.
void timer_enable_break(uint32_t timer_peripheral)
Enable Break.
void timer_set_oc_polarity_high(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Set the Output Polarity High.
void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div, uint32_t alignment, uint32_t direction)
Set the Timer Mode.
void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Disable the Output Compare Clear Function.
void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock)
Set Lock Bits.
void timer_disable_preload(uint32_t timer_peripheral)
Disable Auto-Reload Buffering.
void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value)
Set the Value for the Timer Prescaler.
void timer_disable_counter(uint32_t timer_peripheral)
Stop the timer from counting.
void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Enable the Output Compare Clear Function.
void timer_set_break_polarity_high(uint32_t timer_peripheral)
Activate Break when Input High.
void timer_slave_set_trigger(uint32_t timer, uint8_t trigger)
Set Slave Trigger Source.
void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode)
Timer Set Output Compare Mode.
void timer_slave_set_prescaler(uint32_t timer, enum tim_ic_psc psc)
Set External Trigger Prescaler for Slave.
void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Set Output Compare Idle State Low.
bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag)
Return Interrupt Source.
void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime)
Set Deadtime.
void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment)
Specify the counter alignment mode.
void timer_set_counter(uint32_t timer_peripheral, uint32_t count)
Set Counter.
void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Enable the Output Compare Preload Register.
void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs)
Set Timer Output Idle States High.
void timer_slave_set_mode(uint32_t timer, uint8_t mode)
Set Slave Mode.
void timer_set_dma_on_update_event(uint32_t timer_peripheral)
Set Timer DMA Requests on Update Events.
void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral)
Enable Off-State in Idle Mode.
void timer_enable_update_event(uint32_t timer_peripheral)
Enable Timer Update Events.
void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral)
Enable Timer Capture/Compare Control Preload.
tim_ic_filter
Input Capture input filter.
void timer_slave_set_polarity(uint32_t timer, enum tim_et_pol pol)
Set External Trigger Polarity for Slave.
void timer_enable_counter(uint32_t timer_peripheral)
Enable the timer to start counting.
void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Disable the Output Compare.
tim_oc_mode
Output Compare mode designators.
void timer_set_ti1_ch1(uint32_t timer_peripheral)
Set Timer 1 Input to Channel 1.
tim_et_pol
Slave external trigger polarity.
void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer set Output Compare Idle State High.
void timer_ic_set_input(uint32_t timer, enum tim_ic_id ic, enum tim_ic_input in)
Set Capture/Compare Channel Direction/Input.
void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Disable the Output Compare Preload Register.
void timer_direction_down(uint32_t timer_peripheral)
Set the Timer to Count Down.
void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral)
Disable Timer Capture/Compare Control Update with Trigger.
void timer_ic_enable(uint32_t timer, enum tim_ic_id ic)
Enable Timer Input Capture.
void timer_ic_disable(uint32_t timer, enum tim_ic_id ic)
Disable Timer Input Capture.
void timer_update_on_any(uint32_t timer_peripheral)
Set the Timer to Generate Update IRQ or DMA on any Event.
void timer_disable_break(uint32_t timer_peripheral)
Disable Break.
void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq)
Enable Interrupts for a Timer.
void timer_enable_break_automatic_output(uint32_t timer_peripheral)
Enable Automatic Output in Break.
void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral)
Enable Off-State in Run Mode.
void timer_direction_up(uint32_t timer_peripheral)
Set the Timer to Count Up.
void timer_enable_break_main_output(uint32_t timer_peripheral)
Enable Output in Break.
void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral)
Disable Off-State in Run Mode.
void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Enable the Output Compare.
void timer_disable_update_event(uint32_t timer_peripheral)
Disable Timer Update Events.
tim_oc_id
Output Compare channel designators.
void timer_set_ti1_ch123_xor(uint32_t timer_peripheral)
Set Timer 1 Input to XOR of Three Channels.
void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value)
Timer Set Output Compare Value.
tim_ic_input
Input Capture input source.
void timer_ic_set_prescaler(uint32_t timer, enum tim_ic_id ic, enum tim_ic_psc psc)
Set Input Capture Prescaler.
void timer_ic_set_filter(uint32_t timer, enum tim_ic_id ic, enum tim_ic_filter flt)
Set Input Capture Filter Parameters.
void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id)
Timer Set the Output Polarity Low.
void timer_disable_break_automatic_output(uint32_t timer_peripheral)
Disable Automatic Output in Break.
void timer_set_break_polarity_low(uint32_t timer_peripheral)
Activate Break when Input Low.
uint32_t timer_get_counter(uint32_t timer_peripheral)
Read Counter.
void timer_generate_event(uint32_t timer_peripheral, uint32_t event)
Force generate a timer event.
void timer_slave_set_filter(uint32_t timer, enum tim_ic_filter flt)
Set External Trigger Filter Parameters for Slave.
void timer_set_period(uint32_t timer_peripheral, uint32_t period)
Timer Set Period.
void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value)
Set the Value for the Timer Repetition Counter.
void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag)
Clear a Status Flag.
void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq)
Disable Interrupts for a Timer.
tim_ic_id
Input Capture channel designators.
void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div)
Set Input Filter and Dead-time Clock Divider Ratio.
@ TIM_IC_PSC_8
@ TIM_IC_PSC_4
@ TIM_IC_PSC_OFF
@ TIM_IC_PSC_2
@ TIM_IC_DTF_DIV_32_N_6
@ TIM_IC_DTF_DIV_32_N_5
@ TIM_IC_DTF_DIV_8_N_6
@ TIM_IC_CK_INT_N_4
@ TIM_IC_DTF_DIV_2_N_8
@ TIM_IC_DTF_DIV_16_N_6
@ TIM_IC_CK_INT_N_2
@ TIM_IC_DTF_DIV_4_N_8
@ TIM_IC_OFF
@ TIM_IC_DTF_DIV_16_N_8
@ TIM_IC_DTF_DIV_16_N_5
@ TIM_IC_DTF_DIV_2_N_6
@ TIM_IC_DTF_DIV_4_N_6
@ TIM_IC_CK_INT_N_8
@ TIM_IC_DTF_DIV_8_N_8
@ TIM_IC_DTF_DIV_32_N_8
@ TIM_OCM_FROZEN
@ TIM_OCM_FORCE_LOW
@ TIM_OCM_INACTIVE
@ TIM_OCM_FORCE_HIGH
@ TIM_OCM_PWM2
@ TIM_OCM_TOGGLE
@ TIM_OCM_PWM1
@ TIM_OCM_ACTIVE
@ TIM_ET_RISING
@ TIM_ET_FALLING
@ TIM_OC1N
@ TIM_OC4
@ TIM_OC1
@ TIM_OC3N
@ TIM_OC3
@ TIM_OC2
@ TIM_OC2N
@ TIM_IC_OUT
@ TIM_IC_IN_TRC
@ TIM_IC_IN_TI2
@ TIM_IC_IN_TI3
@ TIM_IC_IN_TI4
@ TIM_IC_IN_TI1
@ TIM_IC1
@ TIM_IC2
@ TIM_IC3
@ TIM_IC4