libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
can.c
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1/**
2 * @addtogroup can_api CAN Peripheral API
3 * @ingroup peripheral_apis
4 * @brief <b>PAC55xxxx CAN Driver</b>
5 * @author @htmlonly &copy; @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
6 * @date February 13, 2020
7 *
8 * This library supports the CAN module in the PAC55xx SoC from Qorvo.
9 *
10 * Note: Acceptance Code Mask Register values of 1 indicate the filter is to
11 * ignore the bit. However, standard CAN driver APIs use a positive logic for the
12 * mask. The implementations in this file inverts masks as appropriate to
13 * the mask to make this more portable/intuitive.
14 *
15 * LGPL License Terms @ref lgpl_license
16 */
17/*
18 * This file is part of the libopencm3 project.
19 *
20 * This library is free software: you can redistribute it and/or modify
21 * it under the terms of the GNU Lesser General Public License as published by
22 * the Free Software Foundation, either version 3 of the License, or
23 * (at your option) any later version.
24 *
25 * This library is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU Lesser General Public License for more details.
29 *
30 * You should have received a copy of the GNU Lesser General Public License
31 * along with this library. If not, see <http://www.gnu.org/licenses/>.
32 */
35
36/*---------------------------------------------------------------------------*/
37/** @brief CAN Enable
38Enable the CAN peripheral and its associated FIFOs/counters/interrupts.
39@param[in] canport Unsigned int32. CAN block register base address.
40*/
41void can_enable(uint32_t canport) {
43}
44
45/*---------------------------------------------------------------------------*/
46/** @brief CAN Disable
47Disable the CAN peripheral and all associated FIFOs/counters/interrupts.
48@param[in] canport Unsigned int32. CAN block register base address.
49*/
50void can_disable(uint32_t canport) {
52}
53
54/*---------------------------------------------------------------------------*/
55/** @brief CAN Init
56Initialize the selected CAN peripheral block.
57@param[in] canport Unsigned int32. CAN block register base address.
58@param[in] listen_only bool. Enable listen only mode.
59@param[in] sjw Unsigned int32. Resynchronization time quanta jump width.
60@param[in] tseg1 Unsigned int32. Time segment 1 time quanta width.
61@param[in] tseg2 Unsigned int32. Time segment 2 time quanta width.
62@param[in] sam3 bool. Use best 2 out of 3 samples.
63@param[in] brp Unsigned int32. Baud rate prescaler.
64*/
65void can_init(uint32_t canport, bool listen_only, uint32_t sjw,
66 uint32_t tseg1, uint32_t tseg2,
67 bool sam3, uint32_t brp) {
68 /* Put CAN module in reset and clear out ISR/SR/CMR/MR */
70 /* Setup single filter scheme */
72 /* enable listen-only mode */
73 if (listen_only) {
75 }
76
77 /* Set Baud Rate Prescaler, sync jump width, tseg1/2 */
79 | CAN_BTR1_TSEG1(tseg1) | CAN_BTR1_TSEG2(tseg2);
80 if (sam3) {
81 /* enable sample bus 3 times */
83 }
84
85 /* Filter: Accept incoming messages with any identifier */
86 CAN_ACR(canport) = 0;
87 /* Note: when mask bits are 1, the bits are ignored */
88 CAN_AMR(canport) = 0xFFFFFFFFu;
89}
90
91/*---------------------------------------------------------------------------*/
92/** @brief CAN Filter Clear
93Clear the message filters to receive all messages.
94@param[in] canport Unsigned int32. CAN block register base address.
95*/
96void can_filter_clear(uint32_t canport) {
97 /* Filter: Accept incoming messages with any identifier */
98 CAN_ACR(canport) = 0;
99 /* Note: when mask bits are 1, the bits are ignored */
100 CAN_AMR(canport) = 0xFFFFFFFFu;
101 /* Setup single filter scheme */
103}
104
105/*---------------------------------------------------------------------------*/
106/** @brief CAN Dual Filter Standard Frame
107Notes:
108 - Acceptance Code Mask Register values of 1 indicate the filter is to ignore
109 the bit. However standard CAN driver APIs use a positive logic for the mask.
110 So this function inverts the mask to make this more portable/intuitive.
111 - Register definition byte order is opposite what is shown in Rev 1.23 of
112 the PAC55XX Family User Guide. Since both data and ID values cross byte
113 boundaries, the bswap32 function is used to correct for the discrepancy.
114
115@param[in] canport Unsigned int32. CAN block register base address.
116@param[in] id1 Unsigned int32. CAN ID 1. Only bits 10:0 are used.
117@param[in] id1_mask Unsigned int32. CAN ID 1 mask. Only bits 10:0 are used.
118@param[in] id2 Unsigned int32. CAN ID 2. Only bits 10:0 are used.
119@param[in] id2_mask Unsigned int32. CAN ID 2 mask. Only bits 10:0 are used.
120@param[in] db bool. CAN first data byte value.
121@param[in] db_mask bool. CAN first data byte mask.
122*/
123void can_filter_dual(uint32_t canport, uint32_t id1, uint32_t id1_mask,
124 uint32_t id2, uint32_t id2_mask,
125 uint8_t db, uint8_t db_mask) {
126 /* set value */
127 uint32_t word = ((id1 << 21) & CAN_ACR_DUAL_ID1)
128 | ((id2 << 5) & CAN_ACR_DUAL_ID2)
129 | ((db << 12) & CAN_ACR_DUAL_DB_UPPER) | (db & CAN_ACR_DUAL_DB_LOWER);
130 CAN_ACR(canport) = __builtin_bswap32(word);
131 /* set mask */
132 word = ((~id1_mask << 21) & CAN_ACR_DUAL_ID1)
133 | ((~id2_mask << 5) & CAN_ACR_DUAL_ID2)
134 | ((~db_mask << 12) & CAN_ACR_DUAL_DB_UPPER)
135 | ((~db_mask) & CAN_ACR_DUAL_DB_LOWER)
137 CAN_AMR(canport) = __builtin_bswap32(word);
138 /* 0: dual filter */
140}
141
142/*---------------------------------------------------------------------------*/
143/** @brief CAN Filter Single Standard Frame
144Notes:
145 - Acceptance Code Mask Register values of 1 indicate the filter is to ignore
146 the bit. However standard CAN driver APIs use a positive logic for the mask.
147 So this function inverts the mask to make this more portable/intuitive.
148 - Register definition byte order is opposite what is shown in Rev 1.23 of
149 the PAC55XX Family User Guide. Since both data and ID values cross byte
150 boundaries, the bswap32 function is used to correct for the discrepancy.
151
152@param[in] canport Unsigned int32. CAN block register base address.
153@param[in] id Unsigned int32. CAN ID. Only bits 10:0 are used.
154@param[in] id_mask Unsigned int32. CAN ID mask. Only bits 10:0 are used.
155@param[in] db1 bool. CAN first data byte value.
156@param[in] db1_mask bool. CAN first data byte mask.
157@param[in] db2 bool. CAN second data byte value.
158@param[in] db2_mask bool. CAN second data byte mask.
159*/
160void can_filter_single_std(uint32_t canport, uint32_t id, uint32_t id_mask,
161 uint8_t db1, uint8_t db1_mask,
162 uint8_t db2, uint8_t db2_mask) {
163 /* set value */
164 uint32_t word = ((id << 21) & CAN_ACR_SINGLE_STD_ID)
165 | ((db1 << 8) & CAN_ACR_SINGLE_STD_DB1)
166 | ((db2 << 0) & CAN_ACR_SINGLE_STD_DB2);
167 CAN_ACR(canport) = __builtin_bswap32(word);
168 /* set mask */
169 word = ((~id_mask << 21) & CAN_ACR_SINGLE_STD_ID)
171 | ((~db1_mask << 8) & CAN_ACR_SINGLE_STD_DB1)
172 | ((~db2_mask << 0) & CAN_ACR_SINGLE_STD_DB2);
173 CAN_AMR(canport) = __builtin_bswap32(word);
174 /* 1: single filter */
176}
177
178/*---------------------------------------------------------------------------*/
179/** @brief CAN Filter Single Standard Frame w/RTR set
180Notes:
181 - Acceptance Code Mask Register values of 1 indicate the filter is to ignore
182 the bit. However standard CAN driver APIs use a positive logic for the mask.
183 So this function inverts the mask to make this more portable/intuitive.
184 - Register definition byte order is opposite what is shown in Rev 1.23 of
185 the PAC55XX Family User Guide. Since both data and ID values cross byte
186 boundaries, the bswap32 function is used to correct for the discrepancy.
187
188@param[in] canport Unsigned int32. CAN block register base address.
189@param[in] id Unsigned int32. CAN ID. Only bits 10:0 are used.
190@param[in] id_mask Unsigned int32. CAN ID mask. Only bits 10:0 are used.
191@param[in] db1 bool. CAN first data byte value.
192@param[in] db1_mask bool. CAN first data byte mask.
193@param[in] db2 bool. CAN second data byte value.
194@param[in] db2_mask bool. CAN second data byte mask.
195*/
196void can_filter_single_std_rtr(uint32_t canport, uint32_t id, uint32_t id_mask,
197 uint8_t db1, uint8_t db1_mask,
198 uint8_t db2, uint8_t db2_mask) {
199 /* set value */
200 uint32_t word = ((id << 21) & CAN_ACR_SINGLE_STD_ID)
202 | ((db2 << 0) & CAN_ACR_SINGLE_STD_DB2);
203 CAN_ACR(canport) = __builtin_bswap32(word);
204 /* set mask */
205 word = ((~id_mask << 21) & CAN_ACR_SINGLE_STD_ID)
206 | ((~db1_mask << 8) & CAN_ACR_SINGLE_STD_DB1)
207 | ((~db2_mask << 0) & CAN_ACR_SINGLE_STD_DB2);
208 CAN_AMR(canport) = __builtin_bswap32(word);
209 /* 1: single filter */
211}
212
213/*---------------------------------------------------------------------------*/
214/** @brief CAN Filter Single Extended Frame
215Notes:
216 - Acceptance Code Mask Register values of 1 indicate the filter is to ignore
217 the bit. However standard CAN driver APIs use a positive logic for the mask.
218 So this function inverts the mask to make this more portable/intuitive.
219 - Register definition byte order is opposite what is shown in Rev 1.23 of
220 the PAC55XX Family User Guide. Since both data and ID values cross byte
221 boundaries, the bswap32 function is used to correct for the discrepancy.
222
223@param[in] canport Unsigned int32. CAN block register base address.
224@param[in] id Unsigned int32. CAN ID. Only bits 28:0 are used.
225@param[in] id_mask Unsigned int32. CAN ID mask. Only bits 28:0 are used.
226*/
227void can_filter_single_ext(uint32_t canport, uint32_t id, uint32_t id_mask) {
228 /* set value */
229 uint32_t word = ((id << 3) & CAN_ACR_SINGLE_EXT_ID);
230 CAN_ACR(canport) = __builtin_bswap32(word);
231 /* set mask */
232 word = ((~id_mask << 3) & CAN_ACR_SINGLE_EXT_ID) | CAN_ACR_SINGLE_EXT_RTR;
233 CAN_AMR(canport) = __builtin_bswap32(word);
234 /* 1: single filter */
236}
237
238/*---------------------------------------------------------------------------*/
239/** @brief CAN Filter Single Extended Frame w/RTR set
240Notes:
241 - Acceptance Code Mask Register values of 1 indicate the filter is to ignore
242 the bit. However standard CAN driver APIs use a positive logic for the mask.
243 So this function inverts the mask to make this more portable/intuitive.
244 - Register definition byte order is opposite what is shown in Rev 1.23 of
245 the PAC55XX Family User Guide. Since both data and ID values cross byte
246 boundaries, the bswap32 function is used to correct for the discrepancy.
247
248@param[in] canport Unsigned int32. CAN block register base address.
249@param[in] id Unsigned int32. CAN ID. Only bits 28:0 are used.
250@param[in] id_mask Unsigned int32. CAN ID mask. Only bits 28:0 are used.
251*/
252void can_filter_single_ext_rtr(uint32_t canport, uint32_t id, uint32_t id_mask) {
253 /* set value */
254 uint32_t word = ((id << 3) & CAN_ACR_SINGLE_EXT_ID) | CAN_ACR_SINGLE_EXT_RTR;
255 CAN_ACR(canport) = __builtin_bswap32(word);
256 /* set mask */
257 word = ((~id_mask << 3) & CAN_ACR_SINGLE_EXT_ID);
258 CAN_AMR(canport) = __builtin_bswap32(word);
259 /* 1: single filter */
261}
262
263/*---------------------------------------------------------------------------*/
264/** @brief CAN Enable IRQ
265@param[in] canport Unsigned int32. CAN block register base address.
266@param[in] irq Unsigned int8. IRQ bit(s).
267*/
268void can_enable_irq(uint32_t canport, uint8_t irq) {
269 /* set to 1 (not masked) to enable */
270 CAN_BTR1_BTR0_RMC_IMR(canport) |= (uint32_t)irq;
271}
272
273/*---------------------------------------------------------------------------*/
274/** @brief CAN Disable IRQ
275@param[in] canport Unsigned int32. CAN block register base address.
276@param[in] irq Unsigned int8. IRQ bit(s).
277*/
278void can_disable_irq(uint32_t canport, uint8_t irq) {
279 /* set to 0 (masked) to disable */
280 CAN_BTR1_BTR0_RMC_IMR(canport) &= ~(uint32_t)irq;
281}
282
283/*---------------------------------------------------------------------------*/
284/** @brief CAN Transmit Standard Frame
285@param[in] canport Unsigned int32. CAN block register base address.
286@param[in] id Unsigned int32. Message ID bits 10:0 used.
287@param[in] rtr bool. Remote Request bit value.
288@param[in] length Unsigned int8. Message payload length.
289@param[in] data Unsigned int8[]. Message payload data.
290@returns true if able to transmit, false otherwise.
291*/
292bool can_transmit_std(uint32_t canport, uint32_t id, bool rtr, uint8_t length,
293 const uint8_t *data) {
294 /* if TBS is 0, then not ready to transmit */
295 if ((CAN_ISR_SR_CMR_MR(canport) & CAN_SR_TBS) == 0) {
296 return false;
297 }
298 uint32_t word = (length & CAN_BITS_3_0)
299 | (rtr ? BIT6 : 0) /* DLC/RTR/FF ==> 7:0 */
300 | ((id & CAN_BITS_10_3) << 5) /* ID 10:3 ==> 15:8 */
301 | ((id & CAN_BITS_2_0) << 21) /* ID 2:0 ==> 23:21 */
302 | (((length > 0) ? data[0] : 0) << 24);
303 CAN_TXBUF(canport) = word;
304
305 if (length > 1) {
306 word = (data[1] << 0) | (data[2] << 8)
307 | (data[3] << 16) | (data[4] << 24);
308 CAN_TXBUF(canport) = word;
309 }
310
311 if (length > 5) {
312 word = (data[5] << 0) | (data[6] << 8) | (data[7] << 16);
313 CAN_TXBUF(canport) = word;
314 }
315
316 /* Request transmit */
318 return true;
319}
320
321/*---------------------------------------------------------------------------*/
322/** @brief CAN Transmit Extended Frame
323@param[in] canport Unsigned int32. CAN block register base address.
324@param[in] id Unsigned int32. Message ID bits 28:0 used.
325@param[in] rtr bool. Remote Request bit value.
326@param[in] length Unsigned int8. Message payload length, 0-8.
327@param[in] data Unsigned int8[]. Message payload data.
328@returns true if able to transmit, false otherwise.
329*/
330bool can_transmit_ext(uint32_t canport, uint32_t id, bool rtr, uint8_t length,
331 const uint8_t *data) {
332 /* if TBS is 0, then not ready to transmit */
333 if ((CAN_ISR_SR_CMR_MR(canport) & CAN_SR_TBS) == 0) {
334 return false;
335 }
336 uint32_t word = (length & CAN_BITS_3_0)
337 | (rtr ? BIT6 : 0) | BIT7 /* DLC/RTR/FF ==> 7:0 */
338 | ((id & CAN_BITS_28_21) >> 13) /* ID 28:21 ==> 15:8 */
339 | ((id & CAN_BITS_20_13) << 3) /* ID 20:13 ==> 23:16 */
340 | ((id & CAN_BITS_12_5) << 19); /* ID 12:5 ==> 31:24 */
341 CAN_TXBUF(canport) = word; /* write first 32-bit word to FIFO */
342
343 word = ((id & CAN_BITS_4_0) << 3); /* ID 4:0 ==> 7:3 */
344 if (length > 0) {
345 word |= (data[0] << 8) | (data[1] << 16) | (data[2] << 24);
346 }
347 /* for extended frame, always write second 32-bit word to FIFO */
348 CAN_TXBUF(canport) = word;
349 if (length > 3) {
350 word = (data[3] << 0) | (data[4] << 8)
351 | (data[5] << 16) | (data[6] << 24);
352 CAN_TXBUF(canport) = word;
353 }
354 if (length > 7) {
355 word = data[7];
356 CAN_TXBUF(canport) = word;
357 }
358 /* Request transmit */
360 return true;
361}
362
363/*---------------------------------------------------------------------------*/
364/** @brief CAN Abort Transmit
365Aborts the current transmission.
366
367@param[in] canport Unsigned int32. CAN block register base address.
368*/
369void can_abort_transmit(uint32_t canport) {
371}
372
373/*---------------------------------------------------------------------------*/
374/** @brief CAN Receive Message
375If no data is in the RX buffer, id and length are set to 0.
376
377@param[in] canport Unsigned int32. CAN block register base address.
378@param[out] id Unsigned int32 pointer. Message ID.
379@param[out] ext bool pointer. The message ID is extended.
380@param[out] rtr bool pointer. Remote Request bit value.
381@param[out] length Unsigned int8 pointer. Length of message payload.
382@param[out] data Unsigned int8[]. Message payload data, min length 8.
383*/
384void can_receive(uint32_t canport, uint32_t *id, bool *ext, bool *rtr, uint8_t *length,
385 uint8_t *data) {
386 if ((CAN_ISR_SR_CMR_MR(canport) & CAN_ISR_RI) == 0 || CAN_RMC(canport) == 0) {
387 *id = 0;
388 *length = 0;
389 return; /* empty RX FIFO */
390 }
391 uint32_t can_buffer = CAN_RXBUF(canport); /* read 32-bit word */
392 uint8_t rx_length = can_buffer & CAN_BITS_3_0;
393 bool is_extended = can_buffer & BIT7;
394 if (ext) {
395 *ext = is_extended;
396 }
397 if (rtr) {
398 *rtr = can_buffer & BIT6;
399 }
400 if (length) {
401 *length = rx_length;
402 }
403 uint32_t _id;
404 if (is_extended) {
405 /* Parse extended message ID from RXBUF */
406 _id = ((can_buffer & CAN_BITS_15_8) << 13) /* ID 28:21 <== 15:8 */
407 | ((can_buffer & CAN_BITS_23_16) >> 3) /* ID 20:13 <== 23:16 */
408 | ((can_buffer & CAN_BITS_31_24) >> 19); /* ID 12:5 <== 31:24 */
409 can_buffer = CAN_RXBUF(canport);
410 _id |= ((can_buffer & CAN_BITS_7_3) >> 3); /* ID 4:0 <== 7:3 */
411
412 /* Parse extended message data from RXBUF */
413 data[0] = can_buffer >> 8;
414 data[1] = can_buffer >> 16;
415 data[2] = can_buffer >> 24;
416 if (rx_length > 3) {
417 can_buffer = CAN_RXBUF(canport);
418 data[3] = can_buffer;
419 data[4] = can_buffer >> 8;
420 data[5] = can_buffer >> 16;
421 data[6] = can_buffer >> 24;
422 }
423 if (rx_length > 7) {
424 can_buffer = CAN_RXBUF(canport);
425 data[7] = can_buffer;
426 }
427 } else {
428 /* Parse standard message ID from RXBUF */
429 _id = ((can_buffer & CAN_BITS_15_8) >> 5) /* ID 10:3 <== 15:8 */
430 | ((can_buffer & CAN_BITS_23_21) >> 21); /* ID 2:0 <== 23:21 */
431 /* Parse standard message data from RXBUF */
432 data[0] = can_buffer >> 24;
433 if (rx_length > 1) {
434 can_buffer = CAN_RXBUF(canport);
435 data[1] = can_buffer;
436 data[2] = can_buffer >> 8;
437 data[3] = can_buffer >> 16;
438 data[4] = can_buffer >> 24;
439 if (rx_length > 5) {
440 /* buffer contains data5,data6,data7 */
441 can_buffer = CAN_RXBUF(canport);
442 data[5] = can_buffer;
443 data[6] = can_buffer >> 8;
444 data[7] = can_buffer >> 16;
445 }
446 }
447 }
448 if (id) {
449 *id = _id;
450 }
451
452 /*
453 * Write 1 to acknowledge/clear the interrupt
454 * Note: ensure not to let the other interrupt masks be written as 1, so as
455 * to avoid acknowledging them.
456 * Note: CAN_ISR_RI is already high, but we still write '1' to it to clear it.
457 */
459 return;
460}
#define BIT7
Definition: common.h:88
#define BIT6
Definition: common.h:87
#define CAN_ACR(can_base)
CAN Acceptance Code Register RW, default 00000000h.
Definition: can.h:78
#define CAN_RXBUF(can_base)
CAN Receive Buffer Register RO, default 00000000h.
Definition: can.h:76
#define CAN_AMR(can_base)
CAN Acceptance Mask Register RW, default 00000000h.
Definition: can.h:80
#define CAN_TXBUF(can_base)
CAN Transmit Buffer Register RW, default 00000000h.
Definition: can.h:74
#define CAN_ACR_SINGLE_STD_DB1
Definition: can.h:244
#define CAN_ACR_DUAL_RTR2
Definition: can.h:240
#define CAN_ACR_DUAL_ID2
Definition: can.h:238
#define CAN_ACR_SINGLE_STD_RTR
Definition: can.h:243
#define CAN_ACR_SINGLE_STD_ID
Definition: can.h:242
#define CAN_ACR_SINGLE_STD_DB2
Definition: can.h:245
#define CAN_ACR_SINGLE_EXT_ID
Definition: can.h:247
#define CAN_ACR_DUAL_DB_UPPER
Definition: can.h:235
#define CAN_ACR_DUAL_ID1
Definition: can.h:237
#define CAN_ACR_DUAL_RTR1
Definition: can.h:239
#define CAN_ACR_DUAL_DB_LOWER
Definition: can.h:236
#define CAN_ACR_SINGLE_EXT_RTR
Definition: can.h:248
void can_filter_single_std(uint32_t canport, uint32_t id, uint32_t id_mask, uint8_t db1, uint8_t db1_mask, uint8_t db2, uint8_t db2_mask)
CAN Filter Single Standard Frame Notes:
Definition: can.c:160
void can_enable(uint32_t canport)
CAN Enable Enable the CAN peripheral and its associated FIFOs/counters/interrupts.
Definition: can.c:41
void can_filter_single_std_rtr(uint32_t canport, uint32_t id, uint32_t id_mask, uint8_t db1, uint8_t db1_mask, uint8_t db2, uint8_t db2_mask)
CAN Filter Single Standard Frame w/RTR set Notes:
Definition: can.c:196
void can_filter_single_ext(uint32_t canport, uint32_t id, uint32_t id_mask)
CAN Filter Single Extended Frame Notes:
Definition: can.c:227
void can_abort_transmit(uint32_t canport)
CAN Abort Transmit Aborts the current transmission.
Definition: can.c:369
void can_filter_single_ext_rtr(uint32_t canport, uint32_t id, uint32_t id_mask)
CAN Filter Single Extended Frame w/RTR set Notes:
Definition: can.c:252
void can_disable(uint32_t canport)
CAN Disable Disable the CAN peripheral and all associated FIFOs/counters/interrupts.
Definition: can.c:50
void can_filter_clear(uint32_t canport)
CAN Filter Clear Clear the message filters to receive all messages.
Definition: can.c:96
void can_filter_dual(uint32_t canport, uint32_t id1, uint32_t id1_mask, uint32_t id2, uint32_t id2_mask, uint8_t db, uint8_t db_mask)
CAN Dual Filter Standard Frame Notes:
Definition: can.c:123
void can_init(uint32_t canport, bool listen_only, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool sam3, uint32_t brp)
CAN Init Initialize the selected CAN peripheral block.
Definition: can.c:65
void can_receive(uint32_t canport, uint32_t *id, bool *ext, bool *rtr, uint8_t *length, uint8_t *data)
CAN Receive Message If no data is in the RX buffer, id and length are set to 0.
Definition: can.c:384
void can_enable_irq(uint32_t canport, uint8_t irq)
CAN Enable IRQ.
Definition: can.c:268
void can_disable_irq(uint32_t canport, uint8_t irq)
CAN Disable IRQ.
Definition: can.c:278
bool can_transmit_ext(uint32_t canport, uint32_t id, bool rtr, uint8_t length, const uint8_t *data)
CAN Transmit Extended Frame.
Definition: can.c:330
bool can_transmit_std(uint32_t canport, uint32_t id, bool rtr, uint8_t length, const uint8_t *data)
CAN Transmit Standard Frame.
Definition: can.c:292
#define CAN_BITS_4_0
Definition: can.h:256
#define CAN_BITS_2_0
Definition: can.h:254
#define CAN_BITS_15_8
Definition: can.h:262
#define CAN_BITS_10_3
Definition: can.h:258
#define CAN_BITS_28_21
Definition: can.h:261
#define CAN_BITS_7_3
Definition: can.h:257
#define CAN_BITS_12_5
Definition: can.h:259
#define CAN_BITS_20_13
Definition: can.h:260
#define CAN_BITS_23_16
Definition: can.h:263
#define CAN_BITS_31_24
Definition: can.h:264
#define CAN_BITS_3_0
Definition: can.h:255
#define CAN_BITS_23_21
Definition: can.h:265
#define CAN_BTR1_BTR0_RMC_IMR(can_base)
This is the 32-bit memory mapped read/write accessor for:
Definition: can.h:70
#define CAN_BTR0_SJW(val)
Definition: can.h:194
#define CAN_BTR0_BRP(val)
Definition: can.h:191
#define CAN_BTR1_SAM
Definition: can.h:207
#define CAN_BTR1_TSEG2(val)
Definition: can.h:206
#define CAN_BTR1_TSEG1(val)
Definition: can.h:202
#define CAN_CMR_AT
AT: Abort transmission.
Definition: can.h:111
#define CAN_CMR_TR
TR: Transmit Request.
Definition: can.h:113
#define CAN_ISR_RI
RI: Receive Interrupt.
Definition: can.h:148
#define CAN_ISR_ACKNOWLEDGE(can_base, isr)
This is a helper to acknowledge an ISR.
Definition: can.h:156
#define CAN_ISR_SR_CMR_MR(can_base)
This is the 32-bit memory mapped read/write accessor for:
Definition: can.h:54
#define CAN_ISR_SR_CMR_MR_CLEAR(can_base, bits)
Definition: can.h:57
#define CAN_ISR_SR_CMR_MR_SET(can_base, bits)
Definition: can.h:55
#define CAN_MR_RM
RM: Reset Mode.
Definition: can.h:104
#define CAN_MR_AFM
AFM: Acceptance Filter Mode.
Definition: can.h:100
#define CAN_MR_LOM
LOM: Listen only mode.
Definition: can.h:102
#define CAN_RMC(can_base)
Definition: can.h:183
#define CAN_SR_TBS
TBS: Transmit Buffer Status.
Definition: can.h:128