65void can_init(uint32_t canport,
bool listen_only, uint32_t sjw,
66 uint32_t tseg1, uint32_t tseg2,
67 bool sam3, uint32_t brp) {
100 CAN_AMR(canport) = 0xFFFFFFFFu;
124 uint32_t id2, uint32_t id2_mask,
125 uint8_t db, uint8_t db_mask) {
130 CAN_ACR(canport) = __builtin_bswap32(word);
137 CAN_AMR(canport) = __builtin_bswap32(word);
161 uint8_t db1, uint8_t db1_mask,
162 uint8_t db2, uint8_t db2_mask) {
167 CAN_ACR(canport) = __builtin_bswap32(word);
173 CAN_AMR(canport) = __builtin_bswap32(word);
197 uint8_t db1, uint8_t db1_mask,
198 uint8_t db2, uint8_t db2_mask) {
203 CAN_ACR(canport) = __builtin_bswap32(word);
208 CAN_AMR(canport) = __builtin_bswap32(word);
230 CAN_ACR(canport) = __builtin_bswap32(word);
233 CAN_AMR(canport) = __builtin_bswap32(word);
255 CAN_ACR(canport) = __builtin_bswap32(word);
258 CAN_AMR(canport) = __builtin_bswap32(word);
293 const uint8_t *data) {
302 | (((length > 0) ? data[0] : 0) << 24);
306 word = (data[1] << 0) | (data[2] << 8)
307 | (data[3] << 16) | (data[4] << 24);
312 word = (data[5] << 0) | (data[6] << 8) | (data[7] << 16);
331 const uint8_t *data) {
345 word |= (data[0] << 8) | (data[1] << 16) | (data[2] << 24);
350 word = (data[3] << 0) | (data[4] << 8)
351 | (data[5] << 16) | (data[6] << 24);
384void can_receive(uint32_t canport, uint32_t *
id,
bool *ext,
bool *rtr, uint8_t *length,
391 uint32_t can_buffer =
CAN_RXBUF(canport);
393 bool is_extended = can_buffer &
BIT7;
398 *rtr = can_buffer &
BIT6;
413 data[0] = can_buffer >> 8;
414 data[1] = can_buffer >> 16;
415 data[2] = can_buffer >> 24;
418 data[3] = can_buffer;
419 data[4] = can_buffer >> 8;
420 data[5] = can_buffer >> 16;
421 data[6] = can_buffer >> 24;
425 data[7] = can_buffer;
432 data[0] = can_buffer >> 24;
435 data[1] = can_buffer;
436 data[2] = can_buffer >> 8;
437 data[3] = can_buffer >> 16;
438 data[4] = can_buffer >> 24;
442 data[5] = can_buffer;
443 data[6] = can_buffer >> 8;
444 data[7] = can_buffer >> 16;
#define CAN_ACR(can_base)
CAN Acceptance Code Register RW, default 00000000h.
#define CAN_RXBUF(can_base)
CAN Receive Buffer Register RO, default 00000000h.
#define CAN_AMR(can_base)
CAN Acceptance Mask Register RW, default 00000000h.
#define CAN_TXBUF(can_base)
CAN Transmit Buffer Register RW, default 00000000h.
#define CAN_ACR_SINGLE_STD_DB1
#define CAN_ACR_DUAL_RTR2
#define CAN_ACR_SINGLE_STD_RTR
#define CAN_ACR_SINGLE_STD_ID
#define CAN_ACR_SINGLE_STD_DB2
#define CAN_ACR_SINGLE_EXT_ID
#define CAN_ACR_DUAL_DB_UPPER
#define CAN_ACR_DUAL_RTR1
#define CAN_ACR_DUAL_DB_LOWER
#define CAN_ACR_SINGLE_EXT_RTR
void can_filter_single_std(uint32_t canport, uint32_t id, uint32_t id_mask, uint8_t db1, uint8_t db1_mask, uint8_t db2, uint8_t db2_mask)
CAN Filter Single Standard Frame Notes:
void can_enable(uint32_t canport)
CAN Enable Enable the CAN peripheral and its associated FIFOs/counters/interrupts.
void can_filter_single_std_rtr(uint32_t canport, uint32_t id, uint32_t id_mask, uint8_t db1, uint8_t db1_mask, uint8_t db2, uint8_t db2_mask)
CAN Filter Single Standard Frame w/RTR set Notes:
void can_filter_single_ext(uint32_t canport, uint32_t id, uint32_t id_mask)
CAN Filter Single Extended Frame Notes:
void can_abort_transmit(uint32_t canport)
CAN Abort Transmit Aborts the current transmission.
void can_filter_single_ext_rtr(uint32_t canport, uint32_t id, uint32_t id_mask)
CAN Filter Single Extended Frame w/RTR set Notes:
void can_disable(uint32_t canport)
CAN Disable Disable the CAN peripheral and all associated FIFOs/counters/interrupts.
void can_filter_clear(uint32_t canport)
CAN Filter Clear Clear the message filters to receive all messages.
void can_filter_dual(uint32_t canport, uint32_t id1, uint32_t id1_mask, uint32_t id2, uint32_t id2_mask, uint8_t db, uint8_t db_mask)
CAN Dual Filter Standard Frame Notes:
void can_init(uint32_t canport, bool listen_only, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool sam3, uint32_t brp)
CAN Init Initialize the selected CAN peripheral block.
void can_receive(uint32_t canport, uint32_t *id, bool *ext, bool *rtr, uint8_t *length, uint8_t *data)
CAN Receive Message If no data is in the RX buffer, id and length are set to 0.
void can_enable_irq(uint32_t canport, uint8_t irq)
CAN Enable IRQ.
void can_disable_irq(uint32_t canport, uint8_t irq)
CAN Disable IRQ.
bool can_transmit_ext(uint32_t canport, uint32_t id, bool rtr, uint8_t length, const uint8_t *data)
CAN Transmit Extended Frame.
bool can_transmit_std(uint32_t canport, uint32_t id, bool rtr, uint8_t length, const uint8_t *data)
CAN Transmit Standard Frame.
#define CAN_BTR1_BTR0_RMC_IMR(can_base)
This is the 32-bit memory mapped read/write accessor for:
#define CAN_BTR0_SJW(val)
#define CAN_BTR0_BRP(val)
#define CAN_BTR1_TSEG2(val)
#define CAN_BTR1_TSEG1(val)
#define CAN_CMR_AT
AT: Abort transmission.
#define CAN_CMR_TR
TR: Transmit Request.
#define CAN_ISR_RI
RI: Receive Interrupt.
#define CAN_ISR_ACKNOWLEDGE(can_base, isr)
This is a helper to acknowledge an ISR.
#define CAN_ISR_SR_CMR_MR(can_base)
This is the 32-bit memory mapped read/write accessor for:
#define CAN_ISR_SR_CMR_MR_CLEAR(can_base, bits)
#define CAN_ISR_SR_CMR_MR_SET(can_base, bits)
#define CAN_MR_RM
RM: Reset Mode.
#define CAN_MR_AFM
AFM: Acceptance Filter Mode.
#define CAN_MR_LOM
LOM: Listen only mode.
#define CAN_RMC(can_base)
#define CAN_SR_TBS
TBS: Transmit Buffer Status.