#include <libopencm3/stm32/pwr.h>
#include <libopencm3/stm32/common/rcc_common_all.h>

Include dependency graph for f4/rcc.h:

Data Structures
struct	rcc_clock_scale

Macros
#define	RCC_CR MMIO32(RCC_BASE + 0x00)
	Clock control register. More...

#define	RCC_PLLCFGR MMIO32(RCC_BASE + 0x04)
	PLL Configuration register. More...

#define	RCC_CFGR MMIO32(RCC_BASE + 0x08)
	Clock Configuration register. More...

#define	RCC_CIR MMIO32(RCC_BASE + 0x0c)
	Clock interrupt register. More...

#define	RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10)
	AHB1 peripheral reset register. More...

#define	RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14)
	AHB2 peripheral reset register. More...

#define	RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18)
	AHB3 peripheral reset register. More...

#define	RCC_APB1RSTR MMIO32(RCC_BASE + 0x20)
	APB1 peripheral reset register. More...

#define	RCC_APB2RSTR MMIO32(RCC_BASE + 0x24)
	APB2 peripheral reset register. More...

#define	RCC_AHB1ENR MMIO32(RCC_BASE + 0x30)
	AHB1 peripheral enable register. More...

#define	RCC_AHB2ENR MMIO32(RCC_BASE + 0x34)
	AHB2 peripheral enable register. More...

#define	RCC_AHB3ENR MMIO32(RCC_BASE + 0x38)
	AHB3 peripheral enable register. More...

#define	RCC_APB1ENR MMIO32(RCC_BASE + 0x40)
	APB1 peripheral enable register. More...

#define	RCC_APB2ENR MMIO32(RCC_BASE + 0x44)
	APB2 peripheral enable register. More...

#define	RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50)
	AHB1 peripheral enable in low power register. More...

#define	RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54)
	AHB2 peripheral enable in low power register. More...

#define	RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58)
	AHB3 peripheral enable in low power register. More...

#define	RCC_APB1LPENR MMIO32(RCC_BASE + 0x60)
	APB1 peripheral enable in low power register. More...

#define	RCC_APB2LPENR MMIO32(RCC_BASE + 0x64)
	APB2 peripheral enable in low power register. More...

#define	RCC_BDCR MMIO32(RCC_BASE + 0x70)
	Backup Domain control register. More...

#define	RCC_CSR MMIO32(RCC_BASE + 0x74)
	Clock control and status register. More...

#define	RCC_SSCGR MMIO32(RCC_BASE + 0x80)
	Spread spectrum clock generation register. More...

#define	RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84)
	PLLI2S configuration register. More...

#define	RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88)
	PLLSAI configuration register. More...

#define	RCC_DCKCFGR MMIO32(RCC_BASE + 0x8C)
	Dedicated clocks configuration register. More...

#define	RCC_CKGATENR MMIO32(RCC_BASE + 0x90)
	RCC clocks gated enable register. More...

#define	RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x94)
	RCC Dedicated Clocks Configuration Register 2. More...

#define	RCC_CR_PLLSAIRDY (1 << 29)

#define	RCC_CR_PLLSAION (1 << 28)

#define	RCC_CR_PLLI2SRDY (1 << 27)

#define	RCC_CR_PLLI2SON (1 << 26)

#define	RCC_CR_PLLRDY (1 << 25)

#define	RCC_CR_PLLON (1 << 24)

#define	RCC_CR_CSSON (1 << 19)

#define	RCC_CR_HSEBYP (1 << 18)

#define	RCC_CR_HSERDY (1 << 17)

#define	RCC_CR_HSEON (1 << 16)

#define	RCC_CR_HSITRIM_SHIFT 3

#define	RCC_CR_HSITRIM_MASK 0x1f

#define	RCC_CR_HSIRDY (1 << 1)

#define	RCC_CR_HSION (1 << 0)

#define	RCC_PLLCFGR_PLLR_SHIFT 28

#define	RCC_PLLCFGR_PLLR_MASK 0x7

#define	RCC_PLLCFGR_PLLQ_SHIFT 24

#define	RCC_PLLCFGR_PLLQ_MASK 0xf

#define	RCC_PLLCFGR_PLLSRC (1 << 22)

#define	RCC_PLLCFGR_PLLP_SHIFT 16

#define	RCC_PLLCFGR_PLLP_MASK 0x3

#define	RCC_PLLCFGR_PLLN_SHIFT 6

#define	RCC_PLLCFGR_PLLN_MASK 0x1ff

#define	RCC_PLLCFGR_PLLM_SHIFT 0

#define	RCC_PLLCFGR_PLLM_MASK 0x3f

#define	RCC_CFGR_MCO2_SHIFT 30

#define	RCC_CFGR_MCO2_MASK 0x3

#define	RCC_CFGR_MCO2_SYSCLK 0x0

#define	RCC_CFGR_MCO2_PLLI2S 0x1

#define	RCC_CFGR_MCO2_HSE 0x2

#define	RCC_CFGR_MCO2_PLL 0x3

#define	RCC_CFGR_MCO2PRE_SHIFT 27

#define	RCC_CFGR_MCO2PRE_MASK 0x7

#define	RCC_CFGR_MCO1PRE_SHIFT 24

#define	RCC_CFGR_MCO1PRE_MASK 0x7

#define	RCC_CFGR_MCOPRE_DIV_NONE 0x0

#define	RCC_CFGR_MCOPRE_DIV_2 0x4

#define	RCC_CFGR_MCOPRE_DIV_3 0x5

#define	RCC_CFGR_MCOPRE_DIV_4 0x6

#define	RCC_CFGR_MCOPRE_DIV_5 0x7

#define	RCC_CFGR_PLLSRC_HSI_CLK 0x0

#define	RCC_CFGR_PLLSRC_HSE_CLK 0x1

#define	RCC_CFGR_I2SSRC (1 << 23)

#define	RCC_CFGR_MCO1_SHIFT 21

#define	RCC_CFGR_MCO1_MASK 0x3

#define	RCC_CFGR_MCO1_HSI 0x0

#define	RCC_CFGR_MCO1_LSE 0x1

#define	RCC_CFGR_MCO1_HSE 0x2

#define	RCC_CFGR_MCO1_PLL 0x3

#define	RCC_CFGR_MCO_SHIFT RCC_CFGR_MCO1_SHIFT

#define	RCC_CFGR_MCO_MASK RCC_CFGR_MCO1_MASK

#define	RCC_CFGR_RTCPRE_SHIFT 16

#define	RCC_CFGR_RTCPRE_MASK 0x1f

#define	RCC_CFGR_PPRE2_SHIFT 13

#define	RCC_CFGR_PPRE2_MASK 0x7

#define	RCC_CFGR_PPRE1_SHIFT 10

#define	RCC_CFGR_PPRE1_MASK 0x7

#define	RCC_CFGR_PPRE_NODIV 0x0

#define	RCC_CFGR_PPRE_DIV2 0x4

#define	RCC_CFGR_PPRE_DIV4 0x5

#define	RCC_CFGR_PPRE_DIV8 0x6

#define	RCC_CFGR_PPRE_DIV16 0x7

#define	RCC_CFGR_HPRE_SHIFT 4

#define	RCC_CFGR_HPRE_MASK 0xf

#define	RCC_CFGR_HPRE_NODIV 0x0

#define	RCC_CFGR_HPRE_DIV2 (0x8 + 0)

#define	RCC_CFGR_HPRE_DIV4 (0x8 + 1)

#define	RCC_CFGR_HPRE_DIV8 (0x8 + 2)

#define	RCC_CFGR_HPRE_DIV16 (0x8 + 3)

#define	RCC_CFGR_HPRE_DIV64 (0x8 + 4)

#define	RCC_CFGR_HPRE_DIV128 (0x8 + 5)

#define	RCC_CFGR_HPRE_DIV256 (0x8 + 6)

#define	RCC_CFGR_HPRE_DIV512 (0x8 + 7)

#define	RCC_CFGR_SWS_SHIFT 2

#define	RCC_CFGR_SWS_MASK 0x3

#define	RCC_CFGR_SWS_HSI 0x0

#define	RCC_CFGR_SWS_HSE 0x1

#define	RCC_CFGR_SWS_PLL 0x2

#define	RCC_CFGR_SW_SHIFT 0

#define	RCC_CFGR_SW_HSI 0x0

#define	RCC_CFGR_SW_HSE 0x1

#define	RCC_CFGR_SW_PLL 0x2

#define	RCC_CFGR_PPRE_DIV_NONE 0x0

#define	RCC_CFGR_PPRE_DIV_2 0x4

#define	RCC_CFGR_PPRE_DIV_4 0x5

#define	RCC_CFGR_PPRE_DIV_8 0x6

#define	RCC_CFGR_PPRE_DIV_16 0x7

#define	RCC_CFGR_HPRE_DIV_NONE 0x0

#define	RCC_CFGR_HPRE_DIV_2 (0x8 + 0)

#define	RCC_CFGR_HPRE_DIV_4 (0x8 + 1)

#define	RCC_CFGR_HPRE_DIV_8 (0x8 + 2)

#define	RCC_CFGR_HPRE_DIV_16 (0x8 + 3)

#define	RCC_CFGR_HPRE_DIV_64 (0x8 + 4)

#define	RCC_CFGR_HPRE_DIV_128 (0x8 + 5)

#define	RCC_CFGR_HPRE_DIV_256 (0x8 + 6)

#define	RCC_CFGR_HPRE_DIV_512 (0x8 + 7)

#define	RCC_CIR_CSSC (1 << 23)

#define	RCC_CIR_PLLSAIRDYC (1 << 22)

#define	RCC_CIR_PLLI2SRDYC (1 << 21)

#define	RCC_CIR_PLLRDYC (1 << 20)

#define	RCC_CIR_HSERDYC (1 << 19)

#define	RCC_CIR_HSIRDYC (1 << 18)

#define	RCC_CIR_LSERDYC (1 << 17)

#define	RCC_CIR_LSIRDYC (1 << 16)

#define	RCC_CIR_PLLSAIRDYIE (1 << 14)

#define	RCC_CIR_PLLI2SRDYIE (1 << 13)

#define	RCC_CIR_PLLRDYIE (1 << 12)

#define	RCC_CIR_HSERDYIE (1 << 11)

#define	RCC_CIR_HSIRDYIE (1 << 10)

#define	RCC_CIR_LSERDYIE (1 << 9)

#define	RCC_CIR_LSIRDYIE (1 << 8)

#define	RCC_CIR_CSSF (1 << 7)

#define	RCC_CIR_PLLSAIRDYF (1 << 6)

#define	RCC_CIR_PLLI2SRDYF (1 << 5)

#define	RCC_CIR_PLLRDYF (1 << 4)

#define	RCC_CIR_HSERDYF (1 << 3)

#define	RCC_CIR_HSIRDYF (1 << 2)

#define	RCC_CIR_LSERDYF (1 << 1)

#define	RCC_CIR_LSIRDYF (1 << 0)

#define	RCC_AHB1RSTR_OTGHSRST (1 << 29)

#define	RCC_AHB1RSTR_ETHMACRST (1 << 25)

#define	RCC_AHB1RSTR_DMA2DRST (1 << 23)

#define	RCC_AHB1RSTR_DMA2RST (1 << 22)

#define	RCC_AHB1RSTR_DMA1RST (1 << 21)

#define	RCC_AHB1RSTR_CRCRST (1 << 12)

#define	RCC_AHB1RSTR_GPIOKRST (1 << 10)

#define	RCC_AHB1RSTR_GPIOJRST (1 << 9)

#define	RCC_AHB1RSTR_GPIOIRST (1 << 8)

#define	RCC_AHB1RSTR_GPIOHRST (1 << 7)

#define	RCC_AHB1RSTR_GPIOGRST (1 << 6)

#define	RCC_AHB1RSTR_GPIOFRST (1 << 5)

#define	RCC_AHB1RSTR_GPIOERST (1 << 4)

#define	RCC_AHB1RSTR_GPIODRST (1 << 3)

#define	RCC_AHB1RSTR_GPIOCRST (1 << 2)

#define	RCC_AHB1RSTR_GPIOBRST (1 << 1)

#define	RCC_AHB1RSTR_GPIOARST (1 << 0)

#define	RCC_AHB1RSTR_IOPKRST RCC_AHB1RSTR_GPIOKRST

#define	RCC_AHB1RSTR_IOPJRST RCC_AHB1RSTR_GPIOJRST

#define	RCC_AHB1RSTR_IOPIRST RCC_AHB1RSTR_GPIOIRST

#define	RCC_AHB1RSTR_IOPHRST RCC_AHB1RSTR_GPIOHRST

#define	RCC_AHB1RSTR_IOPGRST RCC_AHB1RSTR_GPIOGRST

#define	RCC_AHB1RSTR_IOPFRST RCC_AHB1RSTR_GPIOFRST

#define	RCC_AHB1RSTR_IOPERST RCC_AHB1RSTR_GPIOERST

#define	RCC_AHB1RSTR_IOPDRST RCC_AHB1RSTR_GPIODRST

#define	RCC_AHB1RSTR_IOPCRST RCC_AHB1RSTR_GPIOCRST

#define	RCC_AHB1RSTR_IOPBRST RCC_AHB1RSTR_GPIOBRST

#define	RCC_AHB1RSTR_IOPARST RCC_AHB1RSTR_GPIOARST

#define	RCC_AHB2RSTR_OTGFSRST (1 << 7)

#define	RCC_AHB2RSTR_RNGRST (1 << 6)

#define	RCC_AHB2RSTR_HASHRST (1 << 5)

#define	RCC_AHB2RSTR_CRYPRST (1 << 4)

#define	RCC_AHB2RSTR_DCMIRST (1 << 0)

#define	RCC_AHB3RSTR_QSPIRST (1 << 1)

#define	RCC_AHB3RSTR_FSMCRST (1 << 0)

#define	RCC_APB1RSTR_UART8RST (1 << 31)

#define	RCC_APB1RSTR_UART7RST (1 << 30)

#define	RCC_APB1RSTR_DACRST (1 << 29)

#define	RCC_APB1RSTR_PWRRST (1 << 28)

#define	RCC_APB1RSTR_CAN2RST (1 << 26)

#define	RCC_APB1RSTR_CAN1RST (1 << 25)

#define	RCC_APB1RSTR_I2C3RST (1 << 23)

#define	RCC_APB1RSTR_I2C2RST (1 << 22)

#define	RCC_APB1RSTR_I2C1RST (1 << 21)

#define	RCC_APB1RSTR_UART5RST (1 << 20)

#define	RCC_APB1RSTR_UART4RST (1 << 19)

#define	RCC_APB1RSTR_USART3RST (1 << 18)

#define	RCC_APB1RSTR_USART2RST (1 << 17)

#define	RCC_APB1RSTR_SPI3RST (1 << 15)

#define	RCC_APB1RSTR_SPI2RST (1 << 14)

#define	RCC_APB1RSTR_WWDGRST (1 << 11)

#define	RCC_APB1RSTR_TIM14RST (1 << 8)

#define	RCC_APB1RSTR_TIM13RST (1 << 7)

#define	RCC_APB1RSTR_TIM12RST (1 << 6)

#define	RCC_APB1RSTR_TIM7RST (1 << 5)

#define	RCC_APB1RSTR_TIM6RST (1 << 4)

#define	RCC_APB1RSTR_TIM5RST (1 << 3)

#define	RCC_APB1RSTR_TIM4RST (1 << 2)

#define	RCC_APB1RSTR_TIM3RST (1 << 1)

#define	RCC_APB1RSTR_TIM2RST (1 << 0)

#define	RCC_APB2RSTR_DSIRST (1 << 27)

#define	RCC_APB2RSTR_LTDCRST (1 << 26)

#define	RCC_APB2RSTR_SAI1RST (1 << 22)

#define	RCC_APB2RSTR_SPI6RST (1 << 21)

#define	RCC_APB2RSTR_SPI5RST (1 << 20)

#define	RCC_APB2RSTR_TIM11RST (1 << 18)

#define	RCC_APB2RSTR_TIM10RST (1 << 17)

#define	RCC_APB2RSTR_TIM9RST (1 << 16)

#define	RCC_APB2RSTR_SYSCFGRST (1 << 14)

#define	RCC_APB2RSTR_SPI4RST (1 << 13)

#define	RCC_APB2RSTR_SPI1RST (1 << 12)

#define	RCC_APB2RSTR_SDIORST (1 << 11)

#define	RCC_APB2RSTR_ADCRST (1 << 8)

#define	RCC_APB2RSTR_USART6RST (1 << 5)

#define	RCC_APB2RSTR_USART1RST (1 << 4)

#define	RCC_APB2RSTR_TIM8RST (1 << 1)

#define	RCC_APB2RSTR_TIM1RST (1 << 0)

#define	RCC_AHB1ENR_OTGHSULPIEN (1 << 30)

#define	RCC_AHB1ENR_OTGHSEN (1 << 29)

#define	RCC_AHB1ENR_ETHMACPTPEN (1 << 28)

#define	RCC_AHB1ENR_ETHMACRXEN (1 << 27)

#define	RCC_AHB1ENR_ETHMACTXEN (1 << 26)

#define	RCC_AHB1ENR_ETHMACEN (1 << 25)

#define	RCC_AHB1ENR_DMA2DEN (1 << 23)

#define	RCC_AHB1ENR_DMA2EN (1 << 22)

#define	RCC_AHB1ENR_DMA1EN (1 << 21)

#define	RCC_AHB1ENR_CCMDATARAMEN (1 << 20)

#define	RCC_AHB1ENR_BKPSRAMEN (1 << 18)

#define	RCC_AHB1ENR_CRCEN (1 << 12)

#define	RCC_AHB1ENR_GPIOKEN (1 << 10)

#define	RCC_AHB1ENR_GPIOJEN (1 << 9)

#define	RCC_AHB1ENR_GPIOIEN (1 << 8)

#define	RCC_AHB1ENR_GPIOHEN (1 << 7)

#define	RCC_AHB1ENR_GPIOGEN (1 << 6)

#define	RCC_AHB1ENR_GPIOFEN (1 << 5)

#define	RCC_AHB1ENR_GPIOEEN (1 << 4)

#define	RCC_AHB1ENR_GPIODEN (1 << 3)

#define	RCC_AHB1ENR_GPIOCEN (1 << 2)

#define	RCC_AHB1ENR_GPIOBEN (1 << 1)

#define	RCC_AHB1ENR_GPIOAEN (1 << 0)

#define	RCC_AHB1ENR_IOPKEN RCC_AHB1ENR_GPIOKEN

#define	RCC_AHB1ENR_IOPJEN RCC_AHB1ENR_GPIOJEN

#define	RCC_AHB1ENR_IOPIEN RCC_AHB1ENR_GPIOIEN

#define	RCC_AHB1ENR_IOPHEN RCC_AHB1ENR_GPIOHEN

#define	RCC_AHB1ENR_IOPGEN RCC_AHB1ENR_GPIOGEN

#define	RCC_AHB1ENR_IOPFEN RCC_AHB1ENR_GPIOFEN

#define	RCC_AHB1ENR_IOPEEN RCC_AHB1ENR_GPIOEEN

#define	RCC_AHB1ENR_IOPDEN RCC_AHB1ENR_GPIODEN

#define	RCC_AHB1ENR_IOPCEN RCC_AHB1ENR_GPIOCEN

#define	RCC_AHB1ENR_IOPBEN RCC_AHB1ENR_GPIOBEN

#define	RCC_AHB1ENR_IOPAEN RCC_AHB1ENR_GPIOAEN

#define	RCC_AHB2ENR_OTGFSEN (1 << 7)

#define	RCC_AHB2ENR_RNGEN (1 << 6)

#define	RCC_AHB2ENR_HASHEN (1 << 5)

#define	RCC_AHB2ENR_CRYPEN (1 << 4)

#define	RCC_AHB2ENR_DCMIEN (1 << 0)

#define	RCC_AHB3ENR_QSPIEN (1 << 1)

#define	RCC_AHB3ENR_FSMCEN (1 << 0)

#define	RCC_AHB3ENR_FMCEN (1 << 0)

#define	RCC_APB1ENR_UART8EN (1 << 31)

#define	RCC_APB1ENR_UART7EN (1 << 30)

#define	RCC_APB1ENR_DACEN (1 << 29)

#define	RCC_APB1ENR_PWREN (1 << 28)

#define	RCC_APB1ENR_CAN2EN (1 << 26)

#define	RCC_APB1ENR_CAN1EN (1 << 25)

#define	RCC_APB1ENR_I2C3EN (1 << 23)

#define	RCC_APB1ENR_I2C2EN (1 << 22)

#define	RCC_APB1ENR_I2C1EN (1 << 21)

#define	RCC_APB1ENR_UART5EN (1 << 20)

#define	RCC_APB1ENR_UART4EN (1 << 19)

#define	RCC_APB1ENR_USART3EN (1 << 18)

#define	RCC_APB1ENR_USART2EN (1 << 17)

#define	RCC_APB1ENR_SPI3EN (1 << 15)

#define	RCC_APB1ENR_SPI2EN (1 << 14)

#define	RCC_APB1ENR_WWDGEN (1 << 11)

#define	RCC_APB1ENR_TIM14EN (1 << 8)

#define	RCC_APB1ENR_TIM13EN (1 << 7)

#define	RCC_APB1ENR_TIM12EN (1 << 6)

#define	RCC_APB1ENR_TIM7EN (1 << 5)

#define	RCC_APB1ENR_TIM6EN (1 << 4)

#define	RCC_APB1ENR_TIM5EN (1 << 3)

#define	RCC_APB1ENR_TIM4EN (1 << 2)

#define	RCC_APB1ENR_TIM3EN (1 << 1)

#define	RCC_APB1ENR_TIM2EN (1 << 0)

#define	RCC_APB2ENR_DSIEN (1 << 27)

#define	RCC_APB2ENR_LTDCEN (1 << 26)

#define	RCC_APB2ENR_SAI1EN (1 << 22)

#define	RCC_APB2ENR_SPI6EN (1 << 21)

#define	RCC_APB2ENR_SPI5EN (1 << 20)

#define	RCC_APB2ENR_TIM11EN (1 << 18)

#define	RCC_APB2ENR_TIM10EN (1 << 17)

#define	RCC_APB2ENR_TIM9EN (1 << 16)

#define	RCC_APB2ENR_SYSCFGEN (1 << 14)

#define	RCC_APB2ENR_SPI4EN (1 << 13)

#define	RCC_APB2ENR_SPI1EN (1 << 12)

#define	RCC_APB2ENR_SDIOEN (1 << 11)

#define	RCC_APB2ENR_ADC3EN (1 << 10)

#define	RCC_APB2ENR_ADC2EN (1 << 9)

#define	RCC_APB2ENR_ADC1EN (1 << 8)

#define	RCC_APB2ENR_USART6EN (1 << 5)

#define	RCC_APB2ENR_USART1EN (1 << 4)

#define	RCC_APB2ENR_TIM8EN (1 << 1)

#define	RCC_APB2ENR_TIM1EN (1 << 0)

#define	RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30)

#define	RCC_AHB1LPENR_OTGHSLPEN (1 << 29)

#define	RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28)

#define	RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27)

#define	RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26)

#define	RCC_AHB1LPENR_ETHMACLPEN (1 << 25)

#define	RCC_AHB1LPENR_DMA2DLPEN (1 << 23)

#define	RCC_AHB1LPENR_DMA2LPEN (1 << 22)

#define	RCC_AHB1LPENR_DMA1LPEN (1 << 21)

#define	RCC_AHB1LPENR_SRAM3LPEN (1 << 19)

#define	RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18)

#define	RCC_AHB1LPENR_SRAM2LPEN (1 << 17)

#define	RCC_AHB1LPENR_SRAM1LPEN (1 << 16)

#define	RCC_AHB1LPENR_FLITFLPEN (1 << 15)

#define	RCC_AHB1LPENR_CRCLPEN (1 << 12)

#define	RCC_AHB1LPENR_GPIOKLPEN (1 << 10)

#define	RCC_AHB1LPENR_GPIOJLPEN (1 << 9)

#define	RCC_AHB1LPENR_GPIOILPEN (1 << 8)

#define	RCC_AHB1LPENR_GPIOHLPEN (1 << 7)

#define	RCC_AHB1LPENR_GPIOGLPEN (1 << 6)

#define	RCC_AHB1LPENR_GPIOFLPEN (1 << 5)

#define	RCC_AHB1LPENR_GPIOELPEN (1 << 4)

#define	RCC_AHB1LPENR_GPIODLPEN (1 << 3)

#define	RCC_AHB1LPENR_GPIOCLPEN (1 << 2)

#define	RCC_AHB1LPENR_GPIOBLPEN (1 << 1)

#define	RCC_AHB1LPENR_GPIOALPEN (1 << 0)

#define	RCC_AHB1LPENR_IOPKLPEN RCC_AHB1LPENR_GPIOKLPEN

#define	RCC_AHB1LPENR_IOPJLPEN RCC_AHB1LPENR_GPIOJLPEN

#define	RCC_AHB1LPENR_IOPILPEN RCC_AHB1LPENR_GPIOILPEN

#define	RCC_AHB1LPENR_IOPHLPEN RCC_AHB1LPENR_GPIOHLPEN

#define	RCC_AHB1LPENR_IOPGLPEN RCC_AHB1LPENR_GPIOGLPEN

#define	RCC_AHB1LPENR_IOPFLPEN RCC_AHB1LPENR_GPIOFLPEN

#define	RCC_AHB1LPENR_IOPELPEN RCC_AHB1LPENR_GPIOELPEN

#define	RCC_AHB1LPENR_IOPDLPEN RCC_AHB1LPENR_GPIODLPEN

#define	RCC_AHB1LPENR_IOPCLPEN RCC_AHB1LPENR_GPIOCLPEN

#define	RCC_AHB1LPENR_IOPBLPEN RCC_AHB1LPENR_GPIOBLPEN

#define	RCC_AHB1LPENR_IOPALPEN RCC_AHB1LPENR_GPIOALPEN

#define	RCC_AHB2LPENR_OTGFSLPEN (1 << 7)

#define	RCC_AHB2LPENR_RNGLPEN (1 << 6)

#define	RCC_AHB2LPENR_HASHLPEN (1 << 5)

#define	RCC_AHB2LPENR_CRYPLPEN (1 << 4)

#define	RCC_AHB2LPENR_DCMILPEN (1 << 0)

#define	RCC_AHB3LPENR_QSPIEN (1 << 1)

#define	RCC_AHB3LPENR_FSMCLPEN (1 << 0)

#define	RCC_AHB3LPENR_FMCLPEN (1 << 0)

#define	RCC_APB1LPENR_UART8EN (1 << 31)

#define	RCC_APB1LPENR_UART7EN (1 << 30)

#define	RCC_APB1LPENR_DACLPEN (1 << 29)

#define	RCC_APB1LPENR_PWRLPEN (1 << 28)

#define	RCC_APB1LPENR_CAN2LPEN (1 << 26)

#define	RCC_APB1LPENR_CAN1LPEN (1 << 25)

#define	RCC_APB1LPENR_I2C3LPEN (1 << 23)

#define	RCC_APB1LPENR_I2C2LPEN (1 << 22)

#define	RCC_APB1LPENR_I2C1LPEN (1 << 21)

#define	RCC_APB1LPENR_UART5LPEN (1 << 20)

#define	RCC_APB1LPENR_UART4LPEN (1 << 19)

#define	RCC_APB1LPENR_USART3LPEN (1 << 18)

#define	RCC_APB1LPENR_USART2LPEN (1 << 17)

#define	RCC_APB1LPENR_SPI3LPEN (1 << 15)

#define	RCC_APB1LPENR_SPI2LPEN (1 << 14)

#define	RCC_APB1LPENR_WWDGLPEN (1 << 11)

#define	RCC_APB1LPENR_TIM14LPEN (1 << 8)

#define	RCC_APB1LPENR_TIM13LPEN (1 << 7)

#define	RCC_APB1LPENR_TIM12LPEN (1 << 6)

#define	RCC_APB1LPENR_TIM7LPEN (1 << 5)

#define	RCC_APB1LPENR_TIM6LPEN (1 << 4)

#define	RCC_APB1LPENR_TIM5LPEN (1 << 3)

#define	RCC_APB1LPENR_TIM4LPEN (1 << 2)

#define	RCC_APB1LPENR_TIM3LPEN (1 << 1)

#define	RCC_APB1LPENR_TIM2LPEN (1 << 0)

#define	RCC_APB2LPENR_DSILPEN (1 << 27)

#define	RCC_APB2LPENR_LTDCLPEN (1 << 26)

#define	RCC_APB2LPENR_SAI1LPEN (1 << 22)

#define	RCC_APB2LPENR_SPI6LPEN (1 << 21)

#define	RCC_APB2LPENR_SPI5LPEN (1 << 20)

#define	RCC_APB2LPENR_TIM11LPEN (1 << 18)

#define	RCC_APB2LPENR_TIM10LPEN (1 << 17)

#define	RCC_APB2LPENR_TIM9LPEN (1 << 16)

#define	RCC_APB2LPENR_SYSCFGLPEN (1 << 14)

#define	RCC_APB2LPENR_SPI1LPEN (1 << 12)

#define	RCC_APB2LPENR_SDIOLPEN (1 << 11)

#define	RCC_APB2LPENR_ADC3LPEN (1 << 10)

#define	RCC_APB2LPENR_ADC2LPEN (1 << 9)

#define	RCC_APB2LPENR_ADC1LPEN (1 << 8)

#define	RCC_APB2LPENR_USART6LPEN (1 << 5)

#define	RCC_APB2LPENR_USART1LPEN (1 << 4)

#define	RCC_APB2LPENR_TIM8LPEN (1 << 1)

#define	RCC_APB2LPENR_TIM1LPEN (1 << 0)

#define	RCC_BDCR_BDRST (1 << 16)

#define	RCC_BDCR_RTCEN (1 << 15)

#define	RCC_BDCR_RTCSEL_SHIFT 8

#define	RCC_BDCR_RTCSEL_MASK 0x3

#define	RCC_BDCR_RTCSEL_NONE 0

#define	RCC_BDCR_RTCSEL_LSE 1

#define	RCC_BDCR_RTCSEL_LSI 2

#define	RCC_BDCR_RTCSEL_HSE 3

#define	RCC_BDCR_LSEMOD (1 << 3)

#define	RCC_BDCR_LSEBYP (1 << 2)

#define	RCC_BDCR_LSERDY (1 << 1)

#define	RCC_BDCR_LSEON (1 << 0)

#define	RCC_CSR_LPWRRSTF (1 << 31)

#define	RCC_CSR_WWDGRSTF (1 << 30)

#define	RCC_CSR_IWDGRSTF (1 << 29)

#define	RCC_CSR_SFTRSTF (1 << 28)

#define	RCC_CSR_PORRSTF (1 << 27)

#define	RCC_CSR_PINRSTF (1 << 26)

#define	RCC_CSR_BORRSTF (1 << 25)

#define	RCC_CSR_RMVF (1 << 24)

#define	RCC_CSR_RESET_FLAGS

#define	RCC_CSR_LSIRDY (1 << 1)

#define	RCC_CSR_LSION (1 << 0)

#define	RCC_SSCGR_SSCGEN (1 << 31)

#define	RCC_SSCGR_SPREADSEL (1 << 30)

#define	RCC_SSCGR_INCSTEP_SHIFT 13

#define	RCC_SSCGR_INCSTEP_MASK 0x7fff

#define	RCC_SSCGR_MODPER_SHIFT 0

#define	RCC_SSCGR_MODPER_MASK 0x1fff

#define	RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28

#define	RCC_PLLI2SCFGR_PLLI2SR_MASK 0x7

#define	RCC_PLLI2SCFGR_PLLI2SQ_SHIFT 24

#define	RCC_PLLI2SCFGR_PLLI2SQ_MASK 0xf

#define	RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6

#define	RCC_PLLI2SCFGR_PLLI2SN_MASK 0x1ff

#define	RCC_PLLSAICFGR_PLLSAIR_SHIFT 28

#define	RCC_PLLSAICFGR_PLLSAIR_MASK 0x7

#define	RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24

#define	RCC_PLLSAICFGR_PLLSAIQ_MASK 0xF

#define	RCC_PLLSAICFGR_PLLSAIP_SHIFT 16

#define	RCC_PLLSAICFGR_PLLSAIP_MASK 0x3

#define	RCC_PLLSAICFGR_PLLSAIP_DIV2 0x0

#define	RCC_PLLSAICFGR_PLLSAIP_DIV4 0x1

#define	RCC_PLLSAICFGR_PLLSAIP_DIV6 0x2

#define	RCC_PLLSAICFGR_PLLSAIP_DIV8 0x3

#define	RCC_PLLSAICFGR_PLLSAIN_SHIFT 6

#define	RCC_PLLSAICFGR_PLLSAIN_MASK 0x1FF

#define	RCC_DCKCFGR_DSISEL (1 << 29)

#define	RCC_DCKCFGR_SDMMCSEL (1 << 28)

#define	RCC_DCKCFGR_48MSEL (1 << 27)

#define	RCC_DCKCFGR_TIMPRE (1 << 24)

#define	RCC_DCKCFGR_SAI1BSRC_SHIFT 22

#define	RCC_DCKCFGR_SAI1BSRC_MASK 0x3

#define	RCC_DCKCFGR_SAI1ASRC_SHIFT 20

#define	RCC_DCKCFGR_SAI1ASRC_MASK 0x3

#define	RCC_DCKCFGR_SAI1SRC_SAIQ 0x0

#define	RCC_DCKCFGR_SAI1SRC_I2SQ 0x1

#define	RCC_DCKCFGR_SAI1SRC_ALT 0x2

#define	RCC_DCKCFGR_SAI1SRC_ERROR 0x3

#define	RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16

#define	RCC_DCKCFGR_PLLSAIDIVR_MASK 0x3

#define	RCC_DCKCFGR_PLLSAIDIVR_DIVR_2 0x0

#define	RCC_DCKCFGR_PLLSAIDIVR_DIVR_4 0x1

#define	RCC_DCKCFGR_PLLSAIDIVR_DIVR_8 0x2

#define	RCC_DCKCFGR_PLLSAIDIVR_DIVR_16 0x3

#define	RCC_DCKCFGR_PLLSAIDIVQ_SHIFT 8

#define	RCC_DCKCFGR_PLLSAIDIVQ_MASK 0x1f

#define	RCC_DCKCFGR_PLLI2SDIVQ_SHIFT 0

#define	RCC_DCKCFGR_PLLI2SDIVQ_MASK 0x1f

#define	RCC_CKGATENR_EVTCL_CKEN (1<<7)

#define	RCC_CKGATENR_RCC_CKEN (1<<6)

#define	RCC_CKGATENR_FLITF_CKEN (1<<5)

#define	RCC_CKGATENR_SRAM_CKEN (1<<4)

#define	RCC_CKGATENR_SPARE_CKEN (1<<3)

#define	RCC_CKGATENR_CM4DBG_CKEN (1<<2)

#define	RCC_CKGATENR_AHB2APB2_CKEN (1<<1)

#define	RCC_CKGATENR_AHB2APB1_CKEN (1<<0)

#define	_REG_BIT(base, bit) (((base) << 5) + (bit))

Enumerations
enum	rcc_clock_3v3 { RCC_CLOCK_3V3_84MHZ , RCC_CLOCK_3V3_96MHZ , RCC_CLOCK_3V3_168MHZ , RCC_CLOCK_3V3_180MHZ , RCC_CLOCK_3V3_END }

enum	rcc_osc { RCC_PLL , RCC_PLLSAI , RCC_PLLI2S , RCC_HSE , RCC_HSI , RCC_LSE , RCC_LSI }

enum	rcc_periph_clken { RCC_GPIOA = _REG_BIT(0x30, 0) , RCC_GPIOB = _REG_BIT(0x30, 1) , RCC_GPIOC = _REG_BIT(0x30, 2) , RCC_GPIOD = _REG_BIT(0x30, 3) , RCC_GPIOE = _REG_BIT(0x30, 4) , RCC_GPIOF = _REG_BIT(0x30, 5) , RCC_GPIOG = _REG_BIT(0x30, 6) , RCC_GPIOH = _REG_BIT(0x30, 7) , RCC_GPIOI = _REG_BIT(0x30, 8) , RCC_GPIOJ = _REG_BIT(0x30, 9) , RCC_GPIOK = _REG_BIT(0x30, 10) , RCC_CRC = _REG_BIT(0x30, 12) , RCC_BKPSRAM = _REG_BIT(0x30, 18) , RCC_CCMDATARAM = _REG_BIT(0x30, 20) , RCC_DMA1 = _REG_BIT(0x30, 21) , RCC_DMA2 = _REG_BIT(0x30, 22) , RCC_DMA2D = _REG_BIT(0x30, 23) , RCC_ETHMAC = _REG_BIT(0x30, 25) , RCC_ETHMACTX = _REG_BIT(0x30, 26) , RCC_ETHMACRX = _REG_BIT(0x30, 27) , RCC_ETHMACPTP = _REG_BIT(0x30, 28) , RCC_OTGHS = _REG_BIT(0x30, 29) , RCC_OTGHSULPI = _REG_BIT(0x30, 30) , RCC_DCMI = _REG_BIT(0x34, 0) , RCC_CRYP = _REG_BIT(0x34, 4) , RCC_HASH = _REG_BIT(0x34, 5) , RCC_RNG = _REG_BIT(0x34, 6) , RCC_OTGFS = _REG_BIT(0x34, 7) , RCC_FSMC = _REG_BIT(0x38, 0) , RCC_FMC = _REG_BIT(0x38, 0) , RCC_QUADSPI = _REG_BIT(0x38, 1) , RCC_TIM2 = _REG_BIT(0x40, 0) , RCC_TIM3 = _REG_BIT(0x40, 1) , RCC_TIM4 = _REG_BIT(0x40, 2) , RCC_TIM5 = _REG_BIT(0x40, 3) , RCC_TIM6 = _REG_BIT(0x40, 4) , RCC_TIM7 = _REG_BIT(0x40, 5) , RCC_TIM12 = _REG_BIT(0x40, 6) , RCC_TIM13 = _REG_BIT(0x40, 7) , RCC_TIM14 = _REG_BIT(0x40, 8) , RCC_WWDG = _REG_BIT(0x40, 11) , RCC_SPI2 = _REG_BIT(0x40, 14) , RCC_SPI3 = _REG_BIT(0x40, 15) , RCC_USART2 = _REG_BIT(0x40, 17) , RCC_USART3 = _REG_BIT(0x40, 18) , RCC_UART4 = _REG_BIT(0x40, 19) , RCC_UART5 = _REG_BIT(0x40, 20) , RCC_I2C1 = _REG_BIT(0x40, 21) , RCC_I2C2 = _REG_BIT(0x40, 22) , RCC_I2C3 = _REG_BIT(0x40, 23) , RCC_CAN1 = _REG_BIT(0x40, 25) , RCC_CAN2 = _REG_BIT(0x40, 26) , RCC_PWR = _REG_BIT(0x40, 28) , RCC_DAC = _REG_BIT(0x40, 29) , RCC_UART7 = _REG_BIT(0x40, 30) , RCC_UART8 = _REG_BIT(0x40, 31) , RCC_TIM1 = _REG_BIT(0x44, 0) , RCC_TIM8 = _REG_BIT(0x44, 1) , RCC_USART1 = _REG_BIT(0x44, 4) , RCC_USART6 = _REG_BIT(0x44, 5) , RCC_ADC1 = _REG_BIT(0x44, 8) , RCC_ADC2 = _REG_BIT(0x44, 9) , RCC_ADC3 = _REG_BIT(0x44, 10) , RCC_SDIO = _REG_BIT(0x44, 11) , RCC_SPI1 = _REG_BIT(0x44, 12) , RCC_SPI4 = _REG_BIT(0x44, 13) , RCC_SYSCFG = _REG_BIT(0x44, 14) , RCC_TIM9 = _REG_BIT(0x44, 16) , RCC_TIM10 = _REG_BIT(0x44, 17) , RCC_TIM11 = _REG_BIT(0x44, 18) , RCC_SPI5 = _REG_BIT(0x44, 20) , RCC_SPI6 = _REG_BIT(0x44, 21) , RCC_SAI1EN = _REG_BIT(0x44, 22) , RCC_LTDC = _REG_BIT(0x44, 26) , RCC_DSI = _REG_BIT(0x44, 27) , RCC_RTC = _REG_BIT(0x70, 15) , SCC_GPIOA = _REG_BIT(0x50, 0) , SCC_GPIOB = _REG_BIT(0x50, 1) , SCC_GPIOC = _REG_BIT(0x50, 2) , SCC_GPIOD = _REG_BIT(0x50, 3) , SCC_GPIOE = _REG_BIT(0x50, 4) , SCC_GPIOF = _REG_BIT(0x50, 5) , SCC_GPIOG = _REG_BIT(0x50, 6) , SCC_GPIOH = _REG_BIT(0x50, 7) , SCC_GPIOI = _REG_BIT(0x50, 8) , SCC_GPIOJ = _REG_BIT(0x50, 9) , SCC_GPIOK = _REG_BIT(0x50, 10) , SCC_CRC = _REG_BIT(0x50, 12) , SCC_FLTIF = _REG_BIT(0x50, 15) , SCC_SRAM1 = _REG_BIT(0x50, 16) , SCC_SRAM2 = _REG_BIT(0x50, 17) , SCC_BKPSRAM = _REG_BIT(0x50, 18) , SCC_SRAM3 = _REG_BIT(0x50, 19) , SCC_DMA1 = _REG_BIT(0x50, 21) , SCC_DMA2 = _REG_BIT(0x50, 22) , SCC_DMA2D = _REG_BIT(0x50, 23) , SCC_ETHMAC = _REG_BIT(0x50, 25) , SCC_ETHMACTX = _REG_BIT(0x50, 26) , SCC_ETHMACRX = _REG_BIT(0x50, 27) , SCC_ETHMACPTP = _REG_BIT(0x50, 28) , SCC_OTGHS = _REG_BIT(0x50, 29) , SCC_OTGHSULPI = _REG_BIT(0x50, 30) , SCC_DCMI = _REG_BIT(0x54, 0) , SCC_CRYP = _REG_BIT(0x54, 4) , SCC_HASH = _REG_BIT(0x54, 5) , SCC_RNG = _REG_BIT(0x54, 6) , SCC_OTGFS = _REG_BIT(0x54, 7) , SCC_QSPIC = _REG_BIT(0x58, 1) , SCC_FMC = _REG_BIT(0x58, 0) , SCC_FSMC = _REG_BIT(0x58, 0) , SCC_TIM2 = _REG_BIT(0x60, 0) , SCC_TIM3 = _REG_BIT(0x60, 1) , SCC_TIM4 = _REG_BIT(0x60, 2) , SCC_TIM5 = _REG_BIT(0x60, 3) , SCC_TIM6 = _REG_BIT(0x60, 4) , SCC_TIM7 = _REG_BIT(0x60, 5) , SCC_TIM12 = _REG_BIT(0x60, 6) , SCC_TIM13 = _REG_BIT(0x60, 7) , SCC_TIM14 = _REG_BIT(0x60, 8) , SCC_WWDG = _REG_BIT(0x60, 11) , SCC_SPI2 = _REG_BIT(0x60, 14) , SCC_SPI3 = _REG_BIT(0x60, 15) , SCC_USART2 = _REG_BIT(0x60, 17) , SCC_USART3 = _REG_BIT(0x60, 18) , SCC_UART4 = _REG_BIT(0x60, 19) , SCC_UART5 = _REG_BIT(0x60, 20) , SCC_I2C1 = _REG_BIT(0x60, 21) , SCC_I2C2 = _REG_BIT(0x60, 22) , SCC_I2C3 = _REG_BIT(0x60, 23) , SCC_CAN1 = _REG_BIT(0x60, 25) , SCC_CAN2 = _REG_BIT(0x60, 26) , SCC_PWR = _REG_BIT(0x60, 28) , SCC_DAC = _REG_BIT(0x60, 29) , SCC_UART7 = _REG_BIT(0x60, 30) , SCC_UART8 = _REG_BIT(0x60, 31) , SCC_TIM1 = _REG_BIT(0x64, 0) , SCC_TIM8 = _REG_BIT(0x64, 1) , SCC_USART1 = _REG_BIT(0x64, 4) , SCC_USART6 = _REG_BIT(0x64, 5) , SCC_ADC1 = _REG_BIT(0x64, 8) , SCC_ADC2 = _REG_BIT(0x64, 9) , SCC_ADC3 = _REG_BIT(0x64, 10) , SCC_SDIO = _REG_BIT(0x64, 11) , SCC_SPI1 = _REG_BIT(0x64, 12) , SCC_SPI4 = _REG_BIT(0x64, 13) , SCC_SYSCFG = _REG_BIT(0x64, 14) , SCC_TIM9 = _REG_BIT(0x64, 16) , SCC_TIM10 = _REG_BIT(0x64, 17) , SCC_TIM11 = _REG_BIT(0x64, 18) , SCC_SPI5 = _REG_BIT(0x64, 20) , SCC_SPI6 = _REG_BIT(0x64, 21) , SCC_SAI1 = _REG_BIT(0x64, 22) , SCC_LTDC = _REG_BIT(0x64, 26) , SCC_DSI = _REG_BIT(0x64, 27) }

enum	rcc_periph_rst { RST_GPIOA = _REG_BIT(0x10, 0) , RST_GPIOB = _REG_BIT(0x10, 1) , RST_GPIOC = _REG_BIT(0x10, 2) , RST_GPIOD = _REG_BIT(0x10, 3) , RST_GPIOE = _REG_BIT(0x10, 4) , RST_GPIOF = _REG_BIT(0x10, 5) , RST_GPIOG = _REG_BIT(0x10, 6) , RST_GPIOH = _REG_BIT(0x10, 7) , RST_GPIOI = _REG_BIT(0x10, 8) , RST_GPIOJ = _REG_BIT(0x10, 9) , RST_GPIOK = _REG_BIT(0x10, 10) , RST_CRC = _REG_BIT(0x10, 12) , RST_DMA1 = _REG_BIT(0x10, 21) , RST_DMA2 = _REG_BIT(0x10, 22) , RST_DMA2D = _REG_BIT(0x10, 23) , RST_ETHMAC = _REG_BIT(0x10, 25) , RST_OTGHS = _REG_BIT(0x10, 29) , RST_DCMI = _REG_BIT(0x14, 0) , RST_CRYP = _REG_BIT(0x14, 4) , RST_HASH = _REG_BIT(0x14, 5) , RST_RNG = _REG_BIT(0x14, 6) , RST_OTGFS = _REG_BIT(0x14, 7) , RST_QSPI = _REG_BIT(0x18, 1) , RST_FSMC = _REG_BIT(0x18, 0) , RST_FMC = _REG_BIT(0x18, 0) , RST_TIM2 = _REG_BIT(0x20, 0) , RST_TIM3 = _REG_BIT(0x20, 1) , RST_TIM4 = _REG_BIT(0x20, 2) , RST_TIM5 = _REG_BIT(0x20, 3) , RST_TIM6 = _REG_BIT(0x20, 4) , RST_TIM7 = _REG_BIT(0x20, 5) , RST_TIM12 = _REG_BIT(0x20, 6) , RST_TIM13 = _REG_BIT(0x20, 7) , RST_TIM14 = _REG_BIT(0x20, 8) , RST_WWDG = _REG_BIT(0x20, 11) , RST_SPI2 = _REG_BIT(0x20, 14) , RST_SPI3 = _REG_BIT(0x20, 15) , RST_USART2 = _REG_BIT(0x20, 17) , RST_USART3 = _REG_BIT(0x20, 18) , RST_UART4 = _REG_BIT(0x20, 19) , RST_UART5 = _REG_BIT(0x20, 20) , RST_I2C1 = _REG_BIT(0x20, 21) , RST_I2C2 = _REG_BIT(0x20, 22) , RST_I2C3 = _REG_BIT(0x20, 23) , RST_CAN1 = _REG_BIT(0x20, 25) , RST_CAN2 = _REG_BIT(0x20, 26) , RST_PWR = _REG_BIT(0x20, 28) , RST_DAC = _REG_BIT(0x20, 29) , RST_UART7 = _REG_BIT(0x20, 30) , RST_UART8 = _REG_BIT(0x20, 31) , RST_TIM1 = _REG_BIT(0x24, 0) , RST_TIM8 = _REG_BIT(0x24, 1) , RST_USART1 = _REG_BIT(0x24, 4) , RST_USART6 = _REG_BIT(0x24, 5) , RST_ADC = _REG_BIT(0x24, 8) , RST_SDIO = _REG_BIT(0x24, 11) , RST_SPI1 = _REG_BIT(0x24, 12) , RST_SPI4 = _REG_BIT(0x24, 13) , RST_SYSCFG = _REG_BIT(0x24, 14) , RST_TIM9 = _REG_BIT(0x24, 16) , RST_TIM10 = _REG_BIT(0x24, 17) , RST_TIM11 = _REG_BIT(0x24, 18) , RST_SPI5 = _REG_BIT(0x24, 20) , RST_SPI6 = _REG_BIT(0x24, 21) , RST_SAI1RST = _REG_BIT(0x24, 22) , RST_LTDC = _REG_BIT(0x24, 26) , RST_DSI = _REG_BIT(0x24, 27) , RST_BDCR = _REG_BIT(0x70, 16) }

Functions
void	rcc_osc_ready_int_clear (enum rcc_osc osc)

void	rcc_osc_ready_int_enable (enum rcc_osc osc)

void	rcc_osc_ready_int_disable (enum rcc_osc osc)

int	rcc_osc_ready_int_flag (enum rcc_osc osc)

void	rcc_css_int_clear (void)

int	rcc_css_int_flag (void)

void	rcc_wait_for_sysclk_status (enum rcc_osc osc)

void	rcc_osc_on (enum rcc_osc osc)

void	rcc_osc_off (enum rcc_osc osc)

void	rcc_css_enable (void)

void	rcc_css_disable (void)

void	rcc_plli2s_config (uint16_t n, uint8_t r)
	Set the dividers for the PLLI2S clock outputs. More...

void	rcc_pllsai_config (uint16_t n, uint16_t p, uint16_t q, uint16_t r)
	Set the dividers for the PLLSAI clock outputs divider p is only available on F4x9 parts, pass 0 for other parts. More...

void	rcc_pllsai_postscalers (uint8_t q, uint8_t r)
	Set the dedicated dividers after the PLLSAI configuration. More...

void	rcc_set_sysclk_source (uint32_t clk)

void	rcc_set_pll_source (uint32_t pllsrc)

void	rcc_set_ppre2 (uint32_t ppre2)

void	rcc_set_ppre1 (uint32_t ppre1)

void	rcc_set_hpre (uint32_t hpre)

void	rcc_set_rtcpre (uint32_t rtcpre)

void	rcc_set_main_pll_hsi (uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)
	Reconfigures the main PLL for a HSI source. More...

void	rcc_set_main_pll_hse (uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)
	Reconfigures the main PLL for a HSE source. More...

uint32_t	rcc_system_clock_source (void)

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
	Setup clocks to run from PLL. More...

void	rcc_clock_setup_hse_3v3 (const struct rcc_clock_scale *clock)
	Setup clocks with the HSE. More...

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the USART at base specified. More...

uint32_t	rcc_get_timer_clk_freq (uint32_t timer)
	Get the peripheral clock speed for the Timer at base specified. More...

uint32_t	rcc_get_i2c_clk_freq (uint32_t i2c)
	Get the peripheral clock speed for the I2C device at base specified. More...

uint32_t	rcc_get_spi_clk_freq (uint32_t spi)
	Get the peripheral clock speed for the SPI device at base specified. More...

Variables
uint32_t	rcc_ahb_frequency

uint32_t	rcc_apb1_frequency

uint32_t	rcc_apb2_frequency

const struct rcc_clock_scale	rcc_hsi_configs [RCC_CLOCK_3V3_END]

const struct rcc_clock_scale	rcc_hse_8mhz_3v3 [RCC_CLOCK_3V3_END]

const struct rcc_clock_scale	rcc_hse_12mhz_3v3 [RCC_CLOCK_3V3_END]

const struct rcc_clock_scale	rcc_hse_16mhz_3v3 [RCC_CLOCK_3V3_END]

const struct rcc_clock_scale	rcc_hse_25mhz_3v3 [RCC_CLOCK_3V3_END]

Data Structures

Macros

Enumerations

Functions

Variables