libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
3n/pmc.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_PMC_H
21#define LIBOPENCM3_PMC_H
22
23#include <libopencm3/sam/memorymap.h>
24#include <libopencm3/sam/common/pmc_common_all.h>
25#include <libopencm3/sam/common/pmc_common_3n3u.h>
26
27/* --- Power Management Controller (PMC) registers ----------------------- */
28
29/* PMC Clock Generator PLL Register */
30#define CKGR_PLLR CKGR_PLLAR
31
32/* Oscillator Calibration Register */
33#define PMC_OCR MMIO32(PMC_BASE + 0x0110)
34
35
36/* --- Register contents --------------------------------------------------- */
37
38
39/* --- PMC Clock Generator Main Oscillator Register (CKGR_MOR) ------------- */
40
41/* Wait Mode Command */
42#define CKGR_MOR_WAITMODE (0x01 << 2)
43
44
45/* --- PMC Clock Generator PLL Register (CKGR_PLLR) ---------------------- */
46/* CKGR_PLLAR on all other device subfamilies */
47
48/* must be set to program CKGR_PLLR */
49#define CKGR_PLLR_ONE CKGR_PLLAR_ONE
50
51/* PLLA Multiplier */
52#define CKGR_PLLR_MUL_SHIFT CKGR_PLLAR_MULA_SHIFT
53#define CKGR_PLLR_MUL_MASK CKGR_PLLAR_MULA_MASK
54
55/* PLLA Counter */
56#define CKGR_PLLR_PLLCOUNT_SHIFT CKGR_PLLAR_PLLACOUNT_SHIFT
57#define CKGR_PLLR_PLLCOUNT_MASK CKGR_PLLAR_PLLACOUNT_MASK
58
59/* Divider */
60#define CKGR_PLLR_DIV_SHIFT CKGR_PLLAR_DIVA_SHIFT
61#define CKGR_PLLR_DIV_MASK CKGR_PLLAR_DIVA_MASK
62
63
64/* --- PMC Master Clock Register (PMC_MCKR) -------------------------------- */
65
66/* PLL Divide by 2 */
67#define PMC_MCKR_PLLDIV2 (0x01 << 12)
68
69/* Master Clock Source Selection */
70#define PMC_MCKR_CSS_PLL_CLK (2 << PMC_MCKR_CSS_SHIFT)
71
72
73/* --- PMC Programmable Clock Register 0 (PMC_PCK0) ------------------------ */
74
75/* Master Clock Source Selection */
76#define PMC_PCK0_CSS_PLL_CLK (2 << PMC_PCK0_CSS_SHIFT)
77
78
79/* --- PMC Programmable Clock Register 1 (PMC_PCK1) ------------------------ */
80
81/* Master Clock Source Selection */
82#define PMC_PCK1_CSS_PLL_CLK (2 << PMC_PCK1_CSS_SHIFT)
83
84
85/* --- PMC Programmable Clock Register 2 (PMC_PCK2) ------------------------ */
86
87/* Master Clock Source Selection */
88#define PMC_PCK2_CSS_PLL_CLK (2 << PMC_PCK2_CSS_SHIFT)
89
90
91/* --- PMC Interrupt Enable Register (PMC_IER) ----------------------------- */
92
93/* PLL Lock Interrupt Enable */
94#define PMC_IER_LOCK PMC_IER_LOCKA
95
96
97/* --- PMC Interrupt Disable Register (PMC_IDR) ----------------------------- */
98
99/* PLL Lock Interrupt Disable */
100#define PMC_IDR_LOCK PMC_IDR_LOCKA
101
102
103/* --- PMC Status Register (PMC_SR) ---------------------------------------- */
104
105/* PLL Lock Status */
106#define PMC_SR_LOCK PMC_SR_LOCKA
107
108
109/* --- PMC Interrupt Mask Register (PMC_IMR) ----------------------------- */
110
111/* PLL Lock Interrupt Mask */
112#define PMC_IMR_LOCK PMC_IMR_LOCKA
113
114
115/* --- PMC Oscillator Calibration Register (PMC_OCR) ----------------------- */
116
117/* Selection of RC Oscillator Calibration bits for 12 Mhz */
118#define PMC_OCR_SEL12 (0x01 << 23)
119
120/* RC Oscillator Calibration bits for 12 Mhz */
121#define PMC_OCR_CAL12_SHIFT 16
122#define PMC_OCR_CAL12_MASK (0x7F << PMC_OCR_CAL12_SHIFT)
123
124/* Selection of RC Oscillator Calibration bits for 8 Mhz */
125#define PMC_OCR_SEL8 (0x01 << 15)
126
127/* RC Oscillator Calibration bits for 8 Mhz */
128#define PMC_OCR_CAL8_SHIFT 8
129#define PMC_OCR_CAL8_MASK (0x7F << PMC_OCR_CAL8_SHIFT)
130
131/* Selection of RC Oscillator Calibration bits for 4 Mhz */
132#define PMC_OCR_SEL4 (0x01 << 7)
133
134/* RC Oscillator Calibration bits for 4 Mhz */
135#define PMC_OCR_CAL4_SHIFT 0
136#define PMC_OCR_CAL4_MASK (0x7F << PMC_OCR_CAL12_SHIFT)
137
138
139#endif
pmc_common_3n3u.h
pmc_common_all.h