libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
nrf/common/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
5 * Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
6 *
7 * This library is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU Lesser General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public License
18 * along with this library. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#pragma once
22
23#include <libopencm3/cm3/common.h>
24
25/* Factory Information Configuration Registers */
26#define FICR_BASE (0x10000000U)
27
28/* User Information Configuration Registers */
29#define UICR_BASE (0x10001000U)
30
31#define APB_BASE (0x40000000U)
32#define AHB_BASE (0x50000000U)
33#define PPB_BASE (0xE0000000U)
34
35
36#define CLOCK_BASE (APB_BASE)
37
38/* Power Control */
39#define POWER_BASE (APB_BASE)
40
41/* 2.4 GHz Radio */
42#define RADIO_BASE (APB_BASE + 0x1000)
43
44#define UART0_BASE (APB_BASE + 0x2000)
45
46#define SPI0_BASE (APB_BASE + 0x3000)
47#define TWI0_BASE (APB_BASE + 0x3000)
48#define I2C0_BASE (APB_BASE + 0x3000)
49
50#define SPI1_BASE (APB_BASE + 0x4000)
51#define SPIS1_BASE (APB_BASE + 0x4000)
52#define TWI1_BASE (APB_BASE + 0x4000)
53#define I2C1_BASE (APB_BASE + 0x4000)
54
55#define GPIOTE_BASE (APB_BASE + 0x6000)
56
57#define ADC_BASE (APB_BASE + 0x7000)
58
59#define TIMER0_BASE (APB_BASE + 0x8000)
60#define TIMER1_BASE (APB_BASE + 0x9000)
61#define TIMER2_BASE (APB_BASE + 0xA000)
62
63#define RTC0_BASE (APB_BASE + 0xB000)
64
65#define TEMP_BASE (APB_BASE + 0xC000)
66
67#define RNG_BASE (APB_BASE + 0xD000)
68
69/* AES ECB Mode Encryption */
70#define ECB_BASE (APB_BASE + 0xE000)
71
72/* Accelerated Address Resolver */
73#define AAR_BASE (APB_BASE + 0xF000)
74
75/* AES CCM Mode Encryption */
76#define CCM_BASE (APB_BASE + 0xF000)
77
78#define WDT_BASE (APB_BASE + 0x10000)
79#define RTC1_BASE (APB_BASE + 0x11000)
80#define QDEC_BASE (APB_BASE + 0x12000)
81#define LPCOMP_BASE (APB_BASE + 0x13000)
82#define SWI0_BASE (APB_BASE + 0x14000)
83#define SWI1_BASE (APB_BASE + 0x15000)
84#define SWI2_BASE (APB_BASE + 0x16000)
85#define SWI3_BASE (APB_BASE + 0x17000)
86#define SWI4_BASE (APB_BASE + 0x18000)
87#define SWI5_BASE (APB_BASE + 0x19000)
88
89/* Non-Volatile Memory Controller */
90#define NVMC_BASE (APB_BASE + 0x1E000)
91#define PPI_BASE (APB_BASE + 0x1F000)
92#define RTC2_BASE (APB_BASE + 0x24000)
93
94#define GPIO_BASE (AHB_BASE)
95
96#define NVMC_BASE (APB_BASE + 0x1E000)
97