libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
tsc.h
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1/** @defgroup tsc_defines TSC Defines
2 *
3 * @brief <b>Defined Constants and Types for the STM32F0xx Touch Sensor</b>
4 *
5 * @ingroup STM32F0xx_defines
6 *
7 * @version 1.0.0
8 *
9 * @date 11 July 2013
10 *
11 * LGPL License Terms @ref lgpl_license
12 */
13/*
14 * This file is part of the libopencm3 project.
15 *
16 * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
17 *
18 * This library is free software: you can redistribute it and/or modify
19 * it under the terms of the GNU Lesser General Public License as published by
20 * the Free Software Foundation, either version 3 of the License, or
21 * (at your option) any later version.
22 *
23 * This library is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU Lesser General Public License for more details.
27 *
28 * You should have received a copy of the GNU Lesser General Public License
29 * along with this library. If not, see <http://www.gnu.org/licenses/>.
30 */
31
32#ifndef LIBOPENCM3_TSC_H
33#define LIBOPENCM3_TSC_H
34/**@{*/
35
36/*****************************************************************************/
37/* Module definitions */
38/*****************************************************************************/
39
40#define TSC TSC_BASE
41
42/*****************************************************************************/
43/* Register definitions */
44/*****************************************************************************/
45
46#define TSC_CR MMIO32(TSC_BASE + 0x00)
47#define TSC_IER MMIO32(TSC_BASE + 0x04)
48#define TSC_ICR MMIO32(TSC_BASE + 0x08)
49#define TSC_ISR MMIO32(TSC_BASE + 0x0c)
50#define TSC_IOHCR MMIO32(TSC_BASE + 0x10)
51#define TSC_IOASCR MMIO32(TSC_BASE + 0x18)
52#define TSC_IOSCR MMIO32(TSC_BASE + 0x20)
53#define TSC_IOCCR MMIO32(TSC_BASE + 0x28)
54#define TSC_IOGCSR MMIO32(TSC_BASE + 0x30)
55#define TSC_IOGxCR(x) MMIO32(TSC_BASE + 0x34 + ((x)-1)*4)
56
57/*****************************************************************************/
58/* Register values */
59/*****************************************************************************/
60
61/* TSC_CR Values ------------------------------------------------------------*/
62
63#define TSC_CR_CTPH_SHIFT 28
64#define TSC_CR_CTPH (0xF << TSC_CR_CTPH_SHIFT)
65
66#define TSC_CR_CTPL_SHIFT 24
67#define TSC_CR_CTPL (0x0F << TSC_CR_CTPL_SHIFT)
68
69#define TSC_CR_SSD_SHIFT 17
70#define TSC_CR_SSD (0x7F << TSC_CR_SSD_SHIFT)
71
72#define TSC_CR_SSE (1 << 16)
73#define TSC_CR_SSPSC (1 << 15)
74
75#define TSC_CR_PGPSC_SHIFT 12
76#define TSC_CR_PGPSC (7 << TSC_CR_PGPSC_SHIFT)
77
78#define TSC_CR_MCV_SHIFT 5
79#define TSC_CR_MCV (7 << TSC_CR_MCV_SHIFT)
80
81#define TSC_CR_IODEF (1 << 4)
82#define TSC_CR_SYNCPOL (1 << 3)
83#define TSC_CR_AM (1 << 2)
84#define TSC_CR_START (1 << 1)
85#define TSC_CR_TSCE (1 << 0)
86
87/* TSC_IER Values -----------------------------------------------------------*/
88
89#define TSC_IER_MCEIE (1 << 1)
90#define TSC_IER_EOAIE (1 << 0)
91
92/* TSC_ICR Values -----------------------------------------------------------*/
93
94#define TSC_ICR_MCEIC (1 << 1)
95#define TSC_ICR_EOAIC (1 << 0)
96
97/* TSC_ISR Values -----------------------------------------------------------*/
98
99#define TSC_ISR_MCEF (1 << 1)
100#define TSC_ISR_EOAF (1 << 0)
101
102/* TSC_IOHCR Values ---------------------------------------------------------*/
103
104/* Bit helper g = [1..6] io = [1..4] */
105#define TSC_IOBIT_VAL(g, io) ((1 << ((io)-1)) << (((g)-1)*4))
106
107#define TSC_IOHCR_G1(io) TSC_IOBIT_VAL(1, io)
108#define TSC_IOHCR_G2(io) TSC_IOBIT_VAL(2, io)
109#define TSC_IOHCR_G3(io) TSC_IOBIT_VAL(3, io)
110#define TSC_IOHCR_G4(io) TSC_IOBIT_VAL(4, io)
111#define TSC_IOHCR_G5(io) TSC_IOBIT_VAL(5, io)
112#define TSC_IOHCR_G6(io) TSC_IOBIT_VAL(6, io)
113
114/* TSC_IOASCR Values --------------------------------------------------------*/
115
116#define TSC_IOASCR_G1(io) TSC_IOBIT_VAL(1, io)
117#define TSC_IOASCR_G2(io) TSC_IOBIT_VAL(2, io)
118#define TSC_IOASCR_G3(io) TSC_IOBIT_VAL(3, io)
119#define TSC_IOASCR_G4(io) TSC_IOBIT_VAL(4, io)
120#define TSC_IOASCR_G5(io) TSC_IOBIT_VAL(5, io)
121#define TSC_IOASCR_G6(io) TSC_IOBIT_VAL(6, io)
122
123/* TSC_IOSCR Values ---------------------------------------------------------*/
124
125#define TSC_IOSCR_G1(io) TSC_IOBIT_VAL(1, io)
126#define TSC_IOSCR_G2(io) TSC_IOBIT_VAL(2, io)
127#define TSC_IOSCR_G3(io) TSC_IOBIT_VAL(3, io)
128#define TSC_IOSCR_G4(io) TSC_IOBIT_VAL(4, io)
129#define TSC_IOSCR_G5(io) TSC_IOBIT_VAL(5, io)
130#define TSC_IOSCR_G6(io) TSC_IOBIT_VAL(6, io)
131
132/* TSC_IOCCR Values ---------------------------------------------------------*/
133
134#define TSC_IOCCR_G1(io) TSC_IOBIT_VAL(1, io)
135#define TSC_IOCCR_G2(io) TSC_IOBIT_VAL(2, io)
136#define TSC_IOCCR_G3(io) TSC_IOBIT_VAL(3, io)
137#define TSC_IOCCR_G4(io) TSC_IOBIT_VAL(4, io)
138#define TSC_IOCCR_G5(io) TSC_IOBIT_VAL(5, io)
139#define TSC_IOCCR_G6(io) TSC_IOBIT_VAL(6, io)
140
141/* TSC_IOGCSR Values --------------------------------------------------------*/
142
143#define TSC_IOGCSR_GxE(x) (1 << ((x)-1))
144#define TSC_IOGCSR_GxS(x) (1 << ((x)+15))
145
146/*****************************************************************************/
147/* API definitions */
148/*****************************************************************************/
149
150/*****************************************************************************/
151/* API Functions */
152/*****************************************************************************/
153
154BEGIN_DECLS
155
156END_DECLS
157/**@}*/
158
159#endif
END_DECLS
#define END_DECLS
Definition: common.h:34
BEGIN_DECLS
#define BEGIN_DECLS
Definition: common.h:33