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#define | TIM_SMCR_SMS_OFF (0x0 << 0) |
| Slave mode disabled. More...
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#define | TIM_SMCR_SMS_EM1 (0x1 << 0) |
| Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. More...
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#define | TIM_SMCR_SMS_EM2 (0x2 << 0) |
| Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. More...
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#define | TIM_SMCR_SMS_EM3 (0x3 << 0) |
| Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the complementary input. More...
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#define | TIM_SMCR_SMS_RM (0x4 << 0) |
| Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. More...
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#define | TIM_SMCR_SMS_GM (0x5 << 0) |
| Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. More...
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#define | TIM_SMCR_SMS_TM (0x6 << 0) |
| Trigger Mode - The counter starts at a rising edge of the trigger TRGI. More...
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#define | TIM_SMCR_SMS_ECM1 (0x7 << 0) |
| External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. More...
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#define | TIM_SMCR_SMS_MASK (0x7 << 0) |
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