libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
spi_common_all.c
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1/** @addtogroup spi_file SPI peripheral API
2 * @ingroup peripheral_apis
3
4@author @htmlonly © @endhtmlonly 2009
5Uwe Hermann <uwe@hermann-uwe.de>
6@author @htmlonly &copy; @endhtmlonly 2012
7Ken Sarkies <ksarkies@internode.on.net>
8
9Devices can have up to three SPI peripherals. The common 4-wire full-duplex
10mode of operation is supported, along with 3-wire variants using unidirectional
11communication modes or half-duplex bidirectional communication. A variety of
12options allows many of the SPI variants to be supported. Multimaster operation
13is also supported. A CRC can be generated and checked in hardware.
14
15@note Some JTAG pins need to be remapped if SPI is to be used.
16
17@note The I2S protocol shares the SPI hardware so the two protocols cannot be
18used at the same time on the same peripheral.
19
20Example: Clk/4, positive clock polarity, leading edge trigger, 8-bit words,
21LSB first.
22@code
23 spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_4, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
24 SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_LSBFIRST);
25 spi_write(SPI1, 0x55); // 8-bit write
26 spi_write(SPI1, 0xaa88); // 16-bit write
27 reg8 = spi_read(SPI1); // 8-bit read
28 reg16 = spi_read(SPI1); // 16-bit read
29@endcode
30
31@todo need additional functions to aid ISRs in retrieving status
32
33*/
34
35/*
36 * This file is part of the libopencm3 project.
37 *
38 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
39 *
40 * This library is free software: you can redistribute it and/or modify
41 * it under the terms of the GNU Lesser General Public License as published by
42 * the Free Software Foundation, either version 3 of the License, or
43 * (at your option) any later version.
44 *
45 * This library is distributed in the hope that it will be useful,
46 * but WITHOUT ANY WARRANTY; without even the implied warranty of
47 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
48 * GNU Lesser General Public License for more details.
49 *
50 * You should have received a copy of the GNU Lesser General Public License
51 * along with this library. If not, see <http://www.gnu.org/licenses/>.
52 */
53
56
57/**@{*/
58
59/* TODO: Error handling? */
60/*---------------------------------------------------------------------------*/
61/** @brief SPI Enable.
62
63The SPI peripheral is enabled.
64
65@todo Error handling?
66
67@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
68*/
69
70void spi_enable(uint32_t spi)
71{
72 SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */
73}
74
75/* TODO: Error handling? */
76/*---------------------------------------------------------------------------*/
77/** @brief SPI Disable.
78
79The SPI peripheral is disabled.
80
81@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
82*/
83
84void spi_disable(uint32_t spi)
85{
86 uint32_t reg32;
87
88 reg32 = SPI_CR1(spi);
89 reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */
90 SPI_CR1(spi) = reg32;
91}
92
93/*---------------------------------------------------------------------------*/
94/** @brief SPI Clean Disable.
95
96Disable the SPI peripheral according to the procedure in section 23.3.8 of the
97reference manual. This prevents corruption of any ongoing transfers and
98prevents the BSY flag from becoming unreliable.
99
100@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
101@returns data Unsigned int16. 8 or 16 bit data from final read.
102*/
103
104uint16_t spi_clean_disable(uint32_t spi)
105{
106 /* Wait to receive last data */
107 while (!(SPI_SR(spi) & SPI_SR_RXNE));
108
109 uint16_t data = SPI_DR(spi);
110
111 /* Wait to transmit last data */
112 while (!(SPI_SR(spi) & SPI_SR_TXE));
113
114 /* Wait until not busy */
115 while (SPI_SR(spi) & SPI_SR_BSY);
116
117 SPI_CR1(spi) &= ~SPI_CR1_SPE;
118
119 return data;
120}
121
122/*---------------------------------------------------------------------------*/
123/** @brief SPI Data Write.
124
125Data is written to the SPI interface.
126
127@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
128@param[in] data Unsigned int16. 8 or 16 bit data to be written.
129*/
130
131void spi_write(uint32_t spi, uint16_t data)
132{
133 /* Write data (8 or 16 bits, depending on DFF) into DR. */
134 SPI_DR(spi) = data;
135}
136
137/*---------------------------------------------------------------------------*/
138/** @brief SPI Data Write with Blocking.
139
140Data is written to the SPI interface after the previous write transfer has
141finished.
142
143@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
144@param[in] data Unsigned int16. 8 or 16 bit data to be written.
145*/
146
147void spi_send(uint32_t spi, uint16_t data)
148{
149 /* Wait for transfer finished. */
150 while (!(SPI_SR(spi) & SPI_SR_TXE));
151
152 /* Write data (8 or 16 bits, depending on DFF) into DR. */
153 SPI_DR(spi) = data;
154}
155
156/*---------------------------------------------------------------------------*/
157/** @brief SPI Data Read.
158
159Data is read from the SPI interface after the incoming transfer has finished.
160
161@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
162@returns data Unsigned int16. 8 or 16 bit data.
163*/
164
165uint16_t spi_read(uint32_t spi)
166{
167 /* Wait for transfer finished. */
168 while (!(SPI_SR(spi) & SPI_SR_RXNE));
169
170 /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
171 return SPI_DR(spi);
172}
173
174/*---------------------------------------------------------------------------*/
175/** @brief SPI Data Write and Read Exchange.
176
177Data is written to the SPI interface, then a read is done after the incoming
178transfer has finished.
179
180@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
181@param[in] data Unsigned int16. 8 or 16 bit data to be written.
182@returns data Unsigned int16. 8 or 16 bit data.
183*/
184
185uint16_t spi_xfer(uint32_t spi, uint16_t data)
186{
187 spi_write(spi, data);
188
189 /* Wait for transfer finished. */
190 while (!(SPI_SR(spi) & SPI_SR_RXNE));
191
192 /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
193 return SPI_DR(spi);
194}
195
196/*---------------------------------------------------------------------------*/
197/** @brief SPI Set Bidirectional Simplex Mode.
198
199The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
200(using a clock wire and a bidirectional data wire).
201
202@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
203*/
204
206{
208}
209
210/*---------------------------------------------------------------------------*/
211/** @brief SPI Set Unidirectional Mode.
212
213The SPI peripheral is set for unidirectional transfers. This is used in full
214duplex mode or when the SPI is placed in two-wire simplex mode that uses a
215clock wire and a unidirectional data wire.
216
217@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
218*/
219
221{
222 SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE;
223}
224
225/*---------------------------------------------------------------------------*/
226/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
227
228The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
229(using a clock wire and a bidirectional data wire), and is placed in a receive
230state.
231
232@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
233*/
234
236{
238 SPI_CR1(spi) &= ~SPI_CR1_BIDIOE;
239}
240
241/*---------------------------------------------------------------------------*/
242/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
243
244The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
245(using a clock wire and a bidirectional data wire), and is placed in a transmit
246state.
247
248@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
249*/
250
252{
254 SPI_CR1(spi) |= SPI_CR1_BIDIOE;
255}
256
257/*---------------------------------------------------------------------------*/
258/** @brief SPI Enable the CRC.
259
260The SPI peripheral is set to use a CRC field for transmit and receive.
261
262@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
263*/
264
265void spi_enable_crc(uint32_t spi)
266{
267 SPI_CR1(spi) |= SPI_CR1_CRCEN;
268}
269
270/*---------------------------------------------------------------------------*/
271/** @brief SPI Disable the CRC.
272
273@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
274*/
275
276void spi_disable_crc(uint32_t spi)
277{
278 SPI_CR1(spi) &= ~SPI_CR1_CRCEN;
279}
280
281/*---------------------------------------------------------------------------*/
282/** @brief SPI Next Transmit is a Data Word
283
284The next transmission to take place is a data word from the transmit buffer.
285This must be called before transmission to distinguish between sending
286of a data or CRC word.
287
288@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
289*/
290
292{
293 SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT;
294}
295
296/*---------------------------------------------------------------------------*/
297/** @brief SPI Next Transmit is a CRC Word
298
299The next transmission to take place is a crc word from the hardware crc unit.
300This must be called before transmission to distinguish between sending
301of a data or CRC word.
302
303@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
304*/
305
306void spi_set_next_tx_from_crc(uint32_t spi)
307{
308 SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
309}
310
311/*---------------------------------------------------------------------------*/
312/** @brief SPI Set Full Duplex (3-wire) Mode
313
314@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
315*/
316
317void spi_set_full_duplex_mode(uint32_t spi)
318{
319 SPI_CR1(spi) &= ~SPI_CR1_RXONLY;
320}
321
322/*---------------------------------------------------------------------------*/
323/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional
324Transfers
325
326@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
327*/
328
330{
331 SPI_CR1(spi) |= SPI_CR1_RXONLY;
332}
333
334/*---------------------------------------------------------------------------*/
335/** @brief SPI Disable Slave Management by Hardware
336
337In slave mode the NSS hardware input is used as a select enable for the slave.
338
339@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
340*/
341
343{
344 SPI_CR1(spi) &= ~SPI_CR1_SSM;
345}
346
347/*---------------------------------------------------------------------------*/
348/** @brief SPI Enable Slave Management by Software
349
350In slave mode the NSS hardware input is replaced by an internal software
351enable/disable of the slave (@ref spi_set_nss_high).
352
353@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
354*/
355
357{
358 SPI_CR1(spi) |= SPI_CR1_SSM;
359 /* allow slave select to be an input */
360 SPI_CR2(spi) &= ~SPI_CR2_SSOE;
361}
362
363/*---------------------------------------------------------------------------*/
364/** @brief SPI Set the Software NSS Signal High
365
366In slave mode, and only when software slave management is used, this replaces
367the NSS signal with a slave select enable signal.
368
369@todo these should perhaps be combined with an SSM enable as it is meaningless
370otherwise
371
372@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
373*/
374
375void spi_set_nss_high(uint32_t spi)
376{
377 SPI_CR1(spi) |= SPI_CR1_SSI;
378}
379
380/*---------------------------------------------------------------------------*/
381/** @brief SPI Set the Software NSS Signal Low
382
383In slave mode, and only when software slave management is used, this replaces
384the NSS signal with a slave select disable signal.
385
386@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
387*/
388
389void spi_set_nss_low(uint32_t spi)
390{
391 SPI_CR1(spi) &= ~SPI_CR1_SSI;
392}
393
394/*---------------------------------------------------------------------------*/
395/** @brief SPI Set to Send LSB First
396
397@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
398*/
399
400void spi_send_lsb_first(uint32_t spi)
401{
403}
404
405/*---------------------------------------------------------------------------*/
406/** @brief SPI Set to Send MSB First
407
408@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
409*/
410
411void spi_send_msb_first(uint32_t spi)
412{
413 SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST;
414}
415
416/*---------------------------------------------------------------------------*/
417/** @brief SPI Set the Baudrate Prescaler
418
419@todo Why is this specification different to the spi_init_master baudrate
420values?
421
422@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
423@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre.
424*/
425
426void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate)
427{
428 uint32_t reg32;
429
430 if (baudrate > 7) {
431 return;
432 }
433
434 reg32 = (SPI_CR1(spi) & 0xffc7); /* Clear bits [5:3]. */
435 reg32 |= (baudrate << 3);
436 SPI_CR1(spi) = reg32;
437}
438
439/*---------------------------------------------------------------------------*/
440/** @brief SPI Set to Master Mode
441
442@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
443*/
444
445void spi_set_master_mode(uint32_t spi)
446{
447 SPI_CR1(spi) |= SPI_CR1_MSTR;
448}
449
450/*---------------------------------------------------------------------------*/
451/** @brief SPI Set to Slave Mode
452
453@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
454*/
455
456void spi_set_slave_mode(uint32_t spi)
457{
458 SPI_CR1(spi) &= ~SPI_CR1_MSTR;
459}
460
461/*---------------------------------------------------------------------------*/
462/** @brief SPI Set the Clock Polarity to High when Idle
463
464@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
465@sa spi_set_clock_polarity_0
466*/
467
468void spi_set_clock_polarity_1(uint32_t spi)
469{
470 SPI_CR1(spi) |= SPI_CR1_CPOL;
471}
472
473/*---------------------------------------------------------------------------*/
474/** @brief SPI Set the Clock Polarity to Low when Idle
475
476@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
477@sa spi_set_clock_polarity_1
478*/
479
480void spi_set_clock_polarity_0(uint32_t spi)
481{
482 SPI_CR1(spi) &= ~SPI_CR1_CPOL;
483}
484
485/*---------------------------------------------------------------------------*/
486/** @brief SPI Set the Clock Phase to Capture on Trailing Edge
487
488@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
489@sa spi_set_clock_phase_0
490*/
491
492void spi_set_clock_phase_1(uint32_t spi)
493{
494 SPI_CR1(spi) |= SPI_CR1_CPHA;
495}
496
497/*---------------------------------------------------------------------------*/
498/** @brief SPI Set the Clock Phase to Capture on Leading Edge
499
500@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
501@sa spi_set_clock_phase_1
502*/
503
504void spi_set_clock_phase_0(uint32_t spi)
505{
506 SPI_CR1(spi) &= ~SPI_CR1_CPHA;
507}
508
509/*---------------------------------------------------------------------------*/
510/** @brief SPI Enable the Transmit Buffer Empty Interrupt
511
512@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
513*/
514
516{
517 SPI_CR2(spi) |= SPI_CR2_TXEIE;
518}
519
520/*---------------------------------------------------------------------------*/
521/** @brief SPI Disable the Transmit Buffer Empty Interrupt
522
523@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
524*/
525
527{
528 SPI_CR2(spi) &= ~SPI_CR2_TXEIE;
529}
530
531/*---------------------------------------------------------------------------*/
532/** @brief SPI Enable the Receive Buffer Ready Interrupt
533
534@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
535*/
536
538{
539 SPI_CR2(spi) |= SPI_CR2_RXNEIE;
540}
541
542/*---------------------------------------------------------------------------*/
543/** @brief SPI Disable the Receive Buffer Ready Interrupt
544
545@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
546*/
547
549{
550 SPI_CR2(spi) &= ~SPI_CR2_RXNEIE;
551}
552
553/*---------------------------------------------------------------------------*/
554/** @brief SPI Enable the Error Interrupt
555
556@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
557*/
558
560{
561 SPI_CR2(spi) |= SPI_CR2_ERRIE;
562}
563
564/*---------------------------------------------------------------------------*/
565/** @brief SPI Disable the Error Interrupt
566
567@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
568*/
569
571{
572 SPI_CR2(spi) &= ~SPI_CR2_ERRIE;
573}
574
575/*---------------------------------------------------------------------------*/
576/** @brief SPI Set the NSS Pin as an Output
577
578Normally used in master mode to allows the master to place all devices on the
579SPI bus into slave mode. Multimaster mode is not possible.
580
581@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
582*/
583
584void spi_enable_ss_output(uint32_t spi)
585{
586 SPI_CR2(spi) |= SPI_CR2_SSOE;
587}
588
589/*---------------------------------------------------------------------------*/
590/** @brief SPI Set the NSS Pin as an Input
591
592In master mode this allows the master to sense the presence of other masters. If
593NSS is then pulled low the master is placed into slave mode. In slave mode NSS
594becomes a slave enable.
595
596@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
597*/
598
599void spi_disable_ss_output(uint32_t spi)
600{
601 SPI_CR2(spi) &= ~SPI_CR2_SSOE;
602}
603
604/*---------------------------------------------------------------------------*/
605/** @brief SPI Enable Transmit Transfers via DMA
606
607This allows transmissions to proceed unattended using DMA to move data to the
608transmit buffer as it becomes available. The DMA channels provided for each
609SPI peripheral are given in the Technical Manual DMA section.
610
611@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
612*/
613
614void spi_enable_tx_dma(uint32_t spi)
615{
616 SPI_CR2(spi) |= SPI_CR2_TXDMAEN;
617}
618
619/*---------------------------------------------------------------------------*/
620/** @brief SPI Disable Transmit Transfers via DMA
621
622@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
623*/
624
625void spi_disable_tx_dma(uint32_t spi)
626{
627 SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN;
628}
629
630/*---------------------------------------------------------------------------*/
631/** @brief SPI Enable Receive Transfers via DMA
632
633This allows received data streams to proceed unattended using DMA to move data
634from the receive buffer as data becomes available. The DMA channels provided
635for each SPI peripheral are given in the Technical Manual DMA section.
636
637@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
638*/
639
640void spi_enable_rx_dma(uint32_t spi)
641{
642 SPI_CR2(spi) |= SPI_CR2_RXDMAEN;
643}
644
645/*---------------------------------------------------------------------------*/
646/** @brief SPI Disable Receive Transfers via DMA
647
648@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
649*/
650
651void spi_disable_rx_dma(uint32_t spi)
652{
653 SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN;
654}
655
656/*---------------------------------------------------------------------------*/
657/** @brief SPI Standard Mode selection
658@details Set SPI standard Modes
659Mode | CPOL | CPHA
660---- | ---- | ----
661 0 | 0 | 0
662 1 | 0 | 1
663 2 | 1 | 0
664 3 | 1 | 1
665@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
666@param[in] mode Unsigned int8. Standard SPI mode (0, 1, 2, 3)
667@sa spi_set_clock_phase_0 spi_set_clock_phase_1
668@sa spi_set_clock_polarity_0 spi_set_clock_polarity_1
669*/
670
671void spi_set_standard_mode(uint32_t spi, uint8_t mode)
672{
673 if (mode > 3) {
674 return;
675 }
676
677 uint32_t reg32 = SPI_CR1(spi) & ~(SPI_CR1_CPOL | SPI_CR1_CPHA);
678 SPI_CR1(spi) = reg32 | mode;
679}
680
681/**@}*/
#define SPI_CR1_SSM
#define SPI_CR2_TXEIE
#define SPI_CR1_CPOL
#define SPI_CR1_BIDIOE
#define SPI_CR2_TXDMAEN
#define SPI_SR_RXNE
#define SPI_CR1_BIDIMODE
#define SPI_CR1_CRCNEXT
#define SPI_CR1(spi_base)
#define SPI_CR1_MSTR
#define SPI_SR_TXE
#define SPI_CR2(spi_base)
#define SPI_CR1_SSI
#define SPI_CR1_CPHA
#define SPI_DR(spi_base)
#define SPI_CR1_RXONLY
#define SPI_SR_BSY
#define SPI_CR2_RXNEIE
#define SPI_CR1_SPE
#define SPI_CR1_CRCEN
#define SPI_SR(spi_base)
#define SPI_CR2_SSOE
#define SPI_CR2_ERRIE
#define SPI_CR2_RXDMAEN
void spi_disable_rx_dma(uint32_t spi)
SPI Disable Receive Transfers via DMA.
void spi_set_next_tx_from_buffer(uint32_t spi)
SPI Next Transmit is a Data Word.
void spi_disable_crc(uint32_t spi)
SPI Disable the CRC.
uint16_t spi_read(uint32_t spi)
SPI Data Read.
void spi_send(uint32_t spi, uint16_t data)
SPI Data Write with Blocking.
void spi_set_unidirectional_mode(uint32_t spi)
SPI Set Unidirectional Mode.
void spi_enable(uint32_t spi)
SPI Enable.
void spi_set_clock_polarity_1(uint32_t spi)
SPI Set the Clock Polarity to High when Idle.
void spi_enable_crc(uint32_t spi)
SPI Enable the CRC.
void spi_disable(uint32_t spi)
SPI Disable.
void spi_set_nss_low(uint32_t spi)
SPI Set the Software NSS Signal Low.
void spi_enable_tx_buffer_empty_interrupt(uint32_t spi)
SPI Enable the Transmit Buffer Empty Interrupt.
void spi_disable_software_slave_management(uint32_t spi)
SPI Disable Slave Management by Hardware.
void spi_set_clock_polarity_0(uint32_t spi)
SPI Set the Clock Polarity to Low when Idle.
void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate)
SPI Set the Baudrate Prescaler.
void spi_write(uint32_t spi, uint16_t data)
SPI Data Write.
void spi_set_full_duplex_mode(uint32_t spi)
SPI Set Full Duplex (3-wire) Mode.
void spi_enable_tx_dma(uint32_t spi)
SPI Enable Transmit Transfers via DMA.
void spi_set_bidirectional_transmit_only_mode(uint32_t spi)
SPI Set Bidirectional Simplex Receive Only Mode.
void spi_disable_ss_output(uint32_t spi)
SPI Set the NSS Pin as an Input.
void spi_send_lsb_first(uint32_t spi)
SPI Set to Send LSB First.
void spi_disable_error_interrupt(uint32_t spi)
SPI Disable the Error Interrupt.
void spi_set_next_tx_from_crc(uint32_t spi)
SPI Next Transmit is a CRC Word.
void spi_set_receive_only_mode(uint32_t spi)
SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers.
void spi_enable_software_slave_management(uint32_t spi)
SPI Enable Slave Management by Software.
void spi_set_clock_phase_0(uint32_t spi)
SPI Set the Clock Phase to Capture on Leading Edge.
void spi_disable_tx_buffer_empty_interrupt(uint32_t spi)
SPI Disable the Transmit Buffer Empty Interrupt.
void spi_enable_rx_dma(uint32_t spi)
SPI Enable Receive Transfers via DMA.
void spi_set_clock_phase_1(uint32_t spi)
SPI Set the Clock Phase to Capture on Trailing Edge.
void spi_set_standard_mode(uint32_t spi, uint8_t mode)
SPI Standard Mode selection.
void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi)
SPI Enable the Receive Buffer Ready Interrupt.
void spi_set_nss_high(uint32_t spi)
SPI Set the Software NSS Signal High.
void spi_enable_ss_output(uint32_t spi)
SPI Set the NSS Pin as an Output.
void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi)
SPI Disable the Receive Buffer Ready Interrupt.
void spi_send_msb_first(uint32_t spi)
SPI Set to Send MSB First.
uint16_t spi_xfer(uint32_t spi, uint16_t data)
SPI Data Write and Read Exchange.
void spi_set_slave_mode(uint32_t spi)
SPI Set to Slave Mode.
void spi_enable_error_interrupt(uint32_t spi)
SPI Enable the Error Interrupt.
void spi_set_bidirectional_mode(uint32_t spi)
SPI Set Bidirectional Simplex Mode.
void spi_set_bidirectional_receive_only_mode(uint32_t spi)
SPI Set Bidirectional Simplex Receive Only Mode.
uint16_t spi_clean_disable(uint32_t spi)
SPI Clean Disable.
void spi_disable_tx_dma(uint32_t spi)
SPI Disable Transmit Transfers via DMA.
void spi_set_master_mode(uint32_t spi)
SPI Set to Master Mode.
#define SPI_CR1_LSBFIRST