libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
uart.h
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1/** @defgroup VF6xx_uart_defines UART Defines
2 *
3 * @brief <b>Defined Constants and Types for the VF6xx UART Module</b>
4 *
5 * @ingroup VF6xx_defines
6 *
7 * @version 1.0.0
8 *
9 * @author @htmlonly &copy; @endhtmlonly 2014
10 * Stefan Agner <stefan@agner.ch>
11 *
12 * @date 01 July 2014
13 *
14 * LGPL License Terms @ref lgpl_license
15 * */
16/*
17 * This file is part of the libopencm3 project.
18 *
19 * Copyright (C) 2014 Stefan Agner <stefan@agner.ch>
20 *
21 * This library is free software: you can redistribute it and/or modify
22 * it under the terms of the GNU Lesser General Public License as published by
23 * the Free Software Foundation, either version 3 of the License, or
24 * (at your option) any later version.
25 *
26 * This library is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU Lesser General Public License for more details.
30 *
31 * You should have received a copy of the GNU Lesser General Public License
32 * along with this library. If not, see <http://www.gnu.org/licenses/>.
33 */
34
35#ifndef LIBOPENCM3_VF6XX_UART_H
36#define LIBOPENCM3_VF6XX_UART_H
37
38#include <libopencm3/cm3/common.h>
39#include <libopencm3/vf6xx/memorymap.h>
40
41/* --- Convenience macros -------------------------------------------------- */
42
43/****************************************************************************/
44/** @defgroup uart_reg_base UART register base addresses
45@ingroup VF6xx_uart_defines
46
47@{*/
48#define UART0 UART0_BASE
49#define UART1 UART1_BASE
50#define UART2 UART2_BASE
51#define UART3 UART3_BASE
52#define UART4 UART4_BASE
53#define UART5 UART5_BASE
54
55/* --- UART registers ------------------------------------------------------ */
56
57#define UART_BDH(uart_base) MMIO8((uart_base) + 0x00)
58#define UART_BDL(uart_base) MMIO8((uart_base) + 0x01)
59#define UART_C1(uart_base) MMIO8((uart_base) + 0x02)
60#define UART_C2(uart_base) MMIO8((uart_base) + 0x03)
61#define UART_S1(uart_base) MMIO8((uart_base) + 0x04)
62#define UART_S2(uart_base) MMIO8((uart_base) + 0x05)
63#define UART_C3(uart_base) MMIO8((uart_base) + 0x06)
64#define UART_D(uart_base) MMIO8((uart_base) + 0x07)
65#define UART_MA1(uart_base) MMIO8((uart_base) + 0x08)
66#define UART_MA2(uart_base) MMIO8((uart_base) + 0x09)
67#define UART_C4(uart_base) MMIO8((uart_base) + 0x0A)
68#define UART_C5(uart_base) MMIO8((uart_base) + 0x0B)
69#define UART_ED(uart_base) MMIO8((uart_base) + 0x0C)
70#define UART_MODEM(uart_base) MMIO8((uart_base) + 0x0D)
71/* Incomplete */
72
73/* --- CCM values -....----------------------------------------------------- */
74
75/* BDH: Baud Rate Register High */
76#define UART_BDH_LBKDIE (1 << 7)
77#define UART_BDH_RXEDGIE (1 << 6)
78#define UART_BDH_SBR_MASK 0x1f
79
80/* BDL: Baud Rate Register Low */
81#define UART_BDL_SBR_MASK 0xff
82
83/* C1: Control register 1 */
84#define UART_C1_LOOPS (1 << 7)
85#define UART_C1_RSRC (1 << 5)
86#define UART_C1_M (1 << 4)
87#define UART_C1_WAKE (1 << 3)
88#define UART_C1_ILT (1 << 2)
89#define UART_C1_PE (1 << 1)
90#define UART_C1_PT (1 << 0)
91
92/* C2: Control register 2 */
93#define UART_C2_TIE (1 << 7)
94#define UART_C2_TCIE (1 << 6)
95#define UART_C2_RIE (1 << 5)
96#define UART_C2_ILIE (1 << 4)
97#define UART_C2_TE (1 << 3)
98#define UART_C2_RE (1 << 2)
99#define UART_C2_RWU (1 << 1)
100#define UART_C2_SBK (1 << 0)
101
102/* S1: Status register 1 */
103#define UART_S1_TDRE (1 << 7)
104#define UART_S1_TC (1 << 6)
105#define UART_S1_RDRF (1 << 5)
106#define UART_S1_IDLE (1 << 4)
107#define UART_S1_OR (1 << 3)
108#define UART_S1_NF (1 << 2)
109#define UART_S1_FE (1 << 1)
110#define UART_S1_PF (1 << 0)
111
112/* S2: Status register 2 */
113#define UART_S2_LBKDIF (1 << 7)
114#define UART_S2_RXEDGIF (1 << 6)
115#define UART_S2_MSBF (1 << 5)
116#define UART_S2_RXINV (1 << 4)
117#define UART_S2_RWUID (1 << 3)
118#define UART_S2_BRK13 (1 << 2)
119#define UART_S2_LBKDE (1 << 1)
120#define UART_S2_RAF (1 << 0)
121
122/* C3: Control register 3 */
123#define UART_C3_R8 (1 << 7)
124#define UART_C3_T8 (1 << 6)
125#define UART_C3_TXDIR (1 << 5)
126#define UART_C3_TXINV (1 << 4)
127#define UART_C3_ORIE (1 << 3)
128#define UART_C3_NEIE (1 << 2)
129#define UART_C3_FEIE (1 << 1)
130#define UART_C3_PEIE (1 << 0)
131
132/* MODEM: Modem configuration register */
133#define UART_MODEM_RXRTSE (1 << 3)
134#define UART_MODEM_TXRTSPOL (1 << 2)
135#define UART_MODEM_TXRTSE (1 << 1)
136#define UART_MODEM_TXCTSE (1 << 0)
137
138/****************************************************************************/
139/** @defgroup uart_parity UART Parity Selection
140@ingroup VF6xx_uart_defines
141
142@{*/
143#define UART_PARITY_NONE 0x00
144#define UART_PARITY_EVEN UART_C1_PE
145#define UART_PARITY_ODD (UART_C1_PE | UART_C1_PT)
146/**@}*/
147#define UART_PARITY_MASK 0x3
148
149/* CR3_CTSE/CR3_RTSE combined values */
150/****************************************************************************/
151/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
152@ingroup STM32F_usart_defines
153
154@{*/
155#define UART_FLOWCONTROL_NONE 0x00
156#define UART_FLOWCONTROL_RTS UART_MODEM_RXRTSE
157#define UART_FLOWCONTROL_CTS UART_MODEM_TXCTSE
158#define UART_FLOWCONTROL_RTS_CTS (UART_MODEM_RXRTSE | UART_MODEM_TXCTSE)
159/**@}*/
160#define UART_FLOWCONTROL_MASK (UART_MODEM_RXRTSE | UART_MODEM_TXCTSE)
161
162/* --- Function prototypes ------------------------------------------------- */
163
164#include <libopencm3/cm3/common.h>
165
166BEGIN_DECLS
167
168void uart_enable(uint32_t uart);
169void uart_disable(uint32_t uart);
170void uart_set_baudrate(uint32_t uart, uint32_t baud);
171void uart_set_parity(uint32_t uart, uint8_t parity);
172void uart_set_flow_control(uint32_t uart, uint8_t flowcontrol);
173void uart_send(uint32_t uart, uint8_t data);
174void uart_send_blocking(uint32_t usart, uint8_t data);
175void uart_wait_send_ready(uint32_t uart);
176uint8_t uart_recv(uint32_t uart);
177uint8_t uart_recv_blocking(uint32_t uart);
178void uart_wait_recv_ready(uint32_t uart);
179
180END_DECLS
181
182#endif
END_DECLS
#define END_DECLS
Definition: common.h:34
BEGIN_DECLS
#define BEGIN_DECLS
Definition: common.h:33
uart_disable
void uart_disable(uint32_t uart)
UART Disable.
Definition: uart.c:127
uart_set_baudrate
void uart_set_baudrate(uint32_t uart, uint32_t baud)
UART Set Baudrate.
Definition: uart.c:53
uart_send
void uart_send(uint32_t uart, uint8_t data)
UART Send a Data Word.
Definition: uart.c:140
uart_wait_recv_ready
void uart_wait_recv_ready(uint32_t uart)
UART Wait for Received Data Available.
Definition: uart.c:200
uart_send_blocking
void uart_send_blocking(uint32_t usart, uint8_t data)
UART Send Data byte blocking.
Definition: uart.c:171
uart_recv
uint8_t uart_recv(uint32_t uart)
UART Read a Received Data Word.
Definition: uart.c:185
uart_set_parity
void uart_set_parity(uint32_t uart, uint8_t parity)
UART Set Parity.
Definition: uart.c:76
uart_wait_send_ready
void uart_wait_send_ready(uint32_t uart)
UART Wait for Transmit Data Buffer Empty.
Definition: uart.c:155
uart_enable
void uart_enable(uint32_t uart)
UART Enable.
Definition: uart.c:113
uart_recv_blocking
uint8_t uart_recv_blocking(uint32_t uart)
UART Read a Received Data Word with Blocking.
Definition: uart.c:217
uart_set_flow_control
void uart_set_flow_control(uint32_t uart, uint8_t flowcontrol)
UART Set Hardware Flow Control.
Definition: uart.c:95