libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
rcc.c
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1/** @defgroup rcc_file RCC Controller
2
3@brief <b>LM3S RCC Controller</b>
4
5@ingroup LM3Sxx
6
7@version 1.0.0
8
9@author @htmlonly &copy; @endhtmlonly 2015
10Daniele Lacamera <root at danielinux dot net>
11
12@date 21 November 2015
13
14LGPL License Terms @ref lgpl_license
15*/
16/*
17 * This file is part of the libopencm3 project.
18 *
19 * Copyright (C) 2015 Daniele Lacamera <root@danielinux.net>
20 *
21 * This library is free software: you can redistribute it and/or modify
22 * it under the terms of the GNU Lesser General Public License as published by
23 * the Free Software Foundation, either version 3 of the License, or
24 * (at your option) any later version.
25 *
26 * This library is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU Lesser General Public License for more details.
30 *
31 * You should have received a copy of the GNU Lesser General Public License
32 * along with this library. If not, see <http://www.gnu.org/licenses/>.
33 */
34
35#include <stdint.h>
36#include <libopencm3/lm3s/rcc.h>
37#include <libopencm3/cm3/sync.h>
38
40{
41 uint32_t rcc = RCC_RESET_VALUE;
42 uint32_t rcc2 = RCC2_RESET_VALUE;
43
44 /* Stage 0: Reset values applied */
45 RCC_CR = rcc;
46 RCC2_CR = rcc2;
47 __dmb();
48
49 /* Stage 1: Reset Oscillators and select configured values */
51 RCC2_CR = (4 - 1) << RCC2_SYSDIV2_SHIFT;
52 __dmb();
53
54 /* Stage 2: Power on oscillators */
55 rcc &= ~RCC_OFF;
56 rcc2 &= ~RCC2_OFF;
57 RCC_CR = rcc;
58 RCC2_CR = rcc2;
59 __dmb();
60
61 /* Stage 3: Set USESYSDIV */
63 RCC_CR = rcc;
64 __dmb();
65
66 /* Stage 4: Wait for PLL raw interrupt */
67 while ((RCC_RIS & RIS_PLLLRIS) == 0)
68 ;
69
70 /* Stage 5: Disable bypass */
71 rcc &= ~RCC_BYPASS;
72 rcc2 &= ~RCC2_BYPASS;
73 RCC_CR = rcc;
74 RCC2_CR = rcc2;
75 __dmb();
76 return 0;
77}
int rcc_clock_setup_in_xtal_8mhz_out_50mhz(void)
Definition: rcc.c:39
#define RCC2_SYSDIV2_SHIFT
Definition: rcc.h:78
#define RIS_PLLLRIS
Definition: rcc.h:84
#define RCC2_RESET_VALUE
Definition: rcc.h:99
#define RCC_CR
Definition: rcc.h:43
#define RCC_RESET_VALUE
Definition: rcc.h:94
#define RCC_RIS
Definition: rcc.h:42
#define RCC_USESYSDIV
Definition: rcc.h:51
#define RCC2_CR
Definition: rcc.h:44
#define RCC_XTAL_8MHZ_400MHZ
Definition: rcc.h:63
#define RCC_BYPASS
Definition: rcc.h:58
#define RCC_USEPWMDIV
Definition: rcc.h:52
#define RCC_SYSDIV_50MHZ
Definition: rcc.h:49
#define RCC_PWMDIV_64
Definition: rcc.h:55
void __dmb(void)
Definition: sync.c:23