Defined Constants and Types for the STM32F1xx Independent Watchdog Timer
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Defined Constants and Types for the STM32F1xx Independent Watchdog Timer
- Version
- 1.0.0
- Date
- 18 August 2012
LGPL License Terms libopencm3 License
- Author
- © 2010 Thomas Otto tommi.nosp@m.@via.nosp@m.dmin..nosp@m.org
◆ IWDG_KR
◆ IWDG_PR
◆ IWDG_PR_LSB
◆ IWDG_RLR
◆ IWDG_SR
◆ iwdg_prescaler_busy()
bool iwdg_prescaler_busy |
( |
void |
| ) |
|
◆ iwdg_reload_busy()
bool iwdg_reload_busy |
( |
void |
| ) |
|
◆ iwdg_reset()
◆ iwdg_set_period_ms()
void iwdg_set_period_ms |
( |
uint32_t |
period | ) |
|
IWDG Set Period in Milliseconds.
The countdown period is converted into count and prescale values. The maximum period is 32.76 seconds; values above this are truncated. Periods less than 1ms are not supported by this library.
A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds) can occasionally occur if the prescale or preload registers are currently busy loading a previous value.
- Parameters
-
[in] | period | uint32_t Period in milliseconds (< 32760) from a watchdog reset until a system reset is issued. |
Definition at line 73 of file iwdg_common_all.c.
References COUNT_LENGTH, COUNT_MASK, IWDG_KR, IWDG_KR_UNLOCK, IWDG_PR, iwdg_prescaler_busy(), iwdg_reload_busy(), iwdg_reset(), and IWDG_RLR.
◆ iwdg_start()
IWDG Enable Watchdog Timer.
The watchdog timer is started. The timeout period defaults to 512 milliseconds unless it has been previously defined.
Definition at line 54 of file iwdg_common_all.c.
References IWDG_KR, and IWDG_KR_START.