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#define | OPAMP_TCMR(opamp_base) MMIO32((opamp_base) + 0x18) |
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#define | OPAMP_CSR_CALOUT_MASK (0x1) |
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#define | OPAMP_CSR_CALOUT_SHIFT (30) |
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#define | OPAMP_CSR_CALOUT_UNSUCC (0x0) |
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#define | OPAMP_CSR_CALOUT_SUCC (0x1) |
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#define | OPAMP_CSR_PGA_GAIN_MASK (0x1f) |
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#define | OPAMP_CSR_PGA_GAIN_SHIFT (14) |
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#define | OPAMP_CSR_PGA_GAIN_2 (0x00) |
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#define | OPAMP_CSR_PGA_GAIN_4 (0x01) |
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#define | OPAMP_CSR_PGA_GAIN_8 (0x02) |
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#define | OPAMP_CSR_PGA_GAIN_16 (0x03) |
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#define | OPAMP_CSR_PGA_GAIN_32 (0x04) |
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#define | OPAMP_CSR_PGA_GAIN_64 (0x05) |
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#define | OPAMP_CSR_PGA_INV_GAIN_MINUS_1_GAIN_2_VM0 (0x08) |
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#define | OPAMP_CSR_PGA_INV_GAIN_MINUS_3_GAIN_4_VM0 (0x09) |
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#define | OPAMP_CSR_PGA_INV_GAIN_MINUS_7_GAIN_8_VM0 (0x0A) |
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#define | OPAMP_CSR_PGA_INV_GAIN_MINUS_15_GAIN_16_VM0 (0x0B) |
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#define | OPAMP_CSR_PGA_INV_GAIN_MINUS_31_GAIN_32_VM0 (0x0C) |
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#define | OPAMP_CSR_PGA_INV_GAIN_MINUS_63_GAIN_64_VM0 (0x0D) |
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#define | OPAMP_CSR_PGA_FILT_VM0_GAIN_2 (0x10) |
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#define | OPAMP_CSR_PGA_FILT_VM0_GAIN_4 (0x11) |
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#define | OPAMP_CSR_PGA_FILT_VM0_GAIN_8 (0x12) |
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#define | OPAMP_CSR_PGA_FILT_VM0_GAIN_16 (0x13) |
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#define | OPAMP_CSR_PGA_FILT_VM0_GAIN_32 (0x14) |
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#define | OPAMP_CSR_PGA_FILT_VM0_GAIN_64 (0x15) |
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#define | OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_1_GAIN_2_VM0 (0x18) |
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#define | OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_3_GAIN_4_VM0 (0x19) |
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#define | OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_7_GAIN_8_VM0 (0x1a) |
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#define | OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_15_GAIN_16_VM0 (0x1B) |
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#define | OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_31_GAIN_32_VM0 (0x1c) |
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#define | OPAMP_CSR_PGA_FILT_VM1_INV_GAIN_MINUS_63_GAIN_64_VM0 (0x1d) |
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#define | OPAMP_CSR_OPAINTOEN (0x1 << 8) |
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#define | OPAMP_CSR_OPAHSM (0x1 << 7) |
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#define | OPAMP_CSR_VM_SEL_VINM0_IN (0x0) |
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#define | OPAMP_CSR_VM_SEL_VINM1_IN (0x1) |
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#define | OPAMP_CSR_VM_SEL_PGA_MODE (0x2) |
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#define | OPAMP_CSR_VM_SEL_OUT_IN (0x3) |
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#define | OPAMP_CSR_USER_TRIM (0x1 << 4) |
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#define | OPAMP_CSR_VP_SEL_VINP0 (0x0) |
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#define | OPAMP_CSR_VP_SEL_VINP1 (0x1) |
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#define | OPAMP_CSR_VP_SEL_VINP2 (0x2) |
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