PWR Registers

Collaboration diagram for PWR Registers:

Macros
#define	PWR_CR1   MMIO32(POWER_CONTROL_BASE + 0x00)
	Power control register. More...
#define	PWR_CSR1   MMIO32(POWER_CONTROL_BASE + 0x04)
	Power control/status register. More...
#define	PWR_CR2   MMIO32(POWER_CONTROL_BASE + 0x08)
	Power control register 2. More...
#define	PWR_CR3   MMIO32(POWER_CONTROL_BASE + 0x0C)
	Power control register 3. More...
#define	PWR_CPUCR   MMIO32(POWER_CONTROL_BASE + 0x10)
	CPU Power control register 3. More...
#define	PWR_D3CR   MMIO32(POWER_CONTROL_BASE + 0x18)
	D3 Domain Power Control register. More...
#define	PWR_SRDCR   MMIO32(POWER_CONTROL_BASE + 0x18)
#define	PWR_WKUPCR   MMIO32(POWER_CONTROL_BASE + 0x20)
	Wakeup Domain Power Control register. More...

Detailed Description

Macro Definition Documentation

PWR_CPUCR

#define PWR_CPUCR   MMIO32(POWER_CONTROL_BASE + 0x10)

CPU Power control register 3.

Definition at line 48 of file h7/pwr.h.

PWR_CR1

#define PWR_CR1   MMIO32(POWER_CONTROL_BASE + 0x00)

Power control register.

Definition at line 36 of file h7/pwr.h.

PWR_CR2

#define PWR_CR2   MMIO32(POWER_CONTROL_BASE + 0x08)

Power control register 2.

Definition at line 42 of file h7/pwr.h.

PWR_CR3

#define PWR_CR3   MMIO32(POWER_CONTROL_BASE + 0x0C)

Power control register 3.

Definition at line 45 of file h7/pwr.h.

PWR_CSR1

#define PWR_CSR1   MMIO32(POWER_CONTROL_BASE + 0x04)

Power control/status register.

Definition at line 39 of file h7/pwr.h.

PWR_D3CR

#define PWR_D3CR   MMIO32(POWER_CONTROL_BASE + 0x18)

D3 Domain Power Control register.

Note: Referred to as PWR_SRDCR (SmartRun Domain Control) on LP devices. The VOS bitfield differs between the two implementations (unfortunately).

Definition at line 54 of file h7/pwr.h.

PWR_SRDCR

#define PWR_SRDCR   MMIO32(POWER_CONTROL_BASE + 0x18)

Definition at line 55 of file h7/pwr.h.

PWR_WKUPCR

#define PWR_WKUPCR   MMIO32(POWER_CONTROL_BASE + 0x20)

Wakeup Domain Power Control register.

Definition at line 58 of file h7/pwr.h.