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| #define | ANADIG_PLL3_CTRL MMIO32(ANADIG_BASE + 0x010) |
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| #define | ANADIG_PLL7_CTRL MMIO32(ANADIG_BASE + 0x020) |
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| #define | ANADIG_PLL2_CTRL MMIO32(ANADIG_BASE + 0x030) |
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| #define | ANADIG_PLL2_SS MMIO32(ANADIG_BASE + 0x040) |
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| #define | ANADIG_PLL2_NUM MMIO32(ANADIG_BASE + 0x050) |
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| #define | ANADIG_PLL2_DENOM MMIO32(ANADIG_BASE + 0x060) |
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| #define | ANADIG_PLL4_CTRL MMIO32(ANADIG_BASE + 0x070) |
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| #define | ANADIG_PLL4_NUM MMIO32(ANADIG_BASE + 0x080) |
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| #define | ANADIG_PLL4_DENOM MMIO32(ANADIG_BASE + 0x090) |
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| #define | ANADIG_PLL6_CTRL MMIO32(ANADIG_BASE + 0x0A0) |
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| #define | ANADIG_PLL6_NUM MMIO32(ANADIG_BASE + 0x0B0) |
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| #define | ANADIG_PLL6_DENOM MMIO32(ANADIG_BASE + 0x0C0) |
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| #define | ANADIG_PLL5_CTRL MMIO32(ANADIG_BASE + 0x0E0) |
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| #define | ANADIG_PLL3_PFD MMIO32(ANADIG_BASE + 0x0F0) |
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| #define | ANADIG_PLL2_PFD MMIO32(ANADIG_BASE + 0x100) |
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| #define | ANADIG_REG_1P1 MMIO32(ANADIG_BASE + 0x110) |
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| #define | ANADIG_REG_3P0 MMIO32(ANADIG_BASE + 0x120) |
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| #define | ANADIG_REG_2P5 MMIO32(ANADIG_BASE + 0x130) |
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| #define | ANADIG_ANA_MISC0 MMIO32(ANADIG_BASE + 0x150) |
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| #define | ANADIG_ANA_MISC1 MMIO32(ANADIG_BASE + 0x160) |
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| #define | ANADIG_ANADIG_DIGPROG MMIO32(ANADIG_BASE + 0x260) |
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| #define | ANADIG_PLL1_CTRL MMIO32(ANADIG_BASE + 0x270) |
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| #define | ANADIG_PLL1_SS MMIO32(ANADIG_BASE + 0x280) |
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| #define | ANADIG_PLL1_NUM MMIO32(ANADIG_BASE + 0x290) |
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| #define | ANADIG_PLL1_DENOM MMIO32(ANADIG_BASE + 0x2A0) |
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| #define | ANADIG_PLL1_PFD MMIO32(ANADIG_BASE + 0x2B0) |
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| #define | ANADIG_PLL_LOCK MMIO32(ANADIG_BASE + 0x2C0) |
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| #define | ANADIG_PLL3_CTRL_LOCK (1 << 31) |
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| #define | ANADIG_PLL3_CTRL_BYPASS (1 << 16) |
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| #define | ANADIG_PLL3_CTRL_BYPASS_CLK_SRC (1 << 14) |
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| #define | ANADIG_PLL3_CTRL_ENABLE (1 << 13) |
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| #define | ANADIG_PLL3_CTRL_POWER (1 << 12) |
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| #define | ANADIG_PLL3_CTRL_EN_USB_CLKS (1 << 6) |
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| #define | ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) |
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| #define | ANADIG_PLL7_CTRL_LOCK (1 << 31) |
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| #define | ANADIG_PLL7_CTRL_BYPASS (1 << 16) |
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| #define | ANADIG_PLL7_CTRL_BYPASS_CLK_SRC (1 << 14) |
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| #define | ANADIG_PLL7_CTRL_ENABLE (1 << 13) |
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| #define | ANADIG_PLL7_CTRL_POWER (1 << 12) |
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| #define | ANADIG_PLL7_CTRL_EN_USB_CLKS (1 << 6) |
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| #define | ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) |
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| #define | ANADIG_PLL2_CTRL_LOCK (1 << 31) |
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| #define | ANADIG_PLL2_CTRL_PFD_OFFSET_EN (1 << 18) |
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| #define | ANADIG_PLL2_CTRL_DITHER_ENABLE (1 << 17) |
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| #define | ANADIG_PLL2_CTRL_BYPASS (1 << 16) |
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| #define | ANADIG_PLL2_CTRL_BYPASS_CLK_SRC (1 << 14) |
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| #define | ANADIG_PLL2_CTRL_ENABLE (1 << 13) |
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| #define | ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) |
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| #define | ANADIG_PLL2_CTRL_DIV_SELECT (1 << 1) |
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| #define | ANADIG_PLL2_SS_STOP_MASK (0xffff << 16) |
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| #define | ANADIG_PLL2_SS_ENABLE (1 << 15) |
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| #define | ANADIG_PLL2_SS_STEP_MASK 0x8fff |
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| #define | ANADIG_PLL2_NUM_MFN_MASK 0x3fffffff |
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| #define | ANADIG_PLL2_DENOM_MFN_MASK 0x3fffffff |
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| #define | ANADIG_PLL4_CTRL_LOCK (1 << 31) |
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| #define | ANADIG_PLL4_CTRL_PFD_OFFSET_EN (1 << 18) |
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| #define | ANADIG_PLL4_CTRL_DITHER_ENABLE (1 << 17) |
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| #define | ANADIG_PLL4_CTRL_BYPASS (1 << 16) |
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| #define | ANADIG_PLL4_CTRL_BYPASS_CLK_SRC (1 << 14) |
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| #define | ANADIG_PLL4_CTRL_ENABLE (1 << 13) |
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| #define | ANADIG_PLL4_CTRL_POWERDOWN (1 << 12) |
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| #define | ANADIG_PLL4_CTRL_DIV_SELECT_MASK (0x7f) |
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| #define | ANADIG_PLL4_NUM_MFN_MASK 0x3fffffff |
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| #define | ANADIG_PLL4_DENOM_MFN_MASK 0x3fffffff |
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| #define | ANADIG_PLL6_CTRL_LOCK (1 << 31) |
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| #define | ANADIG_PLL6_CTRL_PFD_OFFSET_EN (1 << 18) |
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| #define | ANADIG_PLL6_CTRL_DITHER_ENABLE (1 << 17) |
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| #define | ANADIG_PLL6_CTRL_BYPASS (1 << 16) |
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| #define | ANADIG_PLL6_CTRL_BYPASS_CLK_SRC (1 << 14) |
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| #define | ANADIG_PLL6_CTRL_ENABLE (1 << 13) |
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| #define | ANADIG_PLL6_CTRL_POWERDOWN (1 << 12) |
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| #define | ANADIG_PLL6_CTRL_DIV_SELECT_MASK (0x7f) |
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| #define | ANADIG_PLL6_NUM_MFN_MASK 0x3fffffff |
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| #define | ANADIG_PLL6_DENOM_MFN_MASK 0x3fffffff |
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| #define | ANADIG_PLL5_CTRL_LOCK (1 << 31) |
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| #define | ANADIG_PLL5_CTRL_PFD_OFFSET_EN (1 << 18) |
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| #define | ANADIG_PLL5_CTRL_DITHER_ENABLE (1 << 17) |
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| #define | ANADIG_PLL5_CTRL_BYPASS (1 << 16) |
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| #define | ANADIG_PLL5_CTRL_BYPASS_CLK_SRC (1 << 14) |
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| #define | ANADIG_PLL5_CTRL_ENABLE (1 << 13) |
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| #define | ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) |
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| #define | ANADIG_PLL5_CTRL_DIV_SELECT_MASK (0x3) |
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| #define | ANADIG_PLL_PFD4_CLKGATE (1 << 31) |
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| #define | ANADIG_PLL_PFD4_STABLE (1 << 30) |
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| #define | ANADIG_PLL_PFD4_FRAC_SHIFT 24 |
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| #define | ANADIG_PLL_PFD4_FRAC_MASK (0x3f << 24) |
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| #define | ANADIG_PLL_PFD3_CLKGATE (1 << 23) |
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| #define | ANADIG_PLL_PFD3_STABLE (1 << 22) |
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| #define | ANADIG_PLL_PFD3_FRAC_SHIFT 16 |
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| #define | ANADIG_PLL_PFD3_FRAC_MASK (0x3f << 16) |
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| #define | ANADIG_PLL_PFD2_CLKGATE (1 << 15) |
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| #define | ANADIG_PLL_PFD2_STABLE (1 << 14) |
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| #define | ANADIG_PLL_PFD2_FRAC_SHIFT 8 |
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| #define | ANADIG_PLL_PFD2_FRAC_MASK (0x3f << 8) |
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| #define | ANADIG_PLL_PFD1_CLKGATE (1 << 7) |
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| #define | ANADIG_PLL_PFD1_STABLE (1 << 6) |
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| #define | ANADIG_PLL_PFD1_FRAC_SHIFT 0 |
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| #define | ANADIG_PLL_PFD1_FRAC_MASK (0x3f << 0) |
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| #define | ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17) |
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| #define | ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16) |
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| #define | ANADIG_ANA_MISC0_CLK_24M_IRC_XTAL_SEL (1 << 13) |
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| #define | ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12) |
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| #define | ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7) |
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| #define | ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3) |
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| #define | ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2) |
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| #define | ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1) |
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| #define | ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0) |
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| #define | ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30) |
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| #define | ANADIG_ANA_MISC1_IRQ_TEMPSENSE (1 << 29) |
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| #define | ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) |
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| #define | ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) |
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| #define | ANADIG_ANADIG_DIGPROG_MAJOR_MASK (0xffff << 8) |
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| #define | ANADIG_ANADIG_DIGPROG_MINOR_MASK (0xff << 0) |
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| #define | ANADIG_PLL1_CTRL_LOCK (1 << 31) |
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| #define | ANADIG_PLL1_CTRL_PFD_OFFSET_EN (1 << 18) |
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| #define | ANADIG_PLL1_CTRL_DITHER_ENABLE (1 << 17) |
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| #define | ANADIG_PLL1_CTRL_BYPASS (1 << 16) |
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| #define | ANADIG_PLL1_CTRL_BYPASS_CLK_SRC (1 << 14) |
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| #define | ANADIG_PLL1_CTRL_ENABLE (1 << 13) |
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| #define | ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) |
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| #define | ANADIG_PLL1_CTRL_DIV_SELECT (1 << 1) |
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| #define | ANADIG_PLL1_SS_STOP_MASK (0xffff << 16) |
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| #define | ANADIG_PLL1_SS_ENABLE (1 << 15) |
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| #define | ANADIG_PLL1_SS_STEP_MASK 0x8fff |
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| #define | ANADIG_PLL1_NUM_MFN_MASK 0x3fffffff |
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| #define | ANADIG_PLL1_DENOM_MFN_MASK 0x3fffffff |
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| #define | ANADIG_PLL_LOCK_PLL1 (1 << 6) |
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| #define | ANADIG_PLL_LOCK_PLL2 (1 << 5) |
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| #define | ANADIG_PLL_LOCK_PLL4 (1 << 4) |
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| #define | ANADIG_PLL_LOCK_PLL6 (1 << 3) |
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| #define | ANADIG_PLL_LOCK_PLL5 (1 << 2) |
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| #define | ANADIG_PLL_LOCK_PLL3 (1 << 1) |
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| #define | ANADIG_PLL_LOCK_PLL7 (1 << 0) |
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1.9.4