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#define | TIM1 TIM1_BASE |
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#define | TIM2 TIM2_BASE |
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#define | TIM3 TIM3_BASE |
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#define | TIM5 TIM5_BASE |
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#define | TIM6 TIM6_BASE |
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#define | TIM7 TIM7_BASE |
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#define | TIM_CR1(tim_base) MMIO32((tim_base) + 0x00) |
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#define | TIM1_CR1 TIM_CR1(TIM1) |
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#define | TIM2_CR1 TIM_CR1(TIM2) |
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#define | TIM3_CR1 TIM_CR1(TIM3) |
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#define | TIM4_CR1 TIM_CR1(TIM4) |
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#define | TIM5_CR1 TIM_CR1(TIM5) |
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#define | TIM6_CR1 TIM_CR1(TIM6) |
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#define | TIM7_CR1 TIM_CR1(TIM7) |
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#define | TIM8_CR1 TIM_CR1(TIM8) |
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#define | TIM9_CR1 TIM_CR1(TIM9) |
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#define | TIM10_CR1 TIM_CR1(TIM10) |
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#define | TIM11_CR1 TIM_CR1(TIM11) |
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#define | TIM12_CR1 TIM_CR1(TIM12) |
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#define | TIM13_CR1 TIM_CR1(TIM13) |
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#define | TIM14_CR1 TIM_CR1(TIM14) |
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#define | TIM15_CR1 TIM_CR1(TIM15) |
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#define | TIM16_CR1 TIM_CR1(TIM16) |
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#define | TIM17_CR1 TIM_CR1(TIM17) |
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#define | TIM_CR2(tim_base) MMIO32((tim_base) + 0x04) |
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#define | TIM1_CR2 TIM_CR2(TIM1) |
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#define | TIM2_CR2 TIM_CR2(TIM2) |
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#define | TIM3_CR2 TIM_CR2(TIM3) |
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#define | TIM4_CR2 TIM_CR2(TIM4) |
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#define | TIM5_CR2 TIM_CR2(TIM5) |
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#define | TIM6_CR2 TIM_CR2(TIM6) |
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#define | TIM7_CR2 TIM_CR2(TIM7) |
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#define | TIM8_CR2 TIM_CR2(TIM8) |
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#define | TIM15_CR2 TIM_CR2(TIM15) |
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#define | TIM16_CR2 TIM_CR2(TIM16) |
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#define | TIM17_CR2 TIM_CR2(TIM17) |
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#define | TIM_SMCR(tim_base) MMIO32((tim_base) + 0x08) |
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#define | TIM1_SMCR TIM_SMCR(TIM1) |
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#define | TIM2_SMCR TIM_SMCR(TIM2) |
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#define | TIM3_SMCR TIM_SMCR(TIM3) |
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#define | TIM4_SMCR TIM_SMCR(TIM4) |
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#define | TIM5_SMCR TIM_SMCR(TIM5) |
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#define | TIM8_SMCR TIM_SMCR(TIM8) |
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#define | TIM9_SMCR TIM_SMCR(TIM9) |
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#define | TIM12_SMCR TIM_SMCR(TIM12) |
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#define | TIM15_SMCR TIM_SMCR(TIM15) |
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#define | TIM_DIER(tim_base) MMIO32((tim_base) + 0x0C) |
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#define | TIM1_DIER TIM_DIER(TIM1) |
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#define | TIM2_DIER TIM_DIER(TIM2) |
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#define | TIM3_DIER TIM_DIER(TIM3) |
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#define | TIM4_DIER TIM_DIER(TIM4) |
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#define | TIM5_DIER TIM_DIER(TIM5) |
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#define | TIM6_DIER TIM_DIER(TIM6) |
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#define | TIM7_DIER TIM_DIER(TIM7) |
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#define | TIM8_DIER TIM_DIER(TIM8) |
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#define | TIM9_DIER TIM_DIER(TIM9) |
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#define | TIM10_DIER TIM_DIER(TIM10) |
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#define | TIM11_DIER TIM_DIER(TIM11) |
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#define | TIM12_DIER TIM_DIER(TIM12) |
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#define | TIM13_DIER TIM_DIER(TIM13) |
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#define | TIM14_DIER TIM_DIER(TIM14) |
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#define | TIM15_DIER TIM_DIER(TIM15) |
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#define | TIM16_DIER TIM_DIER(TIM16) |
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#define | TIM17_DIER TIM_DIER(TIM17) |
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#define | TIM_SR(tim_base) MMIO32((tim_base) + 0x10) |
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#define | TIM1_SR TIM_SR(TIM1) |
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#define | TIM2_SR TIM_SR(TIM2) |
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#define | TIM3_SR TIM_SR(TIM3) |
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#define | TIM4_SR TIM_SR(TIM4) |
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#define | TIM5_SR TIM_SR(TIM5) |
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#define | TIM6_SR TIM_SR(TIM6) |
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#define | TIM7_SR TIM_SR(TIM7) |
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#define | TIM8_SR TIM_SR(TIM8) |
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#define | TIM9_SR TIM_SR(TIM9) |
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#define | TIM10_SR TIM_SR(TIM10) |
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#define | TIM11_SR TIM_SR(TIM11) |
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#define | TIM12_SR TIM_SR(TIM12) |
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#define | TIM13_SR TIM_SR(TIM13) |
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#define | TIM14_SR TIM_SR(TIM14) |
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#define | TIM15_SR TIM_SR(TIM15) |
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#define | TIM16_SR TIM_SR(TIM16) |
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#define | TIM17_SR TIM_SR(TIM17) |
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#define | TIM_EGR(tim_base) MMIO32((tim_base) + 0x14) |
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#define | TIM1_EGR TIM_EGR(TIM1) |
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#define | TIM2_EGR TIM_EGR(TIM2) |
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#define | TIM3_EGR TIM_EGR(TIM3) |
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#define | TIM4_EGR TIM_EGR(TIM4) |
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#define | TIM5_EGR TIM_EGR(TIM5) |
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#define | TIM6_EGR TIM_EGR(TIM6) |
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#define | TIM7_EGR TIM_EGR(TIM7) |
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#define | TIM8_EGR TIM_EGR(TIM8) |
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#define | TIM9_EGR TIM_EGR(TIM9) |
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#define | TIM10_EGR TIM_EGR(TIM10) |
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#define | TIM11_EGR TIM_EGR(TIM11) |
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#define | TIM12_EGR TIM_EGR(TIM12) |
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#define | TIM13_EGR TIM_EGR(TIM13) |
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#define | TIM14_EGR TIM_EGR(TIM14) |
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#define | TIM15_EGR TIM_EGR(TIM15) |
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#define | TIM16_EGR TIM_EGR(TIM16) |
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#define | TIM17_EGR TIM_EGR(TIM17) |
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#define | TIM_CCMR1(tim_base) MMIO32((tim_base) + 0x18) |
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#define | TIM1_CCMR1 TIM_CCMR1(TIM1) |
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#define | TIM2_CCMR1 TIM_CCMR1(TIM2) |
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#define | TIM3_CCMR1 TIM_CCMR1(TIM3) |
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#define | TIM4_CCMR1 TIM_CCMR1(TIM4) |
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#define | TIM5_CCMR1 TIM_CCMR1(TIM5) |
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#define | TIM8_CCMR1 TIM_CCMR1(TIM8) |
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#define | TIM9_CCMR1 TIM_CCMR1(TIM9) |
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#define | TIM10_CCMR1 TIM_CCMR1(TIM10) |
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#define | TIM11_CCMR1 TIM_CCMR1(TIM11) |
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#define | TIM12_CCMR1 TIM_CCMR1(TIM12) |
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#define | TIM13_CCMR1 TIM_CCMR1(TIM13) |
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#define | TIM14_CCMR1 TIM_CCMR1(TIM14) |
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#define | TIM15_CCMR1 TIM_CCMR1(TIM15) |
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#define | TIM16_CCMR1 TIM_CCMR1(TIM16) |
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#define | TIM17_CCMR1 TIM_CCMR1(TIM17) |
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#define | TIM_CCMR2(tim_base) MMIO32((tim_base) + 0x1C) |
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#define | TIM1_CCMR2 TIM_CCMR2(TIM1) |
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#define | TIM2_CCMR2 TIM_CCMR2(TIM2) |
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#define | TIM3_CCMR2 TIM_CCMR2(TIM3) |
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#define | TIM4_CCMR2 TIM_CCMR2(TIM4) |
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#define | TIM5_CCMR2 TIM_CCMR2(TIM5) |
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#define | TIM8_CCMR2 TIM_CCMR2(TIM8) |
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#define | TIM_CCER(tim_base) MMIO32((tim_base) + 0x20) |
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#define | TIM1_CCER TIM_CCER(TIM1) |
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#define | TIM2_CCER TIM_CCER(TIM2) |
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#define | TIM3_CCER TIM_CCER(TIM3) |
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#define | TIM4_CCER TIM_CCER(TIM4) |
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#define | TIM5_CCER TIM_CCER(TIM5) |
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#define | TIM8_CCER TIM_CCER(TIM8) |
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#define | TIM9_CCER TIM_CCER(TIM9) |
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#define | TIM10_CCER TIM_CCER(TIM10) |
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#define | TIM11_CCER TIM_CCER(TIM11) |
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#define | TIM12_CCER TIM_CCER(TIM12) |
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#define | TIM13_CCER TIM_CCER(TIM13) |
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#define | TIM14_CCER TIM_CCER(TIM14) |
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#define | TIM15_CCER TIM_CCER(TIM15) |
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#define | TIM16_CCER TIM_CCER(TIM16) |
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#define | TIM17_CCER TIM_CCER(TIM17) |
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#define | TIM_CNT(tim_base) MMIO32((tim_base) + 0x24) |
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#define | TIM1_CNT TIM_CNT(TIM1) |
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#define | TIM2_CNT TIM_CNT(TIM2) |
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#define | TIM3_CNT TIM_CNT(TIM3) |
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#define | TIM4_CNT TIM_CNT(TIM4) |
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#define | TIM5_CNT TIM_CNT(TIM5) |
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#define | TIM6_CNT TIM_CNT(TIM6) |
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#define | TIM7_CNT TIM_CNT(TIM7) |
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#define | TIM8_CNT TIM_CNT(TIM8) |
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#define | TIM9_CNT TIM_CNT(TIM9) |
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#define | TIM10_CNT TIM_CNT(TIM10) |
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#define | TIM11_CNT TIM_CNT(TIM11) |
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#define | TIM12_CNT TIM_CNT(TIM12) |
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#define | TIM13_CNT TIM_CNT(TIM13) |
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#define | TIM14_CNT TIM_CNT(TIM14) |
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#define | TIM15_CNT TIM_CNT(TIM15) |
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#define | TIM16_CNT TIM_CNT(TIM16) |
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#define | TIM17_CNT TIM_CNT(TIM17) |
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#define | TIM_PSC(tim_base) MMIO32((tim_base) + 0x28) |
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#define | TIM1_PSC TIM_PSC(TIM1) |
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#define | TIM2_PSC TIM_PSC(TIM2) |
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#define | TIM3_PSC TIM_PSC(TIM3) |
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#define | TIM4_PSC TIM_PSC(TIM4) |
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#define | TIM5_PSC TIM_PSC(TIM5) |
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#define | TIM6_PSC TIM_PSC(TIM6) |
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#define | TIM7_PSC TIM_PSC(TIM7) |
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#define | TIM8_PSC TIM_PSC(TIM8) |
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#define | TIM9_PSC TIM_PSC(TIM9) |
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#define | TIM10_PSC TIM_PSC(TIM10) |
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#define | TIM11_PSC TIM_PSC(TIM11) |
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#define | TIM12_PSC TIM_PSC(TIM12) |
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#define | TIM13_PSC TIM_PSC(TIM13) |
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#define | TIM14_PSC TIM_PSC(TIM14) |
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#define | TIM15_PSC TIM_PSC(TIM15) |
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#define | TIM16_PSC TIM_PSC(TIM16) |
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#define | TIM17_PSC TIM_PSC(TIM17) |
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#define | TIM_ARR(tim_base) MMIO32((tim_base) + 0x2C) |
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#define | TIM1_ARR TIM_ARR(TIM1) |
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#define | TIM2_ARR TIM_ARR(TIM2) |
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#define | TIM3_ARR TIM_ARR(TIM3) |
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#define | TIM4_ARR TIM_ARR(TIM4) |
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#define | TIM5_ARR TIM_ARR(TIM5) |
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#define | TIM6_ARR TIM_ARR(TIM6) |
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#define | TIM7_ARR TIM_ARR(TIM7) |
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#define | TIM8_ARR TIM_ARR(TIM8) |
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#define | TIM9_ARR TIM_ARR(TIM9) |
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#define | TIM10_ARR TIM_ARR(TIM10) |
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#define | TIM11_ARR TIM_ARR(TIM11) |
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#define | TIM12_ARR TIM_ARR(TIM12) |
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#define | TIM13_ARR TIM_ARR(TIM13) |
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#define | TIM14_ARR TIM_ARR(TIM14) |
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#define | TIM15_ARR TIM_ARR(TIM15) |
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#define | TIM16_ARR TIM_ARR(TIM16) |
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#define | TIM17_ARR TIM_ARR(TIM17) |
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#define | TIM_RCR(tim_base) MMIO32((tim_base) + 0x30) |
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#define | TIM1_RCR TIM_RCR(TIM1) |
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#define | TIM8_RCR TIM_RCR(TIM8) |
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#define | TIM15_RCR TIM_RCR(TIM15) |
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#define | TIM16_RCR TIM_RCR(TIM16) |
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#define | TIM17_RCR TIM_RCR(TIM17) |
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#define | TIM_CCR1(tim_base) MMIO32((tim_base) + 0x34) |
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#define | TIM1_CCR1 TIM_CCR1(TIM1) |
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#define | TIM2_CCR1 TIM_CCR1(TIM2) |
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#define | TIM3_CCR1 TIM_CCR1(TIM3) |
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#define | TIM4_CCR1 TIM_CCR1(TIM4) |
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#define | TIM5_CCR1 TIM_CCR1(TIM5) |
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#define | TIM8_CCR1 TIM_CCR1(TIM8) |
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#define | TIM9_CCR1 TIM_CCR1(TIM9) |
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#define | TIM10_CCR1 TIM_CCR1(TIM10) |
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#define | TIM11_CCR1 TIM_CCR1(TIM11) |
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#define | TIM12_CCR1 TIM_CCR1(TIM12) |
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#define | TIM13_CCR1 TIM_CCR1(TIM13) |
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#define | TIM14_CCR1 TIM_CCR1(TIM14) |
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#define | TIM15_CCR1 TIM_CCR1(TIM15) |
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#define | TIM16_CCR1 TIM_CCR1(TIM16) |
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#define | TIM17_CCR1 TIM_CCR1(TIM17) |
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#define | TIM_CCR2(tim_base) MMIO32((tim_base) + 0x38) |
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#define | TIM1_CCR2 TIM_CCR2(TIM1) |
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#define | TIM2_CCR2 TIM_CCR2(TIM2) |
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#define | TIM3_CCR2 TIM_CCR2(TIM3) |
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#define | TIM4_CCR2 TIM_CCR2(TIM4) |
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#define | TIM5_CCR2 TIM_CCR2(TIM5) |
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#define | TIM8_CCR2 TIM_CCR2(TIM8) |
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#define | TIM9_CCR2 TIM_CCR2(TIM9) |
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#define | TIM12_CCR2 TIM_CCR2(TIM12) |
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#define | TIM15_CCR2 TIM_CCR2(TIM15) |
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#define | TIM_CCR3(tim_base) MMIO32((tim_base) + 0x3C) |
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#define | TIM1_CCR3 TIM_CCR3(TIM1) |
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#define | TIM2_CCR3 TIM_CCR3(TIM2) |
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#define | TIM3_CCR3 TIM_CCR3(TIM3) |
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#define | TIM4_CCR3 TIM_CCR3(TIM4) |
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#define | TIM5_CCR3 TIM_CCR3(TIM5) |
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#define | TIM8_CCR3 TIM_CCR3(TIM8) |
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#define | TIM_CCR4(tim_base) MMIO32((tim_base) + 0x40) |
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#define | TIM1_CCR4 TIM_CCR4(TIM1) |
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#define | TIM2_CCR4 TIM_CCR4(TIM2) |
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#define | TIM3_CCR4 TIM_CCR4(TIM3) |
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#define | TIM4_CCR4 TIM_CCR4(TIM4) |
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#define | TIM5_CCR4 TIM_CCR4(TIM5) |
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#define | TIM8_CCR4 TIM_CCR4(TIM8) |
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#define | TIM_BDTR(tim_base) MMIO32((tim_base) + 0x44) |
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#define | TIM1_BDTR TIM_BDTR(TIM1) |
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#define | TIM8_BDTR TIM_BDTR(TIM8) |
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#define | TIM15_BDTR TIM_BDTR(TIM15) |
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#define | TIM16_BDTR TIM_BDTR(TIM16) |
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#define | TIM17_BDTR TIM_BDTR(TIM17) |
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#define | TIM_DCR(tim_base) MMIO32((tim_base) + 0x48) |
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#define | TIM1_DCR TIM_DCR(TIM1) |
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#define | TIM2_DCR TIM_DCR(TIM2) |
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#define | TIM3_DCR TIM_DCR(TIM3) |
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#define | TIM4_DCR TIM_DCR(TIM4) |
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#define | TIM5_DCR TIM_DCR(TIM5) |
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#define | TIM8_DCR TIM_DCR(TIM8) |
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#define | TIM15_DCR TIM_DCR(TIM15) |
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#define | TIM16_DCR TIM_DCR(TIM16) |
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#define | TIM17_DCR TIM_DCR(TIM17) |
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#define | TIM_DMAR(tim_base) MMIO32((tim_base) + 0x4C) |
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#define | TIM1_DMAR TIM_DMAR(TIM1) |
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#define | TIM2_DMAR TIM_DMAR(TIM2) |
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#define | TIM3_DMAR TIM_DMAR(TIM3) |
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#define | TIM4_DMAR TIM_DMAR(TIM4) |
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#define | TIM5_DMAR TIM_DMAR(TIM5) |
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#define | TIM8_DMAR TIM_DMAR(TIM8) |
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#define | TIM15_DMAR TIM_DMAR(TIM15) |
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#define | TIM16_DMAR TIM_DMAR(TIM16) |
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#define | TIM17_DMAR TIM_DMAR(TIM17) |
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#define | TIM_CR1_CKD_CK_INT (0x0 << 8) |
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#define | TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) |
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#define | TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) |
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#define | TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) |
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#define | TIM_CR1_ARPE (1 << 7) |
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#define | TIM_CR1_CMS_EDGE (0x0 << 5) |
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#define | TIM_CR1_CMS_CENTER_1 (0x1 << 5) |
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#define | TIM_CR1_CMS_CENTER_2 (0x2 << 5) |
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#define | TIM_CR1_CMS_CENTER_3 (0x3 << 5) |
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#define | TIM_CR1_CMS_MASK (0x3 << 5) |
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#define | TIM_CR1_DIR_UP (0 << 4) |
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#define | TIM_CR1_DIR_DOWN (1 << 4) |
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#define | TIM_CR1_OPM (1 << 3) |
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#define | TIM_CR1_URS (1 << 2) |
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#define | TIM_CR1_UDIS (1 << 1) |
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#define | TIM_CR1_CEN (1 << 0) |
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#define | TIM_CR2_OIS4 (1 << 14) |
| Output idle state 4 (OC4 output) More...
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#define | TIM_CR2_OIS3N (1 << 13) |
| Output idle state 3 (OC3N output) More...
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#define | TIM_CR2_OIS3 (1 << 12) |
| Output idle state 3 (OC3 output) More...
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#define | TIM_CR2_OIS2N (1 << 11) |
| Output idle state 2 (OC2N output) More...
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#define | TIM_CR2_OIS2 (1 << 10) |
| Output idle state 2 (OC2 output) More...
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#define | TIM_CR2_OIS1N (1 << 9) |
| Output idle state 1 (OC1N output) More...
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#define | TIM_CR2_OIS1 (1 << 8) |
| Output idle state 1 (OC1 output) More...
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#define | TIM_CR2_OIS_MASK (0x7f << 8) |
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#define | TIM_CR2_TI1S (1 << 7) |
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#define | TIM_CR2_MMS_RESET (0x0 << 4) |
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#define | TIM_CR2_MMS_ENABLE (0x1 << 4) |
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#define | TIM_CR2_MMS_UPDATE (0x2 << 4) |
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#define | TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) |
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#define | TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) |
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#define | TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) |
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#define | TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) |
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#define | TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) |
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#define | TIM_CR2_MMS_MASK (0x7 << 4) |
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#define | TIM_CR2_CCDS (1 << 3) |
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#define | TIM_CR2_CCUS (1 << 2) |
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#define | TIM_CR2_CCPC (1 << 0) |
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#define | TIM_SMCR_ETP (1 << 15) |
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#define | TIM_SMCR_ECE (1 << 14) |
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#define | TIM_SMCR_ETPS_OFF (0x0 << 12) |
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#define | TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) |
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#define | TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) |
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#define | TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) |
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#define | TIM_SMCR_ETPS_MASK (0X3 << 12) |
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#define | TIM_SMCR_ETF_OFF (0x0 << 8) |
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#define | TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) |
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#define | TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) |
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#define | TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) |
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#define | TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) |
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#define | TIM_SMCR_ETF_MASK (0xF << 8) |
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#define | TIM_SMCR_MSM (1 << 7) |
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#define | TIM_SMCR_TS_ITR0 (0x0 << 4) |
| Internal Trigger 0 (ITR0) More...
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#define | TIM_SMCR_TS_ITR1 (0x1 << 4) |
| Internal Trigger 1 (ITR1) More...
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#define | TIM_SMCR_TS_ITR2 (0x2 << 4) |
| Internal Trigger 2 (ITR2) More...
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#define | TIM_SMCR_TS_ITR3 (0x3 << 4) |
| Internal Trigger 3 (ITR3) More...
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#define | TIM_SMCR_TS_TI1F_ED (0x4 << 4) |
| TI1 Edge Detector (TI1F_ED) More...
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#define | TIM_SMCR_TS_TI1FP1 (0x5 << 4) |
| Filtered Timer Input 1 (TI1FP1) More...
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#define | TIM_SMCR_TS_TI2FP2 (0x6 << 4) |
| Filtered Timer Input 2 (TI2FP2) More...
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#define | TIM_SMCR_TS_ETRF (0x7 << 4) |
| External Trigger input (ETRF) More...
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#define | TIM_SMCR_TS_MASK (0x7 << 4) |
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#define | TIM_SMCR_SMS_OFF (0x0 << 0) |
| Slave mode disabled. More...
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#define | TIM_SMCR_SMS_EM1 (0x1 << 0) |
| Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. More...
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#define | TIM_SMCR_SMS_EM2 (0x2 << 0) |
| Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. More...
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#define | TIM_SMCR_SMS_EM3 (0x3 << 0) |
| Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the complementary input. More...
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#define | TIM_SMCR_SMS_RM (0x4 << 0) |
| Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. More...
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#define | TIM_SMCR_SMS_GM (0x5 << 0) |
| Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. More...
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#define | TIM_SMCR_SMS_TM (0x6 << 0) |
| Trigger Mode - The counter starts at a rising edge of the trigger TRGI. More...
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#define | TIM_SMCR_SMS_ECM1 (0x7 << 0) |
| External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. More...
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#define | TIM_SMCR_SMS_MASK (0x7 << 0) |
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#define | TIM_DIER_TDE (1 << 14) |
| Trigger DMA request enable. More...
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#define | TIM_DIER_COMDE (1 << 13) |
| COM DMA request enable. More...
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#define | TIM_DIER_CC4DE (1 << 12) |
| Capture/Compare 4 DMA request enable. More...
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#define | TIM_DIER_CC3DE (1 << 11) |
| Capture/Compare 3 DMA request enable. More...
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#define | TIM_DIER_CC2DE (1 << 10) |
| Capture/Compare 2 DMA request enable. More...
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#define | TIM_DIER_CC1DE (1 << 9) |
| Capture/Compare 1 DMA request enable. More...
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#define | TIM_DIER_UDE (1 << 8) |
| : Update DMA request enable More...
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#define | TIM_DIER_BIE (1 << 7) |
| Break interrupt enable. More...
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#define | TIM_DIER_TIE (1 << 6) |
| Trigger interrupt enable. More...
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#define | TIM_DIER_COMIE (1 << 5) |
| COM interrupt enable. More...
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#define | TIM_DIER_CC4IE (1 << 4) |
| Capture/compare 4 interrupt enable. More...
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#define | TIM_DIER_CC3IE (1 << 3) |
| Capture/compare 3 interrupt enable. More...
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#define | TIM_DIER_CC2IE (1 << 2) |
| Capture/compare 2 interrupt enable. More...
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#define | TIM_DIER_CC1IE (1 << 1) |
| Capture/compare 1 interrupt enable. More...
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#define | TIM_DIER_UIE (1 << 0) |
| Update interrupt enable. More...
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#define | TIM_SR_CC4OF (1 << 12) |
| Capture/compare 4 overcapture flag. More...
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#define | TIM_SR_CC3OF (1 << 11) |
| Capture/compare 3 overcapture flag. More...
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#define | TIM_SR_CC2OF (1 << 10) |
| Capture/compare 2 overcapture flag. More...
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#define | TIM_SR_CC1OF (1 << 9) |
| Capture/compare 1 overcapture flag. More...
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#define | TIM_SR_BIF (1 << 7) |
| Break interrupt flag. More...
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#define | TIM_SR_TIF (1 << 6) |
| Trigger interrupt flag. More...
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#define | TIM_SR_COMIF (1 << 5) |
| COM interrupt flag. More...
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#define | TIM_SR_CC4IF (1 << 4) |
| Capture/compare 4 interrupt flag. More...
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#define | TIM_SR_CC3IF (1 << 3) |
| Capture/compare 3 interrupt flag. More...
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#define | TIM_SR_CC2IF (1 << 2) |
| Capture/compare 2 interrupt flag. More...
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#define | TIM_SR_CC1IF (1 << 1) |
| Capture/compare 1 interrupt flag. More...
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#define | TIM_SR_UIF (1 << 0) |
| Update interrupt flag. More...
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#define | TIM_EGR_BG (1 << 7) |
| Break generation. More...
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#define | TIM_EGR_TG (1 << 6) |
| Trigger generation. More...
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#define | TIM_EGR_COMG (1 << 5) |
| Capture/compare control update generation. More...
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#define | TIM_EGR_CC4G (1 << 4) |
| Capture/compare 4 generation. More...
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#define | TIM_EGR_CC3G (1 << 3) |
| Capture/compare 3 generation. More...
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#define | TIM_EGR_CC2G (1 << 2) |
| Capture/compare 2 generation. More...
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#define | TIM_EGR_CC1G (1 << 1) |
| Capture/compare 1 generation. More...
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#define | TIM_EGR_UG (1 << 0) |
| Update generation. More...
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#define | TIM_CCMR1_OC2CE (1 << 15) |
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#define | TIM_CCMR1_OC2M_FROZEN (0x0 << 12) |
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#define | TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) |
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#define | TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) |
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#define | TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) |
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#define | TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) |
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#define | TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) |
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#define | TIM_CCMR1_OC2M_PWM1 (0x6 << 12) |
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#define | TIM_CCMR1_OC2M_PWM2 (0x7 << 12) |
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#define | TIM_CCMR1_OC2M_MASK (0x7 << 12) |
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#define | TIM_CCMR1_OC2PE (1 << 11) |
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#define | TIM_CCMR1_OC2FE (1 << 10) |
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#define | TIM_CCMR1_CC2S_OUT (0x0 << 8) |
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#define | TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) |
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#define | TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) |
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#define | TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) |
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#define | TIM_CCMR1_CC2S_MASK (0x3 << 8) |
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#define | TIM_CCMR1_OC1CE (1 << 7) |
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#define | TIM_CCMR1_OC1M_FROZEN (0x0 << 4) |
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#define | TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) |
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#define | TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) |
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#define | TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) |
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#define | TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) |
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#define | TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) |
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#define | TIM_CCMR1_OC1M_PWM1 (0x6 << 4) |
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#define | TIM_CCMR1_OC1M_PWM2 (0x7 << 4) |
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#define | TIM_CCMR1_OC1M_MASK (0x7 << 4) |
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#define | TIM_CCMR1_OC1PE (1 << 3) |
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#define | TIM_CCMR1_OC1FE (1 << 2) |
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#define | TIM_CCMR1_CC1S_OUT (0x0 << 0) |
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#define | TIM_CCMR1_CC1S_IN_TI2 (0x2 << 0) |
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#define | TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0) |
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#define | TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) |
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#define | TIM_CCMR1_CC1S_MASK (0x3 << 0) |
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#define | TIM_CCMR1_IC2F_OFF (0x0 << 12) |
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#define | TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) |
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#define | TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) |
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#define | TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) |
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#define | TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) |
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#define | TIM_CCMR1_IC2F_MASK (0xF << 12) |
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#define | TIM_CCMR1_IC2PSC_OFF (0x0 << 10) |
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#define | TIM_CCMR1_IC2PSC_2 (0x1 << 10) |
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#define | TIM_CCMR1_IC2PSC_4 (0x2 << 10) |
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#define | TIM_CCMR1_IC2PSC_8 (0x3 << 10) |
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#define | TIM_CCMR1_IC2PSC_MASK (0x3 << 10) |
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#define | TIM_CCMR1_IC1F_OFF (0x0 << 4) |
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#define | TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) |
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#define | TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) |
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#define | TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) |
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#define | TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) |
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#define | TIM_CCMR1_IC1F_MASK (0xF << 4) |
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#define | TIM_CCMR1_IC1PSC_OFF (0x0 << 2) |
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#define | TIM_CCMR1_IC1PSC_2 (0x1 << 2) |
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#define | TIM_CCMR1_IC1PSC_4 (0x2 << 2) |
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#define | TIM_CCMR1_IC1PSC_8 (0x3 << 2) |
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#define | TIM_CCMR1_IC1PSC_MASK (0x3 << 2) |
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#define | TIM_CCMR2_OC4CE (1 << 15) |
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#define | TIM_CCMR2_OC4M_FROZEN (0x0 << 12) |
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#define | TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) |
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#define | TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) |
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#define | TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) |
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#define | TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) |
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#define | TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) |
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#define | TIM_CCMR2_OC4M_PWM1 (0x6 << 12) |
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#define | TIM_CCMR2_OC4M_PWM2 (0x7 << 12) |
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#define | TIM_CCMR2_OC4M_MASK (0x7 << 12) |
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#define | TIM_CCMR2_OC4PE (1 << 11) |
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#define | TIM_CCMR2_OC4FE (1 << 10) |
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#define | TIM_CCMR2_CC4S_OUT (0x0 << 8) |
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#define | TIM_CCMR2_CC4S_IN_TI4 (0x1 << 8) |
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#define | TIM_CCMR2_CC4S_IN_TI3 (0x2 << 8) |
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#define | TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) |
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#define | TIM_CCMR2_CC4S_MASK (0x3 << 8) |
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#define | TIM_CCMR2_OC3CE (1 << 7) |
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#define | TIM_CCMR2_OC3M_FROZEN (0x0 << 4) |
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#define | TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) |
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#define | TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) |
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#define | TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) |
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#define | TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) |
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#define | TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) |
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#define | TIM_CCMR2_OC3M_PWM1 (0x6 << 4) |
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#define | TIM_CCMR2_OC3M_PWM2 (0x7 << 4) |
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#define | TIM_CCMR2_OC3M_MASK (0x7 << 4) |
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#define | TIM_CCMR2_OC3PE (1 << 3) |
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#define | TIM_CCMR2_OC3FE (1 << 2) |
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#define | TIM_CCMR2_CC3S_OUT (0x0 << 0) |
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#define | TIM_CCMR2_CC3S_IN_TI3 (0x1 << 0) |
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#define | TIM_CCMR2_CC3S_IN_TI4 (0x2 << 0) |
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#define | TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) |
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#define | TIM_CCMR2_CC3S_MASK (0x3 << 0) |
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#define | TIM_CCMR2_IC4F_OFF (0x0 << 12) |
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#define | TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) |
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#define | TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) |
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#define | TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) |
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#define | TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) |
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#define | TIM_CCMR2_IC4F_MASK (0xF << 12) |
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#define | TIM_CCMR2_IC4PSC_OFF (0x0 << 10) |
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#define | TIM_CCMR2_IC4PSC_2 (0x1 << 10) |
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#define | TIM_CCMR2_IC4PSC_4 (0x2 << 10) |
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#define | TIM_CCMR2_IC4PSC_8 (0x3 << 10) |
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#define | TIM_CCMR2_IC4PSC_MASK (0x3 << 10) |
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#define | TIM_CCMR2_IC3F_OFF (0x0 << 4) |
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#define | TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) |
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#define | TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) |
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#define | TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) |
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#define | TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) |
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#define | TIM_CCMR2_IC3F_MASK (0xF << 4) |
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#define | TIM_CCMR2_IC3PSC_OFF (0x0 << 2) |
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#define | TIM_CCMR2_IC3PSC_2 (0x1 << 2) |
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#define | TIM_CCMR2_IC3PSC_4 (0x2 << 2) |
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#define | TIM_CCMR2_IC3PSC_8 (0x3 << 2) |
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#define | TIM_CCMR2_IC3PSC_MASK (0x3 << 2) |
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#define | TIM_CCER_CC4NP (1 << 15) |
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#define | TIM_CCER_CC4P (1 << 13) |
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#define | TIM_CCER_CC4E (1 << 12) |
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#define | TIM_CCER_CC3NP (1 << 11) |
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#define | TIM_CCER_CC3NE (1 << 10) |
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#define | TIM_CCER_CC3P (1 << 9) |
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#define | TIM_CCER_CC3E (1 << 8) |
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#define | TIM_CCER_CC2NP (1 << 7) |
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#define | TIM_CCER_CC2NE (1 << 6) |
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#define | TIM_CCER_CC2P (1 << 5) |
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#define | TIM_CCER_CC2E (1 << 4) |
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#define | TIM_CCER_CC1NP (1 << 3) |
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#define | TIM_CCER_CC1NE (1 << 2) |
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#define | TIM_CCER_CC1P (1 << 1) |
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#define | TIM_CCER_CC1E (1 << 0) |
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#define | TIM_BDTR_MOE (1 << 15) |
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#define | TIM_BDTR_AOE (1 << 14) |
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#define | TIM_BDTR_BKP (1 << 13) |
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#define | TIM_BDTR_BKE (1 << 12) |
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#define | TIM_BDTR_OSSR (1 << 11) |
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#define | TIM_BDTR_OSSI (1 << 10) |
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#define | TIM_BDTR_LOCK_OFF (0x0 << 8) |
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#define | TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) |
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#define | TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) |
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#define | TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) |
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#define | TIM_BDTR_LOCK_MASK (0x3 << 8) |
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#define | TIM_BDTR_DTG_MASK 0x00FF |
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#define | TIM_BDTR_DBL_MASK (0x1F << 8) |
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#define | TIM_BDTR_DBA_MASK (0x1F << 0) |
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