|
#define | SPI_DR8(spi_base) MMIO8((spi_base) + 0x0c) |
|
#define | SPI1_DR8 SPI_DR8(SPI1_BASE) |
|
#define | SPI2_DR8 SPI_DR8(SPI2_BASE) |
|
#define | SPI3_DR8 SPI_DR8(SPI3_BASE) |
|
#define | SPI_CR1_CRCL_8BIT (0 << 11) |
|
#define | SPI_CR1_CRCL_16BIT (1 << 11) |
|
#define | SPI_CR1_CRCL (1 << 11) |
|
#define | SPI_CR2_LDMA_TX (1 << 14) |
|
#define | SPI_CR2_LDMA_RX (1 << 13) |
|
#define | SPI_CR2_FRXTH (1 << 12) |
|
#define | SPI_CR2_FRF (1 << 4) |
|
#define | SPI_CR2_FRF_MOTOROLA_MODE (0 << 4) |
|
#define | SPI_CR2_FRF_TI_MODE (1 << 4) |
|
#define | SPI_CR2_DS_4BIT (0x3 << 8) |
|
#define | SPI_CR2_DS_5BIT (0x4 << 8) |
|
#define | SPI_CR2_DS_6BIT (0x5 << 8) |
|
#define | SPI_CR2_DS_7BIT (0x6 << 8) |
|
#define | SPI_CR2_DS_8BIT (0x7 << 8) |
|
#define | SPI_CR2_DS_9BIT (0x8 << 8) |
|
#define | SPI_CR2_DS_10BIT (0x9 << 8) |
|
#define | SPI_CR2_DS_11BIT (0xA << 8) |
|
#define | SPI_CR2_DS_12BIT (0xB << 8) |
|
#define | SPI_CR2_DS_13BIT (0xC << 8) |
|
#define | SPI_CR2_DS_14BIT (0xD << 8) |
|
#define | SPI_CR2_DS_15BIT (0xE << 8) |
|
#define | SPI_CR2_DS_16BIT (0xF << 8) |
|
#define | SPI_CR2_DS_MASK (0xF << 8) |
|
#define | SPI_CR2_NSSP (1 << 3) |
|
#define | SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11) |
|
#define | SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11) |
|
#define | SPI_SR_FTLVL_HALF_FIFO (0x2 << 11) |
|
#define | SPI_SR_FTLVL_FIFO_FULL (0x3 << 11) |
|
#define | SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9) |
|
#define | SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9) |
|
#define | SPI_SR_FRLVL_HALF_FIFO (0x2 << 9) |
|
#define | SPI_SR_FRLVL_FIFO_FULL (0x3 << 9) |
|
#define | SPI_SR_FRE (1 << 8) |
|