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#define | FDCAN_FIFO0 0 |
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#define | FDCAN_FIFO1 1 |
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#define | FDCAN_BLOCK_ID(can_base) (((can_base) - CAN1)/(CAN2 - CAN1)) |
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#define | FDCAN_CREL(can_base) MMIO32(can_base + 0x0000) |
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#define | FDCAN_ENDN(can_base) MMIO32(can_base + 0x0004) |
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#define | FDCAN_DBTP(can_base) MMIO32(can_base + 0x000C) |
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#define | FDCAN_TEST(can_base) MMIO32(can_base + 0x0010) |
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#define | FDCAN_RWD(can_base) MMIO32(can_base + 0x0014) |
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#define | FDCAN_CCCR(can_base) MMIO32(can_base + 0x0018) |
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#define | FDCAN_NBTP(can_base) MMIO32(can_base + 0x001C) |
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#define | FDCAN_TSCC(can_base) MMIO32(can_base + 0x0020) |
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#define | FDCAN_TSCV(can_base) MMIO32(can_base + 0x0024) |
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#define | FDCAN_TOCC(can_base) MMIO32(can_base + 0x0028) |
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#define | FDCAN_TOCV(can_base) MMIO32(can_base + 0x002C) |
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#define | FDCAN_ECR(can_base) MMIO32(can_base + 0x0040) |
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#define | FDCAN_PSR(can_base) MMIO32(can_base + 0x0044) |
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#define | FDCAN_TDCR(can_base) MMIO32(can_base + 0x0048) |
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#define | FDCAN_IR(can_base) MMIO32(can_base + 0x0050) |
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#define | FDCAN_IE(can_base) MMIO32(can_base + 0x0054) |
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#define | FDCAN_ILS(can_base) MMIO32(can_base + 0x0058) |
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#define | FDCAN_ILE(can_base) MMIO32(can_base + 0x005C) |
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#define | FDCAN_RXFIS(can_base, fifo_id) MMIO32(can_base + FDCAN_RXFIS_BASE + (FDCAN_RXFI_OFFSET * fifo_id)) |
| Generic access to Rx FIFO status registers. More...
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#define | FDCAN_RXF0S(can_base) FDCAN_RXFIS(can_base, 0) |
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#define | FDCAN_RXF1S(can_base) FDCAN_RXFIS(can_base, 1) |
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#define | FDCAN_RXFIA(can_base, fifo_id) MMIO32(can_base + FDCAN_RXFIA_BASE + (FDCAN_RXFI_OFFSET * fifo_id)) |
| Generic access to Rx FIFO acknowledge registers. More...
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#define | FDCAN_RXF0A(can_base) FDCAN_RXFIA(can_base, 0) |
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#define | FDCAN_RXF1A(can_base) FDCAN_RXFIA(can_base, 1) |
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#define | FDCAN_TXBC(can_base) MMIO32(can_base + 0x00C0) |
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#define | FDCAN_TXFQS(can_base) MMIO32(can_base + 0x00C4) |
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#define | FDCAN_CREL_DAY_SHIFT 0 |
| DAY[7:0]: FDCAN core revision date. More...
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#define | FDCAN_CREL_DAY_MASK 0xFF |
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#define | FDCAN_CREL_MON_SHIFT 8 |
| MON[7:0]: FDCAN core revision month. More...
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#define | FDCAN_CREL_MON_MASK 0xFF |
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#define | FDCAN_CREL_YEAR_SHIFT 16 |
| YEAR[3:0]: FDCAN core revision year. More...
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#define | FDCAN_CREL_YEAR_MASK 0xF |
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#define | FDCAN_CREL_SUBSTEP_SHIFT 20 |
| SUBSTEP[3:0]: FDCAN core release sub stepping. More...
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#define | FDCAN_CREL_SUBSTEP_MASK 0xF |
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#define | FDCAN_CREL_STEP_SHIFT 24 |
| STEP[3:0]: FDCAN core release stepping. More...
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#define | FDCAN_CREL_STEP_MASK 0xF |
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#define | FDCAN_CREL_REL_SHIFT 28 |
| REL[3:0]: FDCAN core release number. More...
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#define | FDCAN_CREL_REL_MASK 0xF |
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#define | FDCAN_DBTP_DSJW_SHIFT 0 |
| DSJW[3:0]: Synchronization jump width. More...
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#define | FDCAN_DBTP_DSJW_MASK 0xF |
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#define | FDCAN_DBTP_DTSEG2_SHIFT 4 |
| DTSEG2[3:0]: Data time segment after sample point. More...
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#define | FDCAN_DBTP_DTSEG2_MASK 0xF |
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#define | FDCAN_DBTP_DTSEG1_SHIFT 8 |
| DTSEG1[4:0]: Data time segment before sample point. More...
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#define | FDCAN_DBTP_DTSEG1_MASK 0x1F |
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#define | FDCAN_DBTP_DBRP_SHIFT 16 |
| DBRP[4:0]: Data bit rate prescaler. More...
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#define | FDCAN_DBTP_DBRP_MASK 0x1F |
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#define | FDCAN_DBTP_TDC (1 << 23) |
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#define | FDCAN_TEST_LBCK (1 << 4) |
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#define | FDCAN_TEST_TX_SHIFT 5 |
| TX[1:0]: Control of transmit pin. More...
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#define | FDCAN_TEST_TX_MASK 0x3 |
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#define | FDCAN_TEST_RX (1 << 7) |
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#define | FDCAN_RWD_WDC_SHIFT 0 |
| WDC[7:0]: RAM watchdog configuration. More...
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#define | FDCAN_RWD_WDC_MASK 0xFF |
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#define | FDCAN_RWD_WDV_SHIFT 7 |
| WDV[7:0]: RAM watchdog actual value. More...
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#define | FDCAN_RWD_WDV_MASK 0xFF |
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#define | FDCAN_CCCR_INIT (1 << 0) |
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#define | FDCAN_CCCR_CCE (1 << 1) |
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#define | FDCAN_CCCR_ASM (1 << 2) |
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#define | FDCAN_CCCR_CSA (1 << 3) |
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#define | FDCAN_CCCR_CSR (1 << 4) |
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#define | FDCAN_CCCR_MON (1 << 5) |
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#define | FDCAN_CCCR_DAR (1 << 6) |
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#define | FDCAN_CCCR_TEST (1 << 7) |
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#define | FDCAN_CCCR_FDOE (1 << 8) |
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#define | FDCAN_CCCR_BRSE (1 << 9) |
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#define | FDCAN_CCCR_PXHD (1 << 12) |
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#define | FDCAN_CCCR_EFBI (1 << 13) |
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#define | FDCAN_CCCR_TXP (1 << 14) |
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#define | FDCAN_CCCR_NISO (1 << 15) |
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#define | FDCAN_CCCR_INIT_TIMEOUT 0x0000FFFF |
| Timeout for FDCAN_CCCR register INIT bit to accept set value. More...
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#define | FDCAN_NBTP_NTSEG2_SHIFT 0 |
| NTSEG2[6:0]: Nominal timing segment after sample point length. More...
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#define | FDCAN_NBTP_NTSEG2_MASK 0x7F |
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#define | FDCAN_NBTP_NTSEG1_SHIFT 8 |
| NTSEG1[7:0]: Nominal timing segment before sample point length. More...
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#define | FDCAN_NBTP_NTSEG1_MASK 0xFF |
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#define | FDCAN_NBTP_NBRP_SHIFT 16 |
| NBRP[8:0]: Norminal timing bit rate prescaler. More...
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#define | FDCAN_NBTP_NBRP_MASK 0x1FF |
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#define | FDCAN_NBTP_NSJW_SHIFT 25 |
| NSJW[6:0]: Norminal timing resynchronization jumb width. More...
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#define | FDCAN_NBTP_NSJW_MASK 0x7F |
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#define | FDCAN_TSCC_TSS_SHIFT 0 |
| TSS[1:0]: Timestamp select. More...
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#define | FDCAN_TSCC_TSS_MASK 0x3 |
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#define | FDCAN_TSCC_TCP_SHIFT 16 |
| TCP[3:0]: Timestamp counter prescaler. More...
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#define | FDCAN_TSCC_TCP_MASK 0xF |
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#define | FDCAN_TSCV_TSC_SHIFT 0 |
| TSC[15:0]: Timestamp counter value. More...
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#define | FDCAN_TSCV_TSC_MASK 0xFFFF |
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#define | FDCAN_TOCC_ETOC (1 << 0) |
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#define | FDCAN_TOCC_TOS_SHIFT 1 |
| TOS[1:0]: Timeout select. More...
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#define | FDCAN_TOCC_TOS_MASK 0x3 |
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#define | FDCAN_TOCC_TOP_SHIFT 16 |
| TOP[15:0]: Timeout period. More...
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#define | FDCAN_TOCC_TOP_MASK 0xFFFF |
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#define | FDCAN_TOCV_TOC_SHIFT 0 |
| TOC[15:0]: Timeout counter. More...
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#define | FDCAN_TOCV_TOC_MASK 0xFFFF |
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#define | FDCAN_ECR_TEC_SHIFT 0 |
| TEC[7:0]: Transmit error counter. More...
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#define | FDCAN_ECR_TEC_MASK 0xFF |
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#define | FDCAN_ECR_REC_SHIFT 8 |
| REC[6:0]: Receive error counter. More...
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#define | FDCAN_ECR_REC_MASK 0x7F |
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#define | FDCAN_ECR_RP (1 << 15) |
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#define | FDCAN_ECR_CEL_SHIFT 16 |
| CEL[7:0]: CAN error logging. More...
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#define | FDCAN_ECR_CEL_MASK 0xFF |
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#define | FDCAN_PSR_LEC_SHIFT 0 |
| LEC[2:0]: Last error code. More...
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#define | FDCAN_PSR_LEC_MASK 0x7 |
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#define | FDCAN_PSR_ACT_SHIFT 3 |
| ACT[1:0]: CAN block activity. More...
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#define | FDCAN_PSR_ACT_MASK 0x3 |
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#define | FDCAN_PSR_EP (1 << 5) |
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#define | FDCAN_PSR_EW (1 << 6) |
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#define | FDCAN_PSR_BO (1 << 7) |
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#define | FDCAN_PSR_DLEC_SHIFT 8 |
| DLEC[2:0]: Last error code in data section. More...
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#define | FDCAN_PSR_DLEC_MASK 0x7 |
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#define | FDCAN_PSR_RESI (1 << 11) |
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#define | FDCAN_PSR_RBRSRESI1 (1 << 12) |
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#define | FDCAN_PSR_REDL (1 << 13) |
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#define | FDCAN_PSR_PXE (1 << 14) |
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#define | FDCAN_PSR_TDCV_SHIFT 16 |
| TDCV[6:0]: Transmitter delay compensation value. More...
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#define | FDCAN_PSR_TDCV_MASK 0x7F |
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#define | FDCAN_TDCR_TDCF_SHIFT 0 |
| TDCF[6:0]: Transmitter delay compensation filter window length. More...
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#define | FDCAN_TDCR_TDCF_MASK 0x7F |
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#define | FDCAN_TDCR_TDCO_SHIFT 8 |
| TDCO[6:0]: Transmitter delay compensation offset. More...
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#define | FDCAN_TDCR_TDCO_MASK 0x7F |
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#define | FDCAN_IR_RF0N (1 << 0) |
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#define | FDCAN_IR_RF0F (1 << 1) |
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#define | FDCAN_IR_RF0L (1 << 2) |
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#define | FDCAN_IR_RF1N (1 << 3) |
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#define | FDCAN_IR_RF1F (1 << 4) |
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#define | FDCAN_IR_RF1L (1 << 5) |
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#define | FDCAN_IR_HPM (1 << 6) |
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#define | FDCAN_IR_TC (1 << 7) |
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#define | FDCAN_IR_TCF (1 << 8) |
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#define | FDCAN_IR_TFE (1 << 9) |
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#define | FDCAN_IR_TEFN (1 << 10) |
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#define | FDCAN_IR_TEFF (1 << 11) |
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#define | FDCAN_IR_TEFL (1 << 12) |
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#define | FDCAN_IR_TSW (1 << 13) |
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#define | FDCAN_IR_MRAF (1 << 14) |
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#define | FDCAN_IR_TOO (1 << 15) |
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#define | FDCAN_IR_ELO (1 << 16) |
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#define | FDCAN_IR_EP (1 << 17) |
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#define | FDCAN_IR_EW (1 << 18) |
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#define | FDCAN_IR_BO (1 << 19) |
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#define | FDCAN_IR_WDI (1 << 20) |
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#define | FDCAN_IR_PEA (1 << 21) |
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#define | FDCAN_IR_PED (1 << 22) |
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#define | FDCAN_IR_ARA (1 << 23) |
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#define | FDCAN_IE_RF0NE (1 << 0) |
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#define | FDCAN_IE_RF0FE (1 << 1) |
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#define | FDCAN_IE_RF0LE (1 << 2) |
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#define | FDCAN_IE_RF1NE (1 << 3) |
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#define | FDCAN_IE_RF1FE (1 << 4) |
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#define | FDCAN_IE_RF1LE (1 << 5) |
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#define | FDCAN_IE_HPME (1 << 6) |
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#define | FDCAN_IE_TCE (1 << 7) |
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#define | FDCAN_IE_TCFE (1 << 8) |
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#define | FDCAN_IE_TFEE (1 << 9) |
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#define | FDCAN_IE_TEFNE (1 << 10) |
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#define | FDCAN_IE_TEFFE (1 << 11) |
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#define | FDCAN_IE_TEFLE (1 << 12) |
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#define | FDCAN_IE_TSWE (1 << 13) |
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#define | FDCAN_IE_MRAFE (1 << 14) |
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#define | FDCAN_IE_TOOE (1 << 15) |
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#define | FDCAN_IE_ELOE (1 << 16) |
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#define | FDCAN_IE_EPE (1 << 17) |
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#define | FDCAN_IE_EWE (1 << 18) |
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#define | FDCAN_IE_BOE (1 << 19) |
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#define | FDCAN_IE_WDIE (1 << 20) |
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#define | FDCAN_IE_PEAE (1 << 21) |
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#define | FDCAN_IE_PEDE (1 << 22) |
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#define | FDCAN_IE_ARAE (1 << 23) |
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#define | FDCAN_ILS_RxFIFO0 (1 << 0) |
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#define | FDCAN_ILS_RxFIFO1 (1 << 1) |
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#define | FDCAN_ILS_SMSG (1 << 2) |
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#define | FDCAN_ILS_TFERR (1 << 3) |
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#define | FDCAN_ILS_MISC (1 << 4) |
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#define | FDCAN_ILS_BERR (1 << 5) |
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#define | FDCAN_ILS_PERR (1 << 6) |
|
#define | FDCAN_ILE_INT0 (1 << 0) |
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#define | FDCAN_ILE_INT1 (1 << 1) |
|
#define | FDCAN_XIDAM_EIDM_SHIFT 0 |
| EIDM[28:0]: Extended ID mask for filtering. More...
|
|
#define | FDCAN_XIDAM_EIDM_MASK 0x1FFFFFFF |
|
#define | FDCAN_HPMS_BIDX_SHIFT 0 |
| BIDX[2:0]: Buffer index. More...
|
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#define | FDCAN_HPMS_BIDX_MASK 0x7 |
|
#define | FDCAN_HPMS_MSI_SHIFT 6 |
| MSI[1:0]: Message storage indicator. More...
|
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#define | FDCAN_HPMS_MSI_MASK 0x3 |
|
#define | FDCAN_HPMS_FIDX_SHIFT 8 |
| FIDX[4:0]: Filter index. More...
|
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#define | FDCAN_HPMS_FIDX_MASK 0x1F |
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#define | FDCAN_HPMS_FLS (1 << 15) |
|
#define | FDCAN_RXFIFO_FL_SHIFT 0 |
| Fill level of Rx FIFOs. More...
|
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#define | FDCAN_RXFIFO_GI_SHIFT 8 |
| Get index of Rx FIFOs. More...
|
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#define | FDCAN_RXFIFO_PI_SHIFT 16 |
| Put index of Rx FIFOs. More...
|
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#define | FDCAN_RXFIFO_FF (1 << 24) |
|
#define | FDCAN_RXFIFO_RFL (1 << 25) |
|
#define | FDCAN_RXF0S_F0FL_SHIFT FDCAN_RXFIFO_FL_SHIFT |
| F0FL[3:0]: Fill level of Rx FIFO 0. More...
|
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#define | FDCAN_RXF0S_F0FL_MASK FDCAN_RXFIFO_FL_MASK |
|
#define | FDCAN_RXF0S_F0GI_SHIFT FDCAN_RXFIFO_GI_SHIFT |
| F0GI[1:0]: Get index of Rx FIFO 0. More...
|
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#define | FDCAN_RXF0S_F0GI_MASK FDCAN_RXFIFO_GI_MASK |
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#define | FDCAN_RXF0S_F0PI_SHIFT FDCAN_RXFIFO_PI_SHIFT |
| F0PI[1:0]: Put index of Rx FIFO 0. More...
|
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#define | FDCAN_RXF0S_F0PI_MASK FDCAN_RXFIFO_PI_MASK |
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#define | FDCAN_RXF0S_F0F FDCAN_RXFIFO_FF |
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#define | FDCAN_RXF0S_RF0L FDCAN_RXFIFO_RFL |
|
#define | FDCAN_RXFIFO_AI_SHIFT 0 |
| Rx FIFOs acknowledge index. More...
|
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#define | FDCAN_RXF0A_R0AI_SHIFT FDCAN_RXFIFO_AI_SHIFT |
| R0AI[2:0]: Rx FIFO 0 acknowledge index. More...
|
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#define | FDCAN_RXF0A_R0AI_MASK FDCAN_RXFIFO_AI_MASK |
|
#define | FDCAN_RXF1S_F1FL_SHIFT FDCAN_RXFIFO_FL_SHIFT |
| F1FL[3:1]: Fill level of Rx FIFO 1. More...
|
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#define | FDCAN_RXF1S_F1FL_MASK FDCAN_RXFIFO_FL_MASK |
|
#define | FDCAN_RXF1S_F1GI_SHIFT FDCAN_RXFIFO_GI_SHIFT |
| F1GI[1:1]: Get index of Rx FIFO 1. More...
|
|
#define | FDCAN_RXF1S_F1GI_MASK FDCAN_RXFIFO_GI_MASK |
|
#define | FDCAN_RXF1S_F1PI_SHIFT FDCAN_RXFIFO_PI_SHIFT |
| F1PI[1:1]: Put index of Rx FIFO 1. More...
|
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#define | FDCAN_RXF1S_F1PI_MASK FDCAN_RXFIFO_PI_MASK |
|
#define | FDCAN_RXF1S_F1F FDCAN_RXFIFO_FF |
|
#define | FDCAN_RXF1S_RF1L FDCAN_RXFIFO_RFL |
|
#define | FDCAN_RXF1A_R1AI_SHIFT FDCAN_RXFIFO_AI_SHIFT |
| R1AI[2:0]: Rx FIFO 1 acknowledge index. More...
|
|
#define | FDCAN_RXF1A_R1AI_MASK FDCAN_RXFIFO_AI_MASK |
|
#define | FDCAN_TXBC_TFQM (1 << 24) |
|
#define | FDCAN_TXFQS_TFFL_SHIFT 0 |
| TFFL[2:0]: Tx FIFO free level. More...
|
|
#define | FDCAN_TXFQS_TFGI_SHIFT 8 |
| TFGI[1:0]: Tx FIFO get index. More...
|
|
#define | FDCAN_TXFQS_TFQPI_SHIFT 16 |
| TFQPI[1:0]: Tx FIFO put index. More...
|
|
#define | FDCAN_TXFQS_TFQF (1 << 21) |
|
#define | FDCAN_TXBRP_TRP0 (1 << 0) |
|
#define | FDCAN_TXBRP_TRP1 (1 << 1) |
|
#define | FDCAN_TXBRP_TRP2 (1 << 2) |
|
#define | FDCAN_TXBAR_AR0 (1 << 0) |
|
#define | FDCAN_TXBAR_AR1 (1 << 1) |
|
#define | FDCAN_TXBAR_AR2 (1 << 2) |
|
#define | FDCAN_TXBCR_CR0 (1 << 0) |
|
#define | FDCAN_TXBCR_CR1 (1 << 1) |
|
#define | FDCAN_TXBCR_CR2 (1 << 2) |
|
#define | FDCAN_TXBTO_TO0 (1 << 0) |
|
#define | FDCAN_TXBTO_TO1 (1 << 1) |
|
#define | FDCAN_TXBTO_TO2 (1 << 2) |
|
#define | FDCAN_TXBCF_CF0 (1 << 0) |
|
#define | FDCAN_TXBCF_CF1 (1 << 1) |
|
#define | FDCAN_TXBCF_CF2 (1 << 2) |
|
#define | FDCAN_TXBTIE_TIE0 (1 << 0) |
|
#define | FDCAN_TXBTIE_TIE1 (1 << 1) |
|
#define | FDCAN_TXBTIE_TIE2 (1 << 2) |
|
#define | FDCAN_TXBCIE_CFIE0 (1 << 0) |
|
#define | FDCAN_TXBCIE_CFIE1 (1 << 1) |
|
#define | FDCAN_TXBCIE_CFIE2 (1 << 2) |
|
#define | FDCAN_TXEFS_EFFL_SHIFT 0 |
| EFFL[2:0]: Event FIFO fill level. More...
|
|
#define | FDCAN_TXEFS_EFGI_SHIFT 8 |
| EFG[1:0]: Event FIFO get index. More...
|
|
#define | FDCAN_TXEFS_EFPI_SHIFT 16 |
| EFPI[1:0]: Event FIFO put index. More...
|
|
#define | FDCAN_TXEFS_EFF (1 << 24) |
|
#define | FDCAN_TXEFS_TEF (1 << 25) |
|
#define | FDCAN_TXEFA_EFAI_SHIFT 0 |
| EFAI[1:0]: Event FIFO acknowledge index. More...
|
|
#define | FDCAN_TXEFA_EFAI_MASK 0x3 |
|
#define | FDCAN_SFT_SHIFT 30 |
|
#define | FDCAN_SFT_MASK 0x3 |
|
#define | FDCAN_SFT_RANGE 0x0 |
| Filter matches all messages in range from id1 to id2. More...
|
|
#define | FDCAN_SFT_DUAL 0x1 |
| Filter matches messages with id1 or id2. More...
|
|
#define | FDCAN_SFT_ID_MASK 0x2 |
| Filter matches messages which match id1 after being unmasked using id2. More...
|
|
#define | FDCAN_SFT_DISABLE 0x3 |
| Disable this filter. More...
|
|
#define | FDCAN_SFEC_SHIFT 27 |
|
#define | FDCAN_SFEC_MASK 0x7 |
|
#define | FDCAN_SFEC_DISABLE 0x0 |
| Filter is disabled. More...
|
|
#define | FDCAN_SFEC_FIFO0 0x1 |
| Put message into FIFO0. More...
|
|
#define | FDCAN_SFEC_FIFO1 0x2 |
| Put message into FIFO1. More...
|
|
#define | FDCAN_SFEC_REJECT 0x3 |
| Reject message. More...
|
|
#define | FDCAN_SFEC_PRIO 0x4 |
| Treat message as priority message (and continue processing further rules) More...
|
|
#define | FDCAN_SFEC_PRIO_FIFO0 0x5 |
| Treat message as priority and put it into FIFO0. More...
|
|
#define | FDCAN_SFEC_PRIO_FIFO1 0x6 |
| Treat message as priority and put it into FIFO1. More...
|
|
#define | FDCAN_SFID1_SHIFT 16 |
|
#define | FDCAN_SFID1_MASK 0x7FF |
|
#define | FDCAN_SFID2_SHIFT 0 |
|
#define | FDCAN_SFID2_MASK 0x7FF |
|
#define | FDCAN_EFEC_SHIFT 29 |
|
#define | FDCAN_EFEC_MASK 0x7 |
|
#define | FDCAN_EFEC_DISABLE 0x0 |
| Disable this filter. More...
|
|
#define | FDCAN_EFEC_FIFO0 0x1 |
| Put message into FIFO0. More...
|
|
#define | FDCAN_EFEC_FIFO1 0x2 |
| Put message into FIFO1. More...
|
|
#define | FDCAN_EFEC_REJECT 0x3 |
| Reject message. More...
|
|
#define | FDCAN_EFEC_PRIO 0x4 |
| Treat message as priority message (and continue processing further rules) More...
|
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#define | FDCAN_EFEC_PRIO_FIFO0 0x5 |
| Treat message as priority and put it into FIFO0. More...
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#define | FDCAN_EFEC_PRIO_FIFO1 0x6 |
| Treat message as priority and put it into FIFO1. More...
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#define | FDCAN_EFID1_SHIFT 0 |
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#define | FDCAN_EFID1_MASK 0x1FFFFFFF |
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#define | FDCAN_EFT_SHIFT 30 |
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#define | FDCAN_EFT_MASK 0x3 |
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#define | FDCAN_EFT_RANGE 0x0 |
| Filter matches all messages in range from id1 to id2. More...
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#define | FDCAN_EFT_DUAL 0x1 |
| Filter matches messages with id1 or id2. More...
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#define | FDCAN_EFT_ID_MASK 0x2 |
| Filter matches messages which match id1 after being unmasked using id2. More...
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#define | FDCAN_EFT_RANGE_NOXIDAM 0x3 |
| Similar to FDCAN_EFT_RANGE except of ignoring global mask set using FDCAN_XIDAM register. More...
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#define | FDCAN_EFID2_SHIFT 0 |
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#define | FDCAN_EFID2_MASK 0x1FFFFFFF |
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#define | FDCAN_FIFO_ESI (1 << 31) |
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#define | FDCAN_FIFO_XTD (1 << 30) |
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#define | FDCAN_FIFO_RTR (1 << 29) |
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#define | FDCAN_FIFO_EFC (1 << 23) |
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#define | FDCAN_FIFO_FDF (1 << 21) |
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#define | FDCAN_FIFO_BRS (1 << 20) |
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#define | FDCAN_FIFO_EID_SHIFT 0 |
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#define | FDCAN_FIFO_EID_MASK 0x1FFFFFFF |
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#define | FDCAN_FIFO_SID_SHIFT 18 |
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#define | FDCAN_FIFO_SID_MASK 0x7FF |
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#define | FDCAN_FIFO_DLC_SHIFT 16 |
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#define | FDCAN_FIFO_DLC_MASK 0xF |
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#define | FDCAN_FIFO_MM_SHIFT 24 |
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#define | FDCAN_FIFO_MM_MASK 0xFF |
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#define | FDCAN_FIFO_ANMF (1 << 31) |
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#define | FDCAN_FIFO_FIDX_SHIFT 24 |
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#define | FDCAN_FIFO_FIDX_MASK 0x7F |
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#define | FDCAN_FIFO_RXTS_SHIFT 0 |
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#define | FDCAN_FIFO_RXTS_MASK 0xFFFF |
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#define | FDCAN_E_OK 0 |
| No error. More...
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#define | FDCAN_E_OUTOFRANGE -1 |
| Value provided was out of range. More...
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#define | FDCAN_E_TIMEOUT -2 |
| Timeout waiting for FDCAN block to accept INIT bit change. More...
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#define | FDCAN_E_INVALID -3 |
| Value provided was invalid (FIFO index, FDCAN block base address, length, etc.) More...
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#define | FDCAN_E_BUSY -4 |
| Device is busy: Transmit buffer is full, unable to queue additional message or device is outside of INIT mode and cannot perform desired operation. More...
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#define | FDCAN_E_NOTAVAIL -5 |
| Receive buffer is empty, unable to read any new message. More...
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