#include <libopencm3/stm32/common/adc_common_v2.h>
#include <libopencm3/stm32/common/adc_common_v2_multi.h>

Include dependency graph for g4/adc.h:

Macros
#define	ADC1 ADC1_BASE

#define	ADC2 ADC2_BASE

#define	ADC3 ADC3_BASE

#define	ADC4 ADC4_BASE

#define	ADC5 ADC5_BASE

#define	ADC_GCOMP(adc) MMIO32((adc) + 0xC0)
	ADC_GCOMP Gain compensation Register. More...

#define	ADC_CR_DEEPPWD (1 << 29)

#define	ADC_CR_ADVREGEN (1 << 28)
	ADVREGEN: ADC voltage regulator enable bit. More...

#define	ADC_CFGR1_ALIGN (1 << 15)
	ALIGN: Data alignment. More...

#define	ADC_CFGR1_EXTSEL_SHIFT 5
	EXTSEL[4:0]: External trigger selection for regular group. More...

#define	ADC_CFGR1_EXTSEL_MASK (0x1f << ADC_CFGR1_EXTSEL_SHIFT)

#define	ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)

#define	ADC12_CFGR1_EXTSEL_TIM1_CC1 ADC_CFGR1_EXTSEL_VAL(0)
	CFGR1: ADC configuration register. More...

#define	ADC12_CFGR1_EXTSEL_TIM1_CC2 ADC_CFGR1_EXTSEL_VAL(1)

#define	ADC12_CFGR1_EXTSEL_TIM1_CC3 ADC_CFGR1_EXTSEL_VAL(2)

#define	ADC12_CFGR1_EXTSEL_TIM2_CC2 ADC_CFGR1_EXTSEL_VAL(3)

#define	ADC12_CFGR1_EXTSEL_TIM3_TRGO ADC_CFGR1_EXTSEL_VAL(4)

#define	ADC12_CFGR1_EXTSEL_TIM4_CC4 ADC_CFGR1_EXTSEL_VAL(5)

#define	ADC12_CFGR1_EXTSEL_EXTI11 ADC_CFGR1_EXTSEL_VAL(6)

#define	ADC12_CFGR1_EXTSEL_TIM8_TRGO ADC_CFGR1_EXTSEL_VAL(7)

#define	ADC12_CFGR1_EXTSEL_TIM8_TRGO2 ADC_CFGR1_EXTSEL_VAL(8)

#define	ADC12_CFGR1_EXTSEL_TIM1_TRGO ADC_CFGR1_EXTSEL_VAL(9)

#define	ADC12_CFGR1_EXTSEL_TIM1_TRGO2 ADC_CFGR1_EXTSEL_VAL(10)

#define	ADC12_CFGR1_EXTSEL_TIM2_TRGO ADC_CFGR1_EXTSEL_VAL(11)

#define	ADC12_CFGR1_EXTSEL_TIM4_TRGO ADC_CFGR1_EXTSEL_VAL(12)

#define	ADC12_CFGR1_EXTSEL_TIM6_TRGO ADC_CFGR1_EXTSEL_VAL(13)

#define	ADC12_CFGR1_EXTSEL_TIM15_TRGO ADC_CFGR1_EXTSEL_VAL(14)

#define	ADC12_CFGR1_EXTSEL_TIM3_CC4 ADC_CFGR1_EXTSEL_VAL(15)

#define	ADC12_CFGR1_EXTSEL_TIM20_TRGO ADC_CFGR1_EXTSEL_VAL(16)

#define	ADC12_CFGR1_EXTSEL_TIM20_TRGO2 ADC_CFGR1_EXTSEL_VAL(17)

#define	ADC12_CFGR1_EXTSEL_TIM20_CC1 ADC_CFGR1_EXTSEL_VAL(18)

#define	ADC12_CFGR1_EXTSEL_TIM20_CC2 ADC_CFGR1_EXTSEL_VAL(19)

#define	ADC12_CFGR1_EXTSEL_TIM20_CC3 ADC_CFGR1_EXTSEL_VAL(20)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG1 ADC_CFGR1_EXTSEL_VAL(21)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG3 ADC_CFGR1_EXTSEL_VAL(22)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG5 ADC_CFGR1_EXTSEL_VAL(23)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG6 ADC_CFGR1_EXTSEL_VAL(24)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG7 ADC_CFGR1_EXTSEL_VAL(25)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG8 ADC_CFGR1_EXTSEL_VAL(26)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG9 ADC_CFGR1_EXTSEL_VAL(27)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG10 ADC_CFGR1_EXTSEL_VAL(28)

#define	ADC12_CFGR1_EXTSEL_LPTIMOUT ADC_CFGR1_EXTSEL_VAL(29)

#define	ADC12_CFGR1_EXTSEL_TIM7_TRGO ADC_CFGR1_EXTSEL_VAL(30)

#define	ADC345_CFGR1_EXTSEL_TIM3_CC1 ADC_CFGR1_EXTSEL_VAL(0)

#define	ADC345_CFGR1_EXTSEL_TIM2_CC3 ADC_CFGR1_EXTSEL_VAL(1)

#define	ADC345_CFGR1_EXTSEL_TIM1_CC3 ADC_CFGR1_EXTSEL_VAL(2)

#define	ADC345_CFGR1_EXTSEL_TIM8_CC1 ADC_CFGR1_EXTSEL_VAL(3)

#define	ADC345_CFGR1_EXTSEL_TIM3_TRGO ADC_CFGR1_EXTSEL_VAL(4)

#define	ADC345_CFGR1_EXTSEL_EXTI2 ADC_CFGR1_EXTSEL_VAL(5)

#define	ADC345_CFGR1_EXTSEL_TIM4_CC1 ADC_CFGR1_EXTSEL_VAL(6)

#define	ADC345_CFGR1_EXTSEL_TIM8_TRGO ADC_CFGR1_EXTSEL_VAL(7)

#define	ADC345_CFGR1_EXTSEL_TIM8_TRGO2 ADC_CFGR1_EXTSEL_VAL(8)

#define	ADC345_CFGR1_EXTSEL_TIM1_TRGO ADC_CFGR1_EXTSEL_VAL(9)

#define	ADC345_CFGR1_EXTSEL_TIM1_TRGO2 ADC_CFGR1_EXTSEL_VAL(10)

#define	ADC345_CFGR1_EXTSEL_TIM2_TRGO ADC_CFGR1_EXTSEL_VAL(11)

#define	ADC345_CFGR1_EXTSEL_TIM4_TRGO ADC_CFGR1_EXTSEL_VAL(12)

#define	ADC345_CFGR1_EXTSEL_TIM6_TRGO ADC_CFGR1_EXTSEL_VAL(13)

#define	ADC345_CFGR1_EXTSEL_TIM15_TRGO ADC_CFGR1_EXTSEL_VAL(14)

#define	ADC345_CFGR1_EXTSEL_TIM2_CC1 ADC_CFGR1_EXTSEL_VAL(15)

#define	ADC345_CFGR1_EXTSEL_TIM20_TRGO ADC_CFGR1_EXTSEL_VAL(16)

#define	ADC345_CFGR1_EXTSEL_TIM20_TRGO2 ADC_CFGR1_EXTSEL_VAL(17)

#define	ADC345_CFGR1_EXTSEL_TIM20_CC1 ADC_CFGR1_EXTSEL_VAL(18)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG2 ADC_CFGR1_EXTSEL_VAL(19)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG4 ADC_CFGR1_EXTSEL_VAL(20)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG1 ADC_CFGR1_EXTSEL_VAL(21)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG3 ADC_CFGR1_EXTSEL_VAL(22)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG5 ADC_CFGR1_EXTSEL_VAL(23)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG6 ADC_CFGR1_EXTSEL_VAL(24)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG7 ADC_CFGR1_EXTSEL_VAL(25)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG8 ADC_CFGR1_EXTSEL_VAL(26)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG9 ADC_CFGR1_EXTSEL_VAL(27)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG10 ADC_CFGR1_EXTSEL_VAL(28)

#define	ADC345_CFGR1_EXTSEL_LPTIMOUT ADC_CFGR1_EXTSEL_VAL(29)

#define	ADC345_CFGR1_EXTSEL_TIM7_TRGO ADC_CFGR1_EXTSEL_VAL(30)

#define	ADC_CFGR2_ROVSE (1 << 0)
	ROVSE: Regular Oversampling Enable. More...

#define	ADC_CFGR2_JOVSE (1 << 1)
	JOVSE: Injected Oversampling Enable. More...

#define	ADC_CFGR2_OVSR_SHIFT 2
	OVSR[2:0]: Oversampling ratio. More...

#define	ADC_CFGR2_OVSR_MASK (0x7 << ADC_CFGR2_OVSR_SHIFT)

#define	ADC_CFGR2_OVSR_VAL(x) ((x) << ADC_CFGR2_OVSR_SHIFT)

#define	ADC_CFGR2_OVSR_2x ADC_CFGR2_OVSR_VAL(0)

#define	ADC_CFGR2_OVSR_4x ADC_CFGR2_OVSR_VAL(1)

#define	ADC_CFGR2_OVSR_8x ADC_CFGR2_OVSR_VAL(2)

#define	ADC_CFGR2_OVSR_16x ADC_CFGR2_OVSR_VAL(3)

#define	ADC_CFGR2_OVSR_32x ADC_CFGR2_OVSR_VAL(4)

#define	ADC_CFGR2_OVSR_64x ADC_CFGR2_OVSR_VAL(5)

#define	ADC_CFGR2_OVSR_128x ADC_CFGR2_OVSR_VAL(6)

#define	ADC_CFGR2_OVSR_256x ADC_CFGR2_OVSR_VAL(7)

#define	ADC_CFGR2_OVSS_SHIFT 5
	OVSS[3:0]: Oversampling shift. More...

#define	ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT)

#define	ADC_CFGR2_OVSS_VAL(x) ((x) << ADC_CFGR2_OVSS_SHIFT)

#define	ADC_CFGR2_TROVS (1 << 9)
	TROVS: Triggered Regular Oversampling. More...

#define	ADC_CFGR2_ROVSM (1 << 10)
	ROVSM: Regular Oversampling mode. More...

#define	ADC_CFGR2_GCOMP (1 << 16)
	GCOMP: Gain compensation mode. More...

#define	ADC_CFGR2_SWTRIG (1 << 25)
	SWTRIG: Software trigger bit for sampling time control trigger mode. More...

#define	ADC_CFGR2_BULB (1 << 26)
	BULB: Bulb sampling mode. More...

#define	ADC_CFGR2_SMPTRIG (1 << 27)
	SMPTRIG: Sampling time control trigger mode. More...

#define	ADC_SMPR_SMP_2DOT5CYC 0x0

#define	ADC_SMPR_SMP_6DOT5CYC 0x1

#define	ADC_SMPR_SMP_12DOT5CYC 0x2

#define	ADC_SMPR_SMP_24DOT5CYC 0x3

#define	ADC_SMPR_SMP_47DOT5CYC 0x4

#define	ADC_SMPR_SMP_92DOT5CYC 0x5

#define	ADC_SMPR_SMP_247DOT5CYC 0x6

#define	ADC_SMPR_SMP_640DOT5CYC 0x7

#define	ADC_SMPR1_SMP_PLUSONE (1 << 31)

#define	ADC_JSQR_JL_LSB 0

#define	ADC_JSQR_JL_SHIFT 0

#define	ADC_JSQR_JSQ4_LSB 27

#define	ADC_JSQR_JSQ3_LSB 21

#define	ADC_JSQR_JSQ2_LSB 15

#define	ADC_JSQR_JSQ1_LSB 9

#define	ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 6 + 8))

#define	ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)

#define	ADC_JSQR_JEXTEN_DISABLED (0x0 << 7)

#define	ADC_JSQR_JEXTEN_RISING_EDGE (0x1 << 7)

#define	ADC_JSQR_JEXTEN_FALLING_EDGE (0x2 << 7)

#define	ADC_JSQR_JEXTEN_BOTH_EDGES (0x3 << 7)

#define	ADC_JSQR_JEXTEN_MASK (0x3 << 7)

#define	ADC_JSQR_JEXTSEL_SHIFT 2

#define	ADC12_JSQR_JEXTSEL_TIM1_TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM1_CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM2_TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM2_CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM3_CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM4_TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM8_CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM1_TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM8_TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM8_TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM3_CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM3_TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM3_CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM6_TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM15_TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM20_TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM20_TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM20_CC4 (18 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM16_CC1 (27 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM7_TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM1_TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM1_CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM2_TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM8_CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM4_CC3 (4 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM4_TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM4_CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM8_CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM1_TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM8_TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM8_TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM1_CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM3_TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_EXTI3 (13 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM6_TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM15_TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM20_TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM20_TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM20_CC2 (18 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG1 (27 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG3 (28 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM7_TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC_JSQR_JEXTSEL_MASK (0x1F << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC_JSQR_JL_1_CONVERSION (0x0 << 0)

#define	ADC_JSQR_JL_2_CONVERSIONS (0x1 << 0)

#define	ADC_JSQR_JL_3_CONVERSIONS (0x2 << 0)

#define	ADC_JSQR_JL_4_CONVERSIONS (0x3 << 0)

#define	ADC_OFR1_OFFSET1_EN (1 << 31)

#define	ADC_OFR2_OFFSET2_EN (1 << 31)

#define	ADC_OFR3_OFFSET3_EN (1 << 31)

#define	ADC_OFR4_OFFSET4_EN (1 << 31)

#define	ADC_CSR_JQOVF_SLV (1 << 26)

#define	ADC_CSR_AWD3_SLV (1 << 25)

#define	ADC_CSR_AWD2_SLV (1 << 24)

#define	ADC_CSR_AWD1_SLV (1 << 23)

#define	ADC_CSR_JEOS_SLV (1 << 22)

#define	ADC_CSR_JEOC_SLV (1 << 21)

#define	ADC_CSR_OVR_SLV (1 << 20)

#define	ADC_CSR_EOS_SLV (1 << 19)

#define	ADC_CSR_EOC_SLV (1 << 18)

#define	ADC_CSR_EOSMP_SLV (1 << 17)

#define	ADC_CSR_ADRDY_SLV (1 << 16)

#define	ADC_CSR_JQOVF_MST (1 << 10)

#define	ADC_CSR_AWD3_MST (1 << 9)

#define	ADC_CSR_AWD2_MST (1 << 8)

#define	ADC_CSR_AWD1_MST (1 << 7)

#define	ADC_CSR_JEOS_MST (1 << 6)

#define	ADC_CSR_JEOC_MST (1 << 5)

#define	ADC_CSR_OVR_MST (1 << 4)

#define	ADC_CSR_EOS_MST (1 << 3)

#define	ADC_CSR_EOC_MST (1 << 2)

#define	ADC_CSR_EOSMP_MST (1 << 1)

#define	ADC_CSR_ADRDY_MST (1 << 0)

#define	ADC_CCR_PRESC_MASK (0xf)

#define	ADC_CCR_PRESC_SHIFT (18)

#define	ADC_CCR_PRESC_NODIV (0x0)

#define	ADC_CCR_PRESC_DIV2 (0x1)

#define	ADC_CCR_PRESC_DIV4 (0x2)

#define	ADC_CCR_PRESC_DIV6 (0x3)

#define	ADC_CCR_PRESC_DIV8 (0x4)

#define	ADC_CCR_PRESC_DIV10 (0x5)

#define	ADC_CCR_PRESC_DIV12 (0x6)

#define	ADC_CCR_PRESC_DIV16 (0x7)

#define	ADC_CCR_PRESC_DIV32 (0x8)

#define	ADC_CCR_PRESC_DIV64 (0x9)

#define	ADC_CCR_PRESC_DIV128 (0xa)

#define	ADC_CCR_PRESC_DIV256 (0xb)

#define	ADC_CCR_CKMODE_CKX (0x0 << 16)

#define	ADC_CCR_CKMODE_DIV1 (0x1 << 16)

#define	ADC_CCR_CKMODE_DIV2 (0x2 << 16)

#define	ADC_CCR_CKMODE_DIV4 (0x3 << 16)

#define	ADC_CCR_CKMODE_MASK (0x3 << 16)

#define	ADC_CCR_MDMA_DISABLE (0x0 << 14)

#define	ADC_CCR_MDMA_12_10_BIT (0x2 << 14)

#define	ADC_CCR_MDMA_8_6_BIT (0x3 << 14)

#define	ADC_CCR_DMACFG (1 << 13)

#define	ADC_CCR_DELAY_SHIFT 8

#define	ADC_CCR_DUAL_INDEPENDENT 0x0
	All ADCs independent. More...

#define	ADC_CCR_DUAL_REG_SIMUL_AND_INJECTED_SIMUL 0x1
	Dual modes combined regular simultaneous + injected simultaneous mode. More...

#define	ADC_CCR_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG 0x2
	Dual mode Combined regular simultaneous + alternate trigger mode. More...

#define	ADC_CCR_DUAL_REG_INTERLEAVED_AND_INJECTED_SIMUL 0x3
	Dual mode Combined interleaved mode + injected simultaneous mode. More...

#define	ADC_CCR_DUAL_INJECTED_SIMUL 0x5
	Dual mode Injected simultaneous mode only. More...

#define	ADC_CCR_DUAL_REGULAR_SIMUL 0x6
	Dual mode Regular simultaneous mode only. More...

#define	ADC_CCR_DUAL_INTERLEAVED 0x7
	Dual mode Interleaved mode only. More...

#define	ADC_CCR_DUAL_ALTERNATE_TRIG 0x9
	Dual mode Alternate trigger mode only. More...

#define	ADC_CCR_DUAL_MASK (0x1f)

#define	ADC_CCR_DUAL_SHIFT 0

#define	ADC_CHANNEL_TEMP 16

#define	ADC_CHANNEL_VBAT 17

#define	ADC_CHANNEL_VREF 18

#define	ADC_CHANNEL_COUNT 19

#define	ADC_CHANNEL_IS_FAST(x) ((x) <= 5)

Functions
void	adc_enable_analog_watchdog_regular (uint32_t adc)
	ADC Enable Analog Watchdog for Regular Conversions. More...

void	adc_disable_analog_watchdog_regular (uint32_t adc)
	ADC Enable Analog Watchdog for Regular Conversions. More...

void	adc_enable_analog_watchdog_injected (uint32_t adc)
	ADC Enable Analog Watchdog for Injected Conversions. More...

void	adc_disable_analog_watchdog_injected (uint32_t adc)
	ADC Disable Analog Watchdog for Injected Conversions. More...

void	adc_enable_discontinuous_mode_regular (uint32_t adc, uint8_t length)
	ADC Enable Discontinuous Mode for Regular Conversions. More...

void	adc_disable_discontinuous_mode_regular (uint32_t adc)
	ADC Disable Discontinuous Mode for Regular Conversions. More...

void	adc_enable_discontinuous_mode_injected (uint32_t adc)
	ADC Enable Discontinuous Mode for Injected Conversions. More...

void	adc_disable_discontinuous_mode_injected (uint32_t adc)
	ADC Disable Discontinuous Mode for Injected Conversions. More...

void	adc_enable_automatic_injected_group_conversion (uint32_t adc)
	ADC Enable Automatic Injected Conversions. More...

void	adc_disable_automatic_injected_group_conversion (uint32_t adc)
	ADC Disable Automatic Injected Conversions. More...

void	adc_enable_analog_watchdog_on_all_channels (uint32_t adc)
	ADC Enable Analog Watchdog for All Regular and/or Injected Channels. More...

void	adc_enable_analog_watchdog_on_selected_channel (uint32_t adc, uint8_t channel)
	ADC Enable Analog Watchdog for a Selected Channel. More...

void	adc_enable_eoc_interrupt_injected (uint32_t adc)
	ADC Enable Injected End-Of-Conversion Interrupt. More...

void	adc_disable_eoc_interrupt_injected (uint32_t adc)
	ADC Disable Injected End-Of-Conversion Interrupt. More...

void	adc_enable_eos_interrupt_injected (uint32_t adc)
	ADC Enable Injected End-Of-Sequence Interrupt. More...

void	adc_disable_eos_interrupt_injected (uint32_t adc)
	ADC Disable Injected End-Of-Sequence Interrupt. More...

void	adc_enable_all_awd_interrupt (uint32_t adc)
	ADC Enable Analog Watchdog Interrupt. More...

void	adc_disable_all_awd_interrupt (uint32_t adc)
	ADC Disable Analog Watchdog Interrupt. More...

void	adc_enable_eos_interrupt (uint32_t adc)
	ADC Enable Regular End-Of-Sequence Interrupt. More...

void	adc_disable_eos_interrupt (uint32_t adc)
	ADC Disable Regular End-Of-Sequence Interrupt. More...

void	adc_start_conversion_injected (uint32_t adc)
	ADC Software Triggered Conversion on Injected Channels. More...

void	adc_disable_external_trigger_regular (uint32_t adc)
	ADC Disable an External Trigger for Regular Channels. More...

void	adc_disable_external_trigger_injected (uint32_t adc)
	ADC Disable an External Trigger for Injected Channels. More...

void	adc_set_watchdog_high_threshold (uint32_t adc, uint16_t threshold)
	ADC Set Analog Watchdog Upper Threshold. More...

void	adc_set_watchdog_low_threshold (uint32_t adc, uint16_t threshold)
	ADC Set Analog Watchdog Lower Threshold. More...

void	adc_set_injected_sequence (uint32_t adc, uint8_t length, uint8_t channel[])
	ADC Set an Injected Channel Conversion Sequence. More...

bool	adc_eoc_injected (uint32_t adc)
	ADC Read the End-of-Conversion Flag for Injected Conversion. More...

bool	adc_eos_injected (uint32_t adc)
	ADC Read the End-of-Sequence Flag for Injected Conversions. More...

uint32_t	adc_read_injected (uint32_t adc, uint8_t reg)
	ADC Read from an Injected Conversion Result Register. More...

void	adc_set_injected_offset (uint32_t adc, uint8_t reg, uint32_t offset)
	ADC Set the Injected Channel Data Offset. More...

void	adc_set_clk_source (uint32_t adc, uint32_t source)
	ADC Set Clock Source. More...

void	adc_set_clk_prescale (uint32_t adc, uint32_t prescale)
	ADC Set Clock Prescale. More...

void	adc_set_multi_mode (uint32_t adc, uint32_t mode)
	ADC set multi mode. More...

void	adc_enable_external_trigger_regular (uint32_t adc, uint32_t trigger, uint32_t polarity)
	ADC Enable an External Trigger for Regular Channels. More...

void	adc_enable_external_trigger_injected (uint32_t adc, uint32_t trigger, uint32_t polarity)
	ADC Enable an External Trigger for Injected Channels. More...

bool	adc_awd (uint32_t adc)
	ADC Read the Analog Watchdog Flag. More...

void	adc_enable_deeppwd (uint32_t adc)
	ADC Enable Deep-Power-Down Mdoe. More...

void	adc_disable_deeppwd (uint32_t adc)
	ADC Disable Deep-Power-Down Mdoe. More...

Macros

Functions