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Macros
#define	PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)

#define	PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04)

#define	PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08)

#define	PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0C)

#define	PWR_CR5 MMIO32(POWER_CONTROL_BASE + 0x80)

#define	PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10)

#define	PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14)

#define	PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18)

#define	PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20)

#define	PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28)

#define	PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30)

#define	PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38)

#define	PWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40)

#define	PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48)

#define	PWR_PORT_G MMIO32(POWER_CONTROL_BASE + 0x50)

#define	PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00)

#define	PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04)

#define	PWR_CR1_LPR (1 << 14)

#define	PWR_CR1_VOS_SHIFT 9

#define	PWR_CR1_VOS_MASK 0x3

#define	PWR_CR1_VOS_RANGE_1 1

#define	PWR_CR1_VOS_RANGE_2 2

#define	PWR_CR1_DBP (1 << 8)

#define	PWR_CR1_LPMS_SHIFT 0

#define	PWR_CR1_LPMS_MASK 0x07

#define	PWR_CR1_LPMS_STOP_0 0

#define	PWR_CR1_LPMS_STOP_1 1

#define	PWR_CR1_LPMS_STOP_2 2

#define	PWR_CR1_LPMS_STANDBY 3

#define	PWR_CR1_LPMS_SHUTDOWN 4

#define	PWR_CR2_PVMEN2 (1 << 7)

#define	PWR_CR2_PVMEN1 (1 << 6)

#define	PWR_CR2_PLS_SHIFT 1

#define	PWR_CR2_PLS_MASK 0x07

#define	PWR_CR2_PLS_2V0 0x00

#define	PWR_CR2_PLS_2V2 0x01

#define	PWR_CR2_PLS_2V4 0x02

#define	PWR_CR2_PLS_2V5 0x03

#define	PWR_CR2_PLS_2V6 0x04

#define	PWR_CR2_PLS_2V8 0x05

#define	PWR_CR2_PLS_2V9 0x06

#define	PWR_CR2_PLS_PVD_IN 0x07

#define	PWR_CR2_PVDE (1 << 0)

#define	PWR_CR3_EIWUL (1 << 15)

#define	PWR_CR3_UCPD1_DBDIS (1 << 14)

#define	PWR_CR3_UCPD1_STDBY (1 << 13)

#define	PWR_CR3_APC (1 << 10)

#define	PWR_CR3_RRS (1 << 8)

#define	PWR_CR3_EWUP5 (1 << 4)

#define	PWR_CR3_EWUP4 (1 << 3)

#define	PWR_CR3_EWUP3 (1 << 2)

#define	PWR_CR3_EWUP2 (1 << 1)

#define	PWR_CR3_EWUP1 (1 << 0)

#define	PWR_CR4_VBRS (1 << 9)

#define	PWR_CR4_VBE (1 << 8)

#define	PWR_CR4_WP5 (1 << 4)

#define	PWR_CR4_WP4 (1 << 3)

#define	PWR_CR4_WP3 (1 << 2)

#define	PWR_CR4_WP2 (1 << 1)

#define	PWR_CR4_WP1 (1 << 0)

#define	PWR_CR5_R1MODE_SHIFT 8

#define	PWR_CR5_R1MODE_MASK 0x1

#define	PWR_CR5_R1MODE_BOOST 0

#define	PWR_CR5_R1MODE_NORMAL 1

#define	PWR_CR5_R1MODE (PWR_CR5_R1MODE_MASK << PWR_CR5_R1MODE_SHIFT)

#define	PWR_SR1_WUFI (1 << 15)

#define	PWR_SR1_SBF (1 << 8)

#define	PWR_SR1_WUF5 (1 << 4)

#define	PWR_SR1_WUF4 (1 << 3)

#define	PWR_SR1_WUF3 (1 << 2)

#define	PWR_SR1_WUF2 (1 << 1)

#define	PWR_SR1_WUF1 (1 << 0)

#define	PWR_SR2_PVMO2 (1 << 15)

#define	PWR_SR2_PVMO1 (1 << 14)

#define	PWR_SR2_PVDO (1 << 11)

#define	PWR_SR2_VOSF (1 << 10)

#define	PWR_SR2_REGLPF (1 << 9)

#define	PWR_SR2_REGLPS (1 << 8)

#define	PWR_SCR_CSBF (1 << 8)

#define	PWR_SCR_CWUF5 (1 << 4)

#define	PWR_SCR_CWUF4 (1 << 3)

#define	PWR_SCR_CWUF3 (1 << 2)

#define	PWR_SCR_CWUF2 (1 << 1)

#define	PWR_SCR_CWUF1 (1 << 0)

Enumerations
enum	pwr_vos_scale { PWR_SCALE1 = PWR_CR1_VOS_RANGE_1 , PWR_SCALE2 = PWR_CR1_VOS_RANGE_2 }

Functions
void	pwr_set_vos_scale (enum pwr_vos_scale scale)

void	pwr_disable_backup_domain_write_protect (void)
	Disable Backup Domain Write Protection. More...

void	pwr_enable_backup_domain_write_protect (void)
	Re-enable Backup Domain Write Protection. More...

void	pwr_set_low_power_mode_selection (uint32_t lpms)
	Select the low power mode used in deep sleep. More...

void	pwr_enable_power_voltage_detect (uint32_t pvd_level)
	Enable Power Voltage Detector. More...

void	pwr_disable_power_voltage_detect (void)
	Disable Power Voltage Detector. More...

void	pwr_enable_boost (void)
	Enable Boost Mode. More...

void	pwr_disable_boost (void)
	Disable Boost Mode. More...

Macros

Enumerations

Functions