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libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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Go to the source code of this file.
Macros | |
| #define | PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00) |
| Power control register. More... | |
| #define | PWR_CSR1 MMIO32(POWER_CONTROL_BASE + 0x04) |
| Power control/status register. More... | |
| #define | PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x08) |
| Power control register 2. More... | |
| #define | PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x0C) |
| Power control register 3. More... | |
| #define | PWR_CPUCR MMIO32(POWER_CONTROL_BASE + 0x10) |
| CPU Power control register 3. More... | |
| #define | PWR_D3CR MMIO32(POWER_CONTROL_BASE + 0x18) |
| D3 Domain Power Control register. More... | |
| #define | PWR_SRDCR MMIO32(POWER_CONTROL_BASE + 0x18) |
| #define | PWR_WKUPCR MMIO32(POWER_CONTROL_BASE + 0x20) |
| Wakeup Domain Power Control register. More... | |
| #define | PWR_CR1_SVOS_SHIFT 14 |
| VOS[15:14]: Regulator voltage scaling output selection. More... | |
| #define | PWR_CR1_SVOS_MASK (0x3) |
| #define | PWR_CR1_SVOS_SCALE_3 (0x3) |
| #define | PWR_CR1_SVOS_SCALE_4 (0x2) |
| #define | PWR_CR1_SVOS_SCALE_5 (0x1) |
| #define | PWR_CR1_SRDRAMSO BIT27 |
| SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode. More... | |
| #define | PWR_CR1_HSITFSO BIT26 |
| high-speed interfaces USB and FDCAN memory shut-off in DStop/DStop2 mode More... | |
| #define | PWR_CR1_GFXSO BIT25 |
| GFXMMU and JPEG memory shut-off in DStop/DStop2 mode. More... | |
| #define | PWR_CR1_ITCMSO BIT24 |
| instruction TCM and ETM memory shut-off in DStop/DStop2 mode More... | |
| #define | PWR_CR1_AHBRAM2SO BIT23 |
| AHB SRAM2 shut-off in DStop/DStop2 mode. More... | |
| #define | PWR_CR1_AHBRAM1SO BIT22 |
| AHB SRAM1 shut-off in DStop/DStop2 mode. More... | |
| #define | PWR_CR1_AXIRAM3SO BIT21 |
| AXI SRAM3 shut-off in DStop/DStop2 mode. More... | |
| #define | PWR_CR1_AXIRAM2SO BIT20 |
| AXI SRAM2 shut-off in DStop/DStop2 mode. More... | |
| #define | PWR_CR1_AXIRAM1SO BIT19 |
| AXI SRAM1 shut-off in DStop/DStop2 mode. More... | |
| #define | PWR_CR1_ALS_SHIFT 17 |
| voltage threshold detected by the AVD. More... | |
| #define | PWR_CR1_ALS_MASK 0x3 |
| #define | PWR_CR1_ALS_1P7V 0x0 |
| #define | PWR_CR1_ALS_2P1V 0x1 |
| #define | PWR_CR1_ALS_2P5V 0x2 |
| #define | PWR_CR1_ALS_2P8V 0x3 |
| #define | PWR_CR1_AVDEN BIT16 |
| peripheral voltage monitor on V DDA enable More... | |
| #define | PWR_CR1_AVD_READY BIT13 |
| analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). More... | |
| #define | PWR_CR1_BOOSTE BIT12 |
| analog switch VBoost control This bit enables the booster to guarantee the analog switch AC performance when the V DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V DD supply voltage can be monitored through the PVD and the PLS bits. More... | |
| #define | PWR_CR1_DBP BIT8 |
| DBP[8]: Disable backup domain write protection. More... | |
| #define | PWR_CSR1_MMCVDO BIT17 |
| CSR1 Register Bits. More... | |
| #define | PWR_CSR1_AVDO BIT16 |
| #define | PWR_CSR1_ACTVOS_SHIFT 14 |
| #define | PWR_CSR1_ACTVOSRDY BIT13 |
| #define | PWR_CSR1_PVDO BIT4 |
| #define | PWR_CR2_TEMPH BIT23 |
| CR2 Register Bits. More... | |
| #define | PWR_CR2_TEMPL BIT22 |
| temperature level monitoring versus low threshold More... | |
| #define | PWR_CR2_BRRDY BIT16 |
| backup regulator ready More... | |
| #define | PWR_CR2_MONEN BIT4 |
| V BAT and temperature monitoring enable. More... | |
| #define | PWR_CR2_BREN BIT0 |
| backup regulator enable More... | |
| #define | PWR_CR3_USB33RDY BIT26 |
| CR3 Register Bits. More... | |
| #define | PWR_CR3_USBREGEN BIT25 |
| #define | PWR_CR3_USB33DEN BIT24 |
| #define | PWR_CR3_SMPSEXTRDY BIT16 |
| SMPS step-down converter external supply ready. More... | |
| #define | PWR_CR3_VBRS BIT9 |
| V BAT charging resistor selection More... | |
| #define | PWR_CR3_VBE BIT8 |
| V BAT charging enable. More... | |
| #define | PWR_CR3_SMPSLEVEL_VOS 0x0 |
| #define | PWR_CR3_SMPSLEVEL_1P8V 0x1 |
| #define | PWR_CR3_SMPSLEVEL_2P5V 0x2 |
| #define | PWR_CR3_SMPSLEVEL_SHIFT 4 |
| #define | PWR_CR3_SMPSLEVEL_MASK 0x3 |
| #define | PWR_CR3_SMPSEXTHP BIT3 |
| SMPS step-down converter external power delivery selection. More... | |
| #define | PWR_CR3_SCUEN BIT2 |
| #define | PWR_CR3_SMPSEN BIT2 |
| #define | PWR_CR3_LDOEN BIT1 |
| #define | PWR_CR3_BYPASS BIT0 |
| #define | PWR_D3CR_VOSRDY BIT13 |
| D3CR Register Bits. More... | |
| #define | PWR_D3CR_VOS_SHIFT 14 |
| #define | PWR_D3CR_VOS_MASK (0x03) |
| #define | PWR_D3CR_VOS_SCALE_0 (0x0) |
| VOS0 is implemented on STM32H72x/3x with simple VOS setting. More... | |
| #define | PWR_D3CR_VOS_SCALE_3 (0x1) |
| #define | PWR_D3CR_VOS_SCALE_2 (0x2) |
| #define | PWR_D3CR_VOS_SCALE_1 (0x3) |
| #define | PWR_SRDCR_VOSRDY BIT13 |
| SRDCR Register Bits. More... | |
| #define | PWR_SRDCR_VOS_SHIFT 14 |
| #define | PWR_SRDCR_VOS_MASK (0x03) |
| #define | PWR_SRDCR_VOS_SCALE_3 (0x0) |
| #define | PWR_SRDCR_VOS_SCALE_2 (0x1) |
| #define | PWR_SRDCR_VOS_SCALE_1 (0x2) |
| #define | PWR_SRDCR_VOS_SCALE_0 (0x3) |
Enumerations | |
| enum | pwr_sys_mode { PWR_SYS_SCU_LDO = 0 , PWR_SYS_SCU_BYPASS , PWR_SYS_LDO , PWR_SYS_SMPS_DIRECT , PWR_SYS_SMPS_LDO , PWR_SYS_EXT_SMPS_LDO , PWR_SYS_EXT_SMPS_LDO_BYP , PWR_SYS_BYPASS } |
| enum | pwr_svos_scale { PWR_SVOS_SCALE3 = PWR_CR1_SVOS_SCALE_3 << PWR_CR1_SVOS_SHIFT , PWR_SVOS_SCALE4 = PWR_CR1_SVOS_SCALE_4 << PWR_CR1_SVOS_SHIFT , PWR_SVOS_SCALE5 = PWR_CR1_SVOS_SCALE_5 << PWR_CR1_SVOS_SHIFT } |
| enum | pwr_vos_scale { PWR_VOS_SCALE_UNDEFINED = 0 , PWR_VOS_SCALE_0 , PWR_VOS_SCALE_1 , PWR_VOS_SCALE_2 , PWR_VOS_SCALE_3 } |
Functions | |
| void | pwr_set_mode_ldo (void) |
| Set power subsystem to utilize the LDO for CPU. More... | |
| void | pwr_set_mode_scu_ldo (void) |
| Specific STM32H742/43/50/53 LDO mode setting. More... | |
| void | pwr_set_mode_smps_ldo (bool supply_external, uint32_t smps_level, bool use_ldo) |
| Set power subsystem to utilize the SMPS run through the LDO for CPU. More... | |
| void | pwr_set_mode (enum pwr_sys_mode mode, uint8_t smps_level) |
| Set power system based on "System Supply Configurations" table in reference manual. More... | |
| void | pwr_set_mode_bypass (void) |
| Set power subsystem to bypass all internal supplies. More... | |
| void | pwr_set_mode_scu_bypass (void) |
| Specific STM32H742/43/50/53 Bypsass mode setting. More... | |
| void | pwr_set_svos_scale (enum pwr_svos_scale scale) |
| Set the voltage scaling/strength for the internal SMPS/LDO when in Stop mode. More... | |
| void | pwr_set_vos_scale (enum pwr_vos_scale scale) |
| Set the voltage scaling/strength for the internal SMPS/LDO while running. More... | |
1.9.4