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#define | RCC_CR MMIO32(RCC_BASE + 0x00) |
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#define | RCC_CFGR MMIO32(RCC_BASE + 0x04) |
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#define | RCC_CIR MMIO32(RCC_BASE + 0x08) |
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#define | RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) |
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#define | RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) |
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#define | RCC_AHBENR MMIO32(RCC_BASE + 0x14) |
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#define | RCC_APB2ENR MMIO32(RCC_BASE + 0x18) |
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#define | RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) |
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#define | RCC_BDCR MMIO32(RCC_BASE + 0x20) |
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#define | RCC_CSR MMIO32(RCC_BASE + 0x24) |
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#define | RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /*(**)*/ |
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#define | RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /*(**)*/ |
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#define | RCC_CR_PLL3RDY (1 << 29) /* (**) */ |
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#define | RCC_CR_PLL3ON (1 << 28) /* (**) */ |
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#define | RCC_CR_PLL2RDY (1 << 27) /* (**) */ |
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#define | RCC_CR_PLL2ON (1 << 26) /* (**) */ |
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#define | RCC_CR_PLLRDY (1 << 25) |
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#define | RCC_CR_PLLON (1 << 24) |
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#define | RCC_CR_CSSON (1 << 19) |
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#define | RCC_CR_HSEBYP (1 << 18) |
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#define | RCC_CR_HSERDY (1 << 17) |
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#define | RCC_CR_HSEON (1 << 16) |
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#define | RCC_CR_HSIRDY (1 << 1) |
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#define | RCC_CR_HSION (1 << 0) |
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#define | RCC_CFGR_OTGFSPRE (1 << 22) /* Connectivity line */ |
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#define | RCC_CFGR_USBPRE (1 << 22) /* LD,MD, HD, XL */ |
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#define | RCC_CFGR_PLLMUL_SHIFT 18 |
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#define | RCC_CFGR_PLLMUL (0xF << RCC_CFGR_PLLMUL_SHIFT) |
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#define | RCC_CFGR_PLLXTPRE (1 << 17) |
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#define | RCC_CFGR_PLLSRC (1 << 16) |
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#define | RCC_CFGR_ADCPRE_SHIFT 14 |
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#define | RCC_CFGR_ADCPRE (3 << RCC_CFGR_ADCPRE_SHIFT) |
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#define | RCC_CFGR_PPRE2_SHIFT 11 |
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#define | RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT) |
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#define | RCC_CFGR_PPRE1_SHIFT 8 |
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#define | RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT) |
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#define | RCC_CFGR_HPRE_SHIFT 4 |
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#define | RCC_CFGR_HPRE (0xF << RCC_CFGR_HPRE_SHIFT) |
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#define | RCC_CFGR_SWS_SHIFT 2 |
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#define | RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT) |
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#define | RCC_CFGR_SW_SHIFT 0 |
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#define | RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT) |
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#define | RCC_CFGR_MCO_SHIFT 24 |
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#define | RCC_CFGR_MCO_MASK 0xf |
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#define | RCC_CFGR_MCO_NOCLK 0x0 |
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#define | RCC_CFGR_MCO_SYSCLK 0x4 |
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#define | RCC_CFGR_MCO_HSI 0x5 |
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#define | RCC_CFGR_MCO_HSE 0x6 |
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#define | RCC_CFGR_MCO_PLL_DIV2 0x7 |
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#define | RCC_CFGR_MCO_PLL2 0x8 /* (**) */ |
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#define | RCC_CFGR_MCO_PLL3_DIV2 0x9 /* (**) */ |
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#define | RCC_CFGR_MCO_XT1 0xa /* (**) */ |
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#define | RCC_CFGR_MCO_PLL3 0xb /* (**) */ |
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#define | RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 |
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#define | RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 |
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#define | RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0 |
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#define | RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 |
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#define | RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ |
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#define | RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 |
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#define | RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 |
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#define | RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 |
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#define | RCC_CFGR_PLLSRC_HSE_CLK 0x1 |
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#define | RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */ |
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#define | RCC_CFGR_ADCPRE_DIV2 0x0 |
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#define | RCC_CFGR_ADCPRE_DIV4 0x1 |
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#define | RCC_CFGR_ADCPRE_DIV6 0x2 |
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#define | RCC_CFGR_ADCPRE_DIV8 0x3 |
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#define | RCC_CFGR_PPRE2_SHIFT 11 |
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#define | RCC_CFGR_PPRE2_MASK 0x7 |
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#define | RCC_CFGR_PPRE1_SHIFT 8 |
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#define | RCC_CFGR_PPRE1_MASK 0x7 |
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#define | RCC_CFGR_PPRE_NODIV 0x0 |
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#define | RCC_CFGR_PPRE_DIV2 0x4 |
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#define | RCC_CFGR_PPRE_DIV4 0x5 |
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#define | RCC_CFGR_PPRE_DIV8 0x6 |
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#define | RCC_CFGR_PPRE_DIV16 0x7 |
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#define | RCC_CFGR_HPRE_NODIV 0x0 |
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#define | RCC_CFGR_HPRE_DIV2 0x8 |
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#define | RCC_CFGR_HPRE_DIV4 0x9 |
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#define | RCC_CFGR_HPRE_DIV8 0xa |
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#define | RCC_CFGR_HPRE_DIV16 0xb |
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#define | RCC_CFGR_HPRE_DIV64 0xc |
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#define | RCC_CFGR_HPRE_DIV128 0xd |
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#define | RCC_CFGR_HPRE_DIV256 0xe |
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#define | RCC_CFGR_HPRE_DIV512 0xf |
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#define | RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 |
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#define | RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 |
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#define | RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 |
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#define | RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 |
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#define | RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 |
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#define | RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 |
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#define | RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 |
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#define | RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 |
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#define | RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 |
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#define | RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 |
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#define | RCC_CFGR_PPRE2_HCLK_NODIV 0x0 |
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#define | RCC_CFGR_PPRE2_HCLK_DIV2 0x4 |
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#define | RCC_CFGR_PPRE2_HCLK_DIV4 0x5 |
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#define | RCC_CFGR_PPRE2_HCLK_DIV8 0x6 |
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#define | RCC_CFGR_PPRE2_HCLK_DIV16 0x7 |
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#define | RCC_CFGR_PPRE1_HCLK_NODIV 0x0 |
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#define | RCC_CFGR_PPRE1_HCLK_DIV2 0x4 |
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#define | RCC_CFGR_PPRE1_HCLK_DIV4 0x5 |
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#define | RCC_CFGR_PPRE1_HCLK_DIV8 0x6 |
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#define | RCC_CFGR_PPRE1_HCLK_DIV16 0x7 |
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#define | RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 |
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#define | RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 |
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#define | RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 |
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#define | RCC_CFGR_HPRE_SYSCLK_DIV8 0xa |
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#define | RCC_CFGR_HPRE_SYSCLK_DIV16 0xb |
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#define | RCC_CFGR_HPRE_SYSCLK_DIV64 0xc |
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#define | RCC_CFGR_HPRE_SYSCLK_DIV128 0xd |
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#define | RCC_CFGR_HPRE_SYSCLK_DIV256 0xe |
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#define | RCC_CFGR_HPRE_SYSCLK_DIV512 0xf |
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#define | RCC_CIR_CSSC (1 << 23) |
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#define | RCC_CIR_PLL3RDYC (1 << 22) /* (**) */ |
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#define | RCC_CIR_PLL2RDYC (1 << 21) /* (**) */ |
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#define | RCC_CIR_PLLRDYC (1 << 20) |
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#define | RCC_CIR_HSERDYC (1 << 19) |
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#define | RCC_CIR_HSIRDYC (1 << 18) |
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#define | RCC_CIR_LSERDYC (1 << 17) |
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#define | RCC_CIR_LSIRDYC (1 << 16) |
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#define | RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */ |
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#define | RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */ |
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#define | RCC_CIR_PLLRDYIE (1 << 12) |
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#define | RCC_CIR_HSERDYIE (1 << 11) |
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#define | RCC_CIR_HSIRDYIE (1 << 10) |
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#define | RCC_CIR_LSERDYIE (1 << 9) |
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#define | RCC_CIR_LSIRDYIE (1 << 8) |
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#define | RCC_CIR_CSSF (1 << 7) |
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#define | RCC_CIR_PLL3RDYF (1 << 6) /* (**) */ |
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#define | RCC_CIR_PLL2RDYF (1 << 5) /* (**) */ |
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#define | RCC_CIR_PLLRDYF (1 << 4) |
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#define | RCC_CIR_HSERDYF (1 << 3) |
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#define | RCC_CIR_HSIRDYF (1 << 2) |
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#define | RCC_CIR_LSERDYF (1 << 1) |
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#define | RCC_CIR_LSIRDYF (1 << 0) |
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#define | RCC_APB2RSTR_TIM17RST (1 << 18) |
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#define | RCC_APB2RSTR_TIM16RST (1 << 17) |
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#define | RCC_APB2RSTR_TIM15RST (1 << 16) |
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#define | RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */ |
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#define | RCC_APB2RSTR_USART1RST (1 << 14) |
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#define | RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */ |
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#define | RCC_APB2RSTR_SPI1RST (1 << 12) |
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#define | RCC_APB2RSTR_TIM1RST (1 << 11) |
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#define | RCC_APB2RSTR_ADC2RST (1 << 10) |
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#define | RCC_APB2RSTR_ADC1RST (1 << 9) |
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#define | RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */ |
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#define | RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */ |
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#define | RCC_APB2RSTR_IOPERST (1 << 6) |
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#define | RCC_APB2RSTR_IOPDRST (1 << 5) |
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#define | RCC_APB2RSTR_IOPCRST (1 << 4) |
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#define | RCC_APB2RSTR_IOPBRST (1 << 3) |
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#define | RCC_APB2RSTR_IOPARST (1 << 2) |
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#define | RCC_APB2RSTR_AFIORST (1 << 0) |
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#define | RCC_APB1RSTR_DACRST (1 << 29) |
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#define | RCC_APB1RSTR_PWRRST (1 << 28) |
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#define | RCC_APB1RSTR_BKPRST (1 << 27) |
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#define | RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ |
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#define | RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ |
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#define | RCC_APB1RSTR_CANRST |
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#define | RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ |
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#define | RCC_APB1RSTR_I2C2RST (1 << 22) |
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#define | RCC_APB1RSTR_I2C1RST (1 << 21) |
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#define | RCC_APB1RSTR_UART5RST (1 << 20) |
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#define | RCC_APB1RSTR_UART4RST (1 << 19) |
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#define | RCC_APB1RSTR_USART3RST (1 << 18) |
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#define | RCC_APB1RSTR_USART2RST (1 << 17) |
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#define | RCC_APB1RSTR_SPI3RST (1 << 15) |
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#define | RCC_APB1RSTR_SPI2RST (1 << 14) |
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#define | RCC_APB1RSTR_WWDGRST (1 << 11) |
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#define | RCC_APB1RSTR_TIM7RST (1 << 5) |
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#define | RCC_APB1RSTR_TIM6RST (1 << 4) |
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#define | RCC_APB1RSTR_TIM5RST (1 << 3) |
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#define | RCC_APB1RSTR_TIM4RST (1 << 2) |
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#define | RCC_APB1RSTR_TIM3RST (1 << 1) |
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#define | RCC_APB1RSTR_TIM2RST (1 << 0) |
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#define | RCC_AHBENR_ETHMACENRX (1 << 16) |
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#define | RCC_AHBENR_ETHMACENTX (1 << 15) |
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#define | RCC_AHBENR_ETHMACEN (1 << 14) |
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#define | RCC_AHBENR_OTGFSEN (1 << 12) |
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#define | RCC_AHBENR_SDIOEN (1 << 10) |
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#define | RCC_AHBENR_FSMCEN (1 << 8) |
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#define | RCC_AHBENR_CRCEN (1 << 6) |
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#define | RCC_AHBENR_FLITFEN (1 << 4) |
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#define | RCC_AHBENR_SRAMEN (1 << 2) |
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#define | RCC_AHBENR_DMA2EN (1 << 1) |
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#define | RCC_AHBENR_DMA1EN (1 << 0) |
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#define | RCC_APB2ENR_TIM17EN (1 << 18) |
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#define | RCC_APB2ENR_TIM16EN (1 << 17) |
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#define | RCC_APB2ENR_TIM15EN (1 << 16) |
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#define | RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ |
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#define | RCC_APB2ENR_USART1EN (1 << 14) |
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#define | RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ |
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#define | RCC_APB2ENR_SPI1EN (1 << 12) |
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#define | RCC_APB2ENR_TIM1EN (1 << 11) |
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#define | RCC_APB2ENR_ADC2EN (1 << 10) |
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#define | RCC_APB2ENR_ADC1EN (1 << 9) |
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#define | RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ |
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#define | RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ |
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#define | RCC_APB2ENR_IOPEEN (1 << 6) |
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#define | RCC_APB2ENR_IOPDEN (1 << 5) |
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#define | RCC_APB2ENR_IOPCEN (1 << 4) |
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#define | RCC_APB2ENR_IOPBEN (1 << 3) |
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#define | RCC_APB2ENR_IOPAEN (1 << 2) |
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#define | RCC_APB2ENR_AFIOEN (1 << 0) |
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#define | RCC_APB1ENR_DACEN (1 << 29) |
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#define | RCC_APB1ENR_PWREN (1 << 28) |
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#define | RCC_APB1ENR_BKPEN (1 << 27) |
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#define | RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ |
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#define | RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ |
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#define | RCC_APB1ENR_CANEN |
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#define | RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ |
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#define | RCC_APB1ENR_I2C2EN (1 << 22) |
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#define | RCC_APB1ENR_I2C1EN (1 << 21) |
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#define | RCC_APB1ENR_UART5EN (1 << 20) |
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#define | RCC_APB1ENR_UART4EN (1 << 19) |
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#define | RCC_APB1ENR_USART3EN (1 << 18) |
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#define | RCC_APB1ENR_USART2EN (1 << 17) |
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#define | RCC_APB1ENR_SPI3EN (1 << 15) |
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#define | RCC_APB1ENR_SPI2EN (1 << 14) |
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#define | RCC_APB1ENR_WWDGEN (1 << 11) |
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#define | RCC_APB1ENR_TIM7EN (1 << 5) |
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#define | RCC_APB1ENR_TIM6EN (1 << 4) |
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#define | RCC_APB1ENR_TIM5EN (1 << 3) |
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#define | RCC_APB1ENR_TIM4EN (1 << 2) |
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#define | RCC_APB1ENR_TIM3EN (1 << 1) |
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#define | RCC_APB1ENR_TIM2EN (1 << 0) |
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#define | RCC_BDCR_BDRST (1 << 16) |
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#define | RCC_BDCR_RTCEN (1 << 15) |
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#define | RCC_BDCR_LSEBYP (1 << 2) |
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#define | RCC_BDCR_LSERDY (1 << 1) |
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#define | RCC_BDCR_LSEON (1 << 0) |
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#define | RCC_CSR_LPWRRSTF (1 << 31) |
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#define | RCC_CSR_WWDGRSTF (1 << 30) |
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#define | RCC_CSR_IWDGRSTF (1 << 29) |
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#define | RCC_CSR_SFTRSTF (1 << 28) |
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#define | RCC_CSR_PORRSTF (1 << 27) |
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#define | RCC_CSR_PINRSTF (1 << 26) |
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#define | RCC_CSR_RMVF (1 << 24) |
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#define | RCC_CSR_RESET_FLAGS |
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#define | RCC_CSR_LSIRDY (1 << 1) |
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#define | RCC_CSR_LSION (1 << 0) |
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#define | RCC_AHBRSTR_ETHMACRST (1 << 14) |
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#define | RCC_AHBRSTR_OTGFSRST (1 << 12) |
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#define | RCC_CFGR2_I2S3SRC_SYSCLK 0x0 |
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#define | RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 |
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#define | RCC_CFGR2_I2S2SRC_SYSCLK 0x0 |
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#define | RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 |
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#define | RCC_CFGR2_I2S2SRC (1 << 17) |
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#define | RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 |
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#define | RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 |
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#define | RCC_CFGR2_PREDIV1SRC (1 << 16) |
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#define | RCC_CFGR2_PLL3MUL_SHIFT 12 |
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#define | RCC_CFGR2_PLL3MUL (0xF << RCC_CFGR2_PLL3MUL_SHIFT) |
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#define | RCC_CFGR2_PLL2MUL_SHIFT 8 |
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#define | RCC_CFGR2_PLL2MUL (0xF << RCC_CFGR2_PLL2MUL_SHIFT) |
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#define | RCC_CFGR2_PREDIV2_SHIFT 4 |
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#define | RCC_CFGR2_PREDIV2 (0xF << RCC_CFGR2_PREDIV2_SHIFT) |
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#define | RCC_CFGR2_PREDIV1_SHIFT 0 |
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#define | RCC_CFGR2_PREDIV1 (0xF << RCC_CFGR2_PREDIV1_SHIFT) |
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#define | RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 |
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#define | RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 |
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#define | RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 |
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#define | RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 |
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#define | RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa |
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#define | RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb |
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#define | RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc |
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#define | RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe |
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#define | RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf |
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#define | RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 |
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#define | RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 |
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#define | RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 |
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#define | RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 |
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#define | RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa |
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#define | RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb |
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#define | RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc |
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#define | RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe |
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#define | RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf |
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#define | RCC_CFGR2_PREDIV_NODIV 0x0 |
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#define | RCC_CFGR2_PREDIV_DIV2 0x1 |
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#define | RCC_CFGR2_PREDIV_DIV3 0x2 |
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#define | RCC_CFGR2_PREDIV_DIV4 0x3 |
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#define | RCC_CFGR2_PREDIV_DIV5 0x4 |
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#define | RCC_CFGR2_PREDIV_DIV6 0x5 |
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#define | RCC_CFGR2_PREDIV_DIV7 0x6 |
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#define | RCC_CFGR2_PREDIV_DIV8 0x7 |
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#define | RCC_CFGR2_PREDIV_DIV9 0x8 |
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#define | RCC_CFGR2_PREDIV_DIV10 0x9 |
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#define | RCC_CFGR2_PREDIV_DIV11 0xa |
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#define | RCC_CFGR2_PREDIV_DIV12 0xb |
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#define | RCC_CFGR2_PREDIV_DIV13 0xc |
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#define | RCC_CFGR2_PREDIV_DIV14 0xd |
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#define | RCC_CFGR2_PREDIV_DIV15 0xe |
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#define | RCC_CFGR2_PREDIV_DIV16 0xf |
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#define | RCC_CFGR2_PREDIV2_NODIV 0x0 |
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#define | RCC_CFGR2_PREDIV2_DIV2 0x1 |
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#define | RCC_CFGR2_PREDIV2_DIV3 0x2 |
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#define | RCC_CFGR2_PREDIV2_DIV4 0x3 |
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#define | RCC_CFGR2_PREDIV2_DIV5 0x4 |
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#define | RCC_CFGR2_PREDIV2_DIV6 0x5 |
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#define | RCC_CFGR2_PREDIV2_DIV7 0x6 |
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#define | RCC_CFGR2_PREDIV2_DIV8 0x7 |
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#define | RCC_CFGR2_PREDIV2_DIV9 0x8 |
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#define | RCC_CFGR2_PREDIV2_DIV10 0x9 |
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#define | RCC_CFGR2_PREDIV2_DIV11 0xa |
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#define | RCC_CFGR2_PREDIV2_DIV12 0xb |
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#define | RCC_CFGR2_PREDIV2_DIV13 0xc |
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#define | RCC_CFGR2_PREDIV2_DIV14 0xd |
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#define | RCC_CFGR2_PREDIV2_DIV15 0xe |
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#define | RCC_CFGR2_PREDIV2_DIV16 0xf |
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#define | _REG_BIT(base, bit) (((base) << 5) + (bit)) |
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