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| #define | QUADSPI_CR MMIO32(QUADSPI_BASE + 0x0U) |
| | QUADSPI Control register. More...
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| #define | QUADSPI_DCR MMIO32(QUADSPI_BASE + 0x4U) |
| | QUADSPI Device Configuration. More...
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| #define | QUADSPI_SR MMIO32(QUADSPI_BASE + 0x8U) |
| | QUADSPI Status Register. More...
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| #define | QUADSPI_FCR MMIO32(QUADSPI_BASE + 0xCU) |
| | QUADSPI Flag Clear Register. More...
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| #define | QUADSPI_DLR MMIO32(QUADSPI_BASE + 0x10U) |
| | QUADSPI Data Length Register. More...
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| #define | QUADSPI_CCR MMIO32(QUADSPI_BASE + 0x14U) |
| | QUADSPI Communication Configuration Register. More...
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| #define | QUADSPI_AR MMIO32(QUADSPI_BASE + 0x18U) |
| | QUADSPI address register. More...
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| #define | QUADSPI_ABR MMIO32(QUADSPI_BASE + 0x1CU) |
| | QUADSPI alternate bytes register. More...
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| #define | QUADSPI_DR MMIO32(QUADSPI_BASE + 0x20U) |
| | QUADSPI data register. More...
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| #define | QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U) |
| | BYTE addressable version for fetching bytes from the interface. More...
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| #define | QUADSPI_PSMKR MMIO32(QUADSPI_BASE + 0x24U) |
| | QUADSPI polling status. More...
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| #define | QUADSPI_PSMAR MMIO32(QUADSPI_BASE + 0x28U) |
| | QUADSPI polling status match. More...
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| #define | QUADSPI_PIR MMIO32(QUADSPI_BASE + 0x2CU) |
| | QUADSPI polling interval register. More...
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| #define | QUADSPI_LPTR MMIO32(QUADSPI_BASE + 0x30U |
| | QUADSPI low power timeout. More...
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| #define | QUADSPI_CR_PRESCALE_MASK 0xff |
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| #define | QUADSPI_CR_PRESCALE_SHIFT 24 |
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| #define | QUADSPI_CR_PMM (1 << 23) |
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| #define | QUADSPI_CR_APMS (1 << 22) |
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| #define | QUADSPI_CR_TOIE (1 << 20) |
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| #define | QUADSPI_CR_SMIE (1 << 19) |
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| #define | QUADSPI_CR_FTIE (1 << 18) |
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| #define | QUADSPI_CR_TCIE (1 << 17) |
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| #define | QUADSPI_CR_TEIE (1 << 16) |
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| #define | QUADSPI_CR_FTHRES_MASK 0x1f |
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| #define | QUADSPI_CR_FTHRES_SHIFT 8 |
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| #define | QUADSPI_CR_FSEL (1 << 7) |
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| #define | QUADSPI_CR_DFM (1 << 6) |
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| #define | QUADSPI_CR_SSHIFT (1 << 4) |
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| #define | QUADSPI_CR_TCEN (1 << 3) |
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| #define | QUADSPI_CR_ABORT (1 << 1) |
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| #define | QUADSPI_CR_EN (1 << 0) |
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| #define | QUADSPI_DCR_FSIZE_MASK 0x1f |
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| #define | QUADSPI_DCR_FSIZE_SHIFT 16 |
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| #define | QUADSPI_DCR_CSHT_MASK 0x7 |
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| #define | QUADSPI_DCR_CSHT_SHIFT 8 |
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| #define | QUADSPI_DCR_CKMODE (1 << 0) |
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| #define | QUADSPI_SR_FLEVEL_MASK 0x3f |
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| #define | QUADSPI_SR_FLEVEL_SHIFT 8 |
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| #define | QUADSPI_SR_BUSY (1 << 5) |
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| #define | QUADSPI_SR_TOF (1 << 4) |
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| #define | QUADSPI_SR_SMF (1 << 3) |
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| #define | QUADSPI_SR_FTF (1 << 2) |
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| #define | QUADSPI_SR_TCF (1 << 1) |
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| #define | QUADSPI_SR_TEF (1 << 0) |
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| #define | QUADSPI_FCR_CTOF (1 << 4) |
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| #define | QUADSPI_FCR_CSMF (1 << 3) |
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| #define | QUADSPI_FCR_CTCF (1 << 1) |
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| #define | QUADSPI_FCR_CTEF (1 << 0) |
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| #define | QUADSPI_CCR_DDRM (1 << 31) |
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| #define | QUADSPI_CCR_DHHC (1 << 30) |
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| #define | QUADSPI_CCR_SIOO (1 << 28) |
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| #define | QUADSPI_CCR_FMODE_MASK 0x3 |
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| #define | QUADSPI_CCR_FMODE_SHIFT 26 |
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| #define | QUADSPI_CCR_DMODE_MASK 0x3 |
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| #define | QUADSPI_CCR_DMODE_SHIFT 24 |
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| #define | QUADSPI_CCR_DCYC_MASK 0x1f |
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| #define | QUADSPI_CCR_DCYC_SHIFT 18 |
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| #define | QUADSPI_CCR_ABSIZE_MASK 0x3 |
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| #define | QUADSPI_CCR_ABSIZE_SHIFT 16 |
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| #define | QUADSPI_CCR_ABMODE_MASK 0x3 |
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| #define | QUADSPI_CCR_ABMODE_SHIFT 14 |
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| #define | QUADSPI_CCR_ADSIZE_MASK 0x3 |
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| #define | QUADSPI_CCR_ADSIZE_SHIFT 12 |
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| #define | QUADSPI_CCR_ADMODE_MASK 0x3 |
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| #define | QUADSPI_CCR_ADMODE_SHIFT 10 |
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| #define | QUADSPI_CCR_IMODE_MASK 0x3 |
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| #define | QUADSPI_CCR_IMODE_SHIFT 8 |
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| #define | QUADSPI_CCR_INST_MASK 0xff |
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| #define | QUADSPI_CCR_INST_SHIFT 0 |
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| #define | QUADSPI_CCR_MODE_NONE 0 |
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| #define | QUADSPI_CCR_MODE_1LINE 1 |
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| #define | QUADSPI_CCR_MODE_2LINE 2 |
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| #define | QUADSPI_CCR_MODE_4LINE 3 |
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| #define | QUADSPI_CCR_FMODE_IWRITE 0 |
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| #define | QUADSPI_CCR_FMODE_IREAD 1 |
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| #define | QUADSPI_CCR_FMODE_APOLL 2 |
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| #define | QUADSPI_CCR_FMODE_MEMMAP 3 |
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