|
| #define | DAC_CCR(dac) MMIO32((dac) + 0x38) |
| | DAC calibration control register (DAC_CCR) More...
|
| |
| #define | DAC_MCR(dac) MMIO32((dac) + 0x3C) |
| | DAC mode control register (DAC_MCR) More...
|
| |
| #define | DAC_SHSR1(dac) MMIO32((dac) + 0x40) |
| | DAC channel1 sample and hold sample time register (DAC_SHSR1) More...
|
| |
| #define | DAC_SHSR2(dac) MMIO32((dac) + 0x44) |
| | DAC channel2 sample and hold sample time register (DAC_SHSR2) More...
|
| |
| #define | DAC_SHHR(dac) MMIO32((dac) + 0x48) |
| | DAC sample and hold time register (DAC_SHHR) More...
|
| |
| #define | DAC_SHRR(dac) MMIO32((dac) + 0x4C) |
| | DAC sample and hold refresh time register (DAC_SHRR) More...
|
| |
| #define | DAC_STR1(dac) MMIO32((dac) + 0x58) |
| | DAC channel1 sawtooth register (DAC_STR1) More...
|
| |
| #define | DAC_STR2(dac) MMIO32((dac) + 0x5C) |
| | DAC channel2 sawtooth register (DAC_STR2) More...
|
| |
| #define | DAC_STMODR(dac) MMIO32((dac) + 0x60) |
| | DAC sawtooth mode register (DAC_STMODR) More...
|
| |
| #define | DAC_CR_CEN2 (1 << 30) |
| | CEN2: DAC channel2 calibration enable. More...
|
| |
| #define | DAC_CR_TSEL2_SHIFT 18 |
| |
| #define | DAC_CR_TSEL2_SW (0x0 << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_T6 (0x7 << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_T3 (0x8 << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_HRR1 (0x9 << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_HRR2 (0xA << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_HRR3 (0xB << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_HRR4 (0xC << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_HRR5 (0xD << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_HRR6 (0xE << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TSEL2_HR2 (0xF << DAC_CR_TSEL2_SHIFT) |
| |
| #define | DAC_CR_TEN2 (1 << 17) |
| |
| #define | DAC_CR_CEN1 (1 << 14) |
| |
| #define | DAC_CR_TSEL1_SHIFT 2 |
| |
| #define | DAC_CR_TSEL1_CK (0x0 << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_T6 (0x7 << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_T3 (0x8 << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_HRR1 (0x9 << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_HRR2 (0xA << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_HRR3 (0xB << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_HRR4 (0xC << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_HRR5 (0xD << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_HRR6 (0xE << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TSEL1_HR3 (0xF << DAC_CR_TSEL1_SHIFT) |
| |
| #define | DAC_CR_TEN1 (1 << 1) |
| | TEN1: DAC channel1 trigger enable. More...
|
| |
| #define | DAC_SWTRIGR_SWTRIGB2 (1 << 17) |
| | SWTRIG2: DAC channel2 software trigger B. More...
|
| |
| #define | DAC_SWTRIGR_SWTRIGB1 (1 << 16) |
| | SWTRIG1: DAC channel1 software trigger B. More...
|
| |
| #define | DAC_DOR1_DACC1DORB_SHIFT 16 |
| |
| #define | DAC_DOR1_DACC1DORB_MASK 0xFFF |
| |
| #define | DAC_DOR2_DACC2DORB_SHIFT 16 |
| |
| #define | DAC_DOR2_DACC2DORB_MASK 0xFFF |
| |
| #define | DAC_SR_BWST2 (1 << 31) |
| | DAC channel2 busy writing sample time flag. More...
|
| |
| #define | DAC_SR_CAL_FLAG2 (1 << 30) |
| | DAC channel2 calibration offset status. More...
|
| |
| #define | DAC_SR_DMAUDR2 (1 << 29) |
| | DAC channel2 DMA underrun flag. More...
|
| |
| #define | DAC_SR_DORSTAT2 (1 << 28) |
| | DAC channel2 output register status bit. More...
|
| |
| #define | DAC_SR_DAC2RDY (1 << 27) |
| | DAC channel2 ready status bit. More...
|
| |
| #define | DAC_SR_BWST1 (1 << 15) |
| | DAC channel1 busy writing sample time flag. More...
|
| |
| #define | DAC_SR_CAL_FLAG1 (1 << 14) |
| | DAC channel1 calibration offset status. More...
|
| |
| #define | DAC_SR_DMAUDR1 (1 << 13) |
| | DAC channel1 DMA underrun flag. More...
|
| |
| #define | DAC_SR_DORSTAT1 (1 << 12) |
| | DAC channel1 output register status bit. More...
|
| |
| #define | DAC_SR_DAC1RDY (1 << 11) |
| | DAC channel1 ready status bit. More...
|
| |
| #define | DAC_CCR_OTRIM2_SHIFT 16 |
| |
| #define | DAC_CCR_OTRIM2_MASK 0x1F |
| |
| #define | DAC_CCR_OTRIM1_SHIFT 0 |
| |
| #define | DAC_CCR_OTRIM1_MASK 0x1F |
| |
| #define | DAC_MCR_SINFORMAT2 (1 << 25) |
| | Enable signed format for DAC channel2. More...
|
| |
| #define | DAC_MCR_DMADOUBLE2 (1 << 24) |
| | DAC channel2 DMA double data mode. More...
|
| |
| #define | DAC_MCR_MODE2_SHIFT 16 |
| | MODE2[2:0]: DAC channel2 mode. More...
|
| |
| #define | DAC_MCR_MODE2_E_BUFF (0x0 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_MODE2_EP_BUFF (0x1 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_MODE2_E (0x2 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_MODE2_EP (0x3 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_MODE2_SH_E_BUFF (0x4 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_MODE2_SH_EP_BUFF (0x5 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_MODE2_SH_E (0x6 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_MODE2_SH_EP (0x7 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_MODE2_PERIPHERAL (0x1 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_MODE2_UNBUFFERED (0x2 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_MODE2_SAMPLEHOLD (0x4 << DAC_MCR_MODE2_SHIFT) |
| |
| #define | DAC_MCR_HFSEL_SHIFT 14 |
| |
| #define | DAC_MCR_HFSEL_MASK 0x3 |
| |
| #define | DAC_MCR_HFSEL_DIS (0x0 << DAC_MCR_HFSEL_SHIFT) |
| |
| #define | DAC_MCR_HFSEL_AHB80 (0x1 << DAC_MCR_HFSEL_SHIFT) |
| |
| #define | DAC_MCR_HFSEL_AHB160 (0x2 << DAC_MCR_HFSEL_SHIFT) |
| |
| #define | DAC_MCR_SINFORMAT1 (1 << 9) |
| | Enable signed format for DAC channel1. More...
|
| |
| #define | DAC_MCR_DMADOUBLE1 (1 << 8) |
| | DAC channel1 DMA double data mode. More...
|
| |
| #define | DAC_MCR_MODE1_SHIFT 0 |
| |
| #define | DAC_MCR_MODE1_E_BUFF (0x0 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_MCR_MODE1_EP_BUFF (0x1 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_MCR_MODE1_E (0x2 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_MCR_MODE1_EP (0x3 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_MCR_MODE1_SH_E_BUFF (0x4 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_MCR_MODE1_SH_EP_BUFF (0x5 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_MCR_MODE1_SH_E (0x6 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_MCR_MODE1_SH_EP (0x7 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_MCR_MODE1_PERIPHERAL (0x1 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_MCR_MODE1_UNBUFFERED (0x2 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_MCR_MODE1_SAMPLEHOLD (0x4 << DAC_MCR_MODE1_SHIFT) |
| |
| #define | DAC_SHSR1_TSAMPLE1_SHIFT 0 |
| |
| #define | DAC_SHSR1_TSAMPLE1_MASK 0x1FF |
| |
| #define | DAC_SHSR2_TSAMPLE2_SHIFT 0 |
| |
| #define | DAC_SHSR2_TSAMPLE2_MASK 0x1FF |
| |
| #define | DAC_SHHSR_THOLD2_SHIFT 16 |
| |
| #define | DAC_SHHSR_THOLD2_MASK 0x1FF |
| |
| #define | DAC_SHHSR_THOLD1_SHIFT 0 |
| |
| #define | DAC_SHHSR_THOLD1_MASK 0x1FF |
| |
| #define | DAC_STR1_STINCDATA1_SHIFT 16 |
| |
| #define | DAC_STR1_STINCDATA1_MASK 0xFFFF |
| |
| #define | DAC_STR1_STDIR1_SHIFT 12 |
| |
| #define | DAC_STR1_STDIR1_DEC (0x0 << DAC_STR_STDIR1_SHIFT) |
| |
| #define | DAC_STR1_STDIR1_INC (0x1 << DAC_STR_STDIR1_SHIFT) |
| |
| #define | DAC_STR1_STRSTDATA1_SHIFT 0 |
| |
| #define | DAC_STR1_STRSTDATA1_MASK 0xFFF |
| |
| #define | DAC_STR2_STINCDATA2_SHIFT 16 |
| |
| #define | DAC_STR2_STINCDATA2_MASK 0xFFFF |
| |
| #define | DAC_STR2_STDIR2_SHIFT 12 |
| |
| #define | DAC_STR2_STDIR2_DEC (0x0 << DAC_STR_STDIR2_SHIFT) |
| |
| #define | DAC_STR2_STDIR2_INC (0x1 << DAC_STR_STDIR2_SHIFT) |
| |
| #define | DAC_STR2_STRSTDATA2_SHIFT 0 |
| |
| #define | DAC_STR2_STRSTDATA2_MASK 0xFFF |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_SHIFT 24 |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_SW (0x0 << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T1 (0x1 << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T2 (0x2 << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T3 (0x3 << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T4 (0x4 << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T5 (0x5 << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T6 (0x6 << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T7 (0x7 << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T8 (0x8 << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T9 (0x9 << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T10 (0xA << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T11 (0xB << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T12 (0xC << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T13 (0xD << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T14 (0xE << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL2_T15 (0xF << DAC_STMODR_STINCTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_SHIFT 16 |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_SW (0x0 << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T1 (0x1 << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T2 (0x2 << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T3 (0x3 << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T4 (0x4 << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T5 (0x5 << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T6 (0x6 << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T7 (0x7 << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T8 (0x8 << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T9 (0x9 << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T10 (0xA << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T11 (0xB << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T12 (0xC << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T13 (0xD << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T14 (0xE << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL2_T15 (0xF << DAC_STMODR_STRSTTRIGSEL2_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_SHIFT 8 |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_SW (0x0 << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T1 (0x1 << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T2 (0x2 << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T3 (0x3 << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T4 (0x4 << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T5 (0x5 << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T6 (0x6 << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T7 (0x7 << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T8 (0x8 << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T9 (0x9 << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T10 (0xA << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T11 (0xB << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T12 (0xC << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T13 (0xD << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T14 (0xE << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STINCTRIGSEL1_T15 (0xF << DAC_STMODR_STINCTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_SHIFT 0 |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_SW (0x0 << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T1 (0x1 << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T2 (0x2 << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T3 (0x3 << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T4 (0x4 << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T5 (0x5 << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T6 (0x6 << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T7 (0x7 << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T8 (0x8 << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T9 (0x9 << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T10 (0xA << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T11 (0xB << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T12 (0xC << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T13 (0xD << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T14 (0xE << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
| #define | DAC_STMODR_STRSTTRIGSEL1_T15 (0xF << DAC_STMODR_STRSTTRIGSEL1_SHIFT) |
| |
